781 lines
17 KiB
C
781 lines
17 KiB
C
/*
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* e1.c
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*
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* Copyright (C) 2019-2020 Sylvain Munaut <tnt@246tNt.com>
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* SPDX-License-Identifier: GPL-3.0-or-later
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*/
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#include <stdint.h>
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#include <stdbool.h>
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#include <string.h>
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#include "config.h"
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#include "console.h"
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#include "e1.h"
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#include "e1_hw.h"
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#include "dma.h"
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#include "led.h" // FIXME
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#include "misc.h"
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#include "utils.h"
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// HW access
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// ---------
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static volatile struct e1_core * const e1_regs_base = (void *)(E1_CORE_BASE);
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static volatile uint8_t * const e1_data = (void *)(E1_DATA_BASE);
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// Helpers
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// -------
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static unsigned int
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e1_data_ofs(int mf, int frame, int ts)
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{
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return (mf << 9) | (frame << 5) | ts;
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}
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static volatile uint8_t *
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e1_data_ptr(int mf, int frame, int ts)
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{
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return &e1_data[e1_data_ofs(mf, frame, ts)];
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}
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// FIFOs
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// -----
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/* Note: FIFO works at 'frame' level (i.e. 32 bytes) */
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struct e1_fifo {
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/* Buffer zone associated with the FIFO */
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unsigned int base;
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unsigned int mask;
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/* Pointers / Levels */
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unsigned int wptr[2]; /* 0=committed 1=allocated */
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unsigned int rptr[2]; /* 0=discared 1=peeked */
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};
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/* Utils */
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static void
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e1f_init(struct e1_fifo *fifo, unsigned int base, unsigned int len)
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{
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memset(fifo, 0x00, sizeof(struct e1_fifo));
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fifo->base = base;
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fifo->mask = len - 1;
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}
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static void
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e1f_reset(struct e1_fifo *fifo)
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{
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fifo->wptr[0] = fifo->wptr[1] = 0;
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fifo->rptr[0] = fifo->rptr[1] = 0;
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}
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static unsigned int
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e1f_allocd_frames(struct e1_fifo *fifo)
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{
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/* Number of frames that are allocated (i.e. where we can't write to) */
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return (fifo->wptr[1] - fifo->rptr[0]) & fifo->mask;
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}
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static unsigned int
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e1f_valid_frames(struct e1_fifo *fifo)
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{
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/* Number of valid frames */
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return (fifo->wptr[0] - fifo->rptr[0]) & fifo->mask;
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}
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static unsigned int
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e1f_unseen_frames(struct e1_fifo *fifo)
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{
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/* Number of valid frames that haven't been peeked yet */
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return (fifo->wptr[0] - fifo->rptr[1]) & fifo->mask;
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}
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static unsigned int
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e1f_free_frames(struct e1_fifo *fifo)
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{
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/* Number of frames that aren't allocated */
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return (fifo->rptr[0] - fifo->wptr[1] - 1) & fifo->mask;
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}
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static unsigned int
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e1f_ofs_to_dma(unsigned int ofs)
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{
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/* DMA address are 32-bits word address. Offsets are 32 byte address */
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return (ofs << 3);
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}
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static unsigned int
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e1f_ofs_to_mf(unsigned int ofs)
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{
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/* E1 Buffer Descriptors are always multiframe aligned */
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return (ofs >> 4);
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}
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/* Debug */
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static void
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e1f_debug(struct e1_fifo *fifo, const char *name)
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{
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unsigned int la, lv, lu, lf;
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la = e1f_allocd_frames(fifo);
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lv = e1f_valid_frames(fifo);
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lu = e1f_unseen_frames(fifo);
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lf = e1f_free_frames(fifo);
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printf("%s: R: %u / %u | W: %u / %u | A:%u V:%u U:%u F:%u\n",
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name,
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fifo->rptr[0], fifo->rptr[1], fifo->wptr[0], fifo->wptr[1],
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la, lv, lu, lf
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);
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}
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/* Frame level read/write */
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static unsigned int
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e1f_frame_write(struct e1_fifo *fifo, unsigned int *ofs, unsigned int max_frames)
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{
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unsigned int lf, le;
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lf = e1f_free_frames(fifo);
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le = fifo->mask - fifo->wptr[0] + 1;
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if (max_frames > le)
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max_frames = le;
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if (max_frames > lf)
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max_frames = lf;
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*ofs = fifo->base + fifo->wptr[0];
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fifo->wptr[1] = fifo->wptr[0] = (fifo->wptr[0] + max_frames) & fifo->mask;
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return max_frames;
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}
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static unsigned int
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e1f_frame_read(struct e1_fifo *fifo, unsigned int *ofs, unsigned int max_frames)
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{
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unsigned int lu, le;
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lu = e1f_unseen_frames(fifo);
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le = fifo->mask - fifo->rptr[1] + 1;
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if (max_frames > le)
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max_frames = le;
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if (max_frames > lu)
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max_frames = lu;
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*ofs = fifo->base + fifo->rptr[1];
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fifo->rptr[0] = fifo->rptr[1] = (fifo->rptr[1] + max_frames) & fifo->mask;
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return max_frames;
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}
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/* MultiFrame level split read/write */
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static bool
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e1f_multiframe_write_prepare(struct e1_fifo *fifo, unsigned int *ofs)
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{
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unsigned int lf;
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lf = e1f_free_frames(fifo);
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if (lf < 16)
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return false;
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*ofs = fifo->base + fifo->wptr[1];
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fifo->wptr[1] = (fifo->wptr[1] + 16) & fifo->mask;
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return true;
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}
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static void
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e1f_multiframe_write_commit(struct e1_fifo *fifo)
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{
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fifo->wptr[0] = (fifo->wptr[0] + 16) & fifo->mask;
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}
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static bool
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e1f_multiframe_read_peek(struct e1_fifo *fifo, unsigned int *ofs)
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{
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unsigned int lu;
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lu = e1f_unseen_frames(fifo);
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if (lu < 16)
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return false;
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*ofs = fifo->base + fifo->rptr[1];
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fifo->rptr[1] = (fifo->rptr[1] + 16) & fifo->mask;
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return true;
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}
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static void
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e1f_multiframe_read_discard(struct e1_fifo *fifo)
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{
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fifo->rptr[0] = (fifo->rptr[0] + 16) & fifo->mask;
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}
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static void
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e1f_multiframe_empty_tail(struct e1_fifo *fifo)
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{
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fifo->rptr[0] = fifo->rptr[1] = (fifo->wptr[0] & ~15);
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}
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static void
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e1f_multiframe_empty_head(struct e1_fifo *fifo)
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{
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fifo->wptr[0] = fifo->wptr[1] = ((fifo->rptr[1] + 15) & ~15);
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}
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// Main logic
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// ----------
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enum e1_pipe_state {
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IDLE = 0, /* not running */
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STARTING = 1, /* after e1_start(), waiting for priming */
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RUN = 2, /* normal operation */
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RECOVER = 3, /* after underflow, overflow or alignment error */
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SHUTDOWN = 4, /* after e1_stop(), waiting for shutdown */
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};
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struct e1_state {
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struct {
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struct {
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uint32_t cfg;
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uint32_t val;
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} cr;
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struct e1_fifo fifo;
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int in_flight;
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enum e1_pipe_state state;
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} rx;
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struct {
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struct {
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uint32_t cfg;
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uint32_t val;
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} cr;
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struct e1_fifo fifo;
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int in_flight;
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enum e1_pipe_state state;
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} tx;
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struct {
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uint16_t rx_pulse;
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uint16_t rx_sample;
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uint16_t rx_one;
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uint16_t _val;
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} linemon;
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struct e1_error_count errors;
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};
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static struct e1_state g_e1[NUM_E1_PORTS];
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static volatile struct e1_core *
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_get_regs(int port)
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{
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if ((port < 0) || (port >= NUM_E1_PORTS))
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panic("_get_regs invalid port %d", port);
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return &e1_regs_base[port];
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}
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static struct e1_state *
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_get_state(int port)
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{
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if ((port < 0) || (port >= NUM_E1_PORTS))
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panic("_get_state invalid port %d", port);
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return &g_e1[port];
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}
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#define RXCR_PERMITTED ( \
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E1_RX_CR_MODE_MASK )
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#define TXCR_PERMITTED ( \
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E1_TX_CR_MODE_MASK | \
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E1_TX_CR_TICK_MASK | \
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E1_TX_CR_ALARM | \
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E1_TX_CR_LOOPBACK | \
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E1_TX_CR_LOOPBACK_CROSS )
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static void
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_e1_update_cr_val(int port)
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{
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struct e1_state *e1 = _get_state(port);
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/* RX */
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if (e1->rx.state == IDLE) {
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/* "Off" state: Force MFA mode to detect remote side */
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e1->rx.cr.val = (e1->rx.cr.cfg & ~E1_RX_CR_MODE_MASK) | E1_RX_CR_ENABLE | E1_RX_CR_MODE_MFA;
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} else {
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/* "On state: Enabled + User config */
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e1->rx.cr.val = e1->rx.cr.cfg | E1_RX_CR_ENABLE;
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}
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/* TX */
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if (e1->tx.state == IDLE) {
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/* "Off" state: We TX only AIS */
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e1->tx.cr.val = (e1->tx.cr.cfg & ~(E1_TX_CR_MODE_MASK | E1_TX_CR_ALARM)) | E1_TX_CR_ENABLE | E1_TX_CR_MODE_TRSP;
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} else {
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/* "On state: Enabled + User config */
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e1->tx.cr.val = e1->tx.cr.cfg | E1_TX_CR_ENABLE;
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}
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}
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void
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e1_init(int port, uint16_t rx_cr, uint16_t tx_cr)
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{
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volatile struct e1_core *e1_regs = _get_regs(port);
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struct e1_state *e1 = _get_state(port);
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/* Global state init */
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memset(e1, 0x00, sizeof(struct e1_state));
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/* Initialize FIFOs */
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e1f_init(&e1->rx.fifo, (512 * port) + 0, 256);
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e1f_init(&e1->tx.fifo, (512 * port) + 256, 256);
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/* Flow state */
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e1->rx.state = IDLE;
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e1->tx.state = IDLE;
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/* Set config registers */
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e1->rx.cr.cfg = rx_cr & RXCR_PERMITTED;
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e1->tx.cr.cfg = tx_cr & TXCR_PERMITTED;
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_e1_update_cr_val(port);
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e1_regs->rx.csr = e1->rx.cr.val;
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e1_regs->tx.csr = e1->tx.cr.val;
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}
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void
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e1_rx_config(int port, uint16_t cr)
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{
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volatile struct e1_core *e1_regs = _get_regs(port);
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struct e1_state *e1 = _get_state(port);
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e1->rx.cr.cfg = cr & RXCR_PERMITTED;
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_e1_update_cr_val(port);
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e1_regs->rx.csr = e1->rx.cr.val;
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}
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void
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e1_tx_config(int port, uint16_t cr)
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{
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volatile struct e1_core *e1_regs = _get_regs(port);
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struct e1_state *e1 = _get_state(port);
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e1->tx.cr.cfg = cr & TXCR_PERMITTED;
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_e1_update_cr_val(port);
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e1_regs->tx.csr = e1->tx.cr.val;
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}
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void
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e1_start(int port)
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{
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volatile struct e1_core *e1_regs = _get_regs(port);
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struct e1_state *e1 = _get_state(port);
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/* RX */
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switch (e1->rx.state) {
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case IDLE:
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/* We're idle, clear fifo and normal start */
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e1f_reset(&e1->rx.fifo);
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e1->rx.state = STARTING;
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break;
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case SHUTDOWN:
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/* Shutdown is pending, go to recover which is basically
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* a shutdown with auto-restart */
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e1->rx.state = RECOVER;
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break;
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default:
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/* Huh ... hope for the best */
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printf("[!] E1 RX start while not stopped ...\n");
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}
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/* TX */
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switch (e1->tx.state) {
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case IDLE:
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/* We're idle, clear fifo and normal start */
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e1f_reset(&e1->tx.fifo);
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e1->tx.state = STARTING;
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break;
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case SHUTDOWN:
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/* Shutdown is pending, go to recover which is basically
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* a shutdown with auto-restart */
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e1->tx.state = RECOVER;
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/* We also prune any pending data in FIFO that's not
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* already queued to hw */
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e1f_multiframe_empty_head(&e1->rx.fifo);
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break;
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default:
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/* Huh ... hope for the best */
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printf("[!] E1 TX start while not stopped ...\n");
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}
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/* Update CRs */
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_e1_update_cr_val(port);
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e1_regs->rx.csr = e1->rx.cr.val | E1_RX_CR_OVFL_CLR;
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e1_regs->tx.csr = e1->tx.cr.val | E1_TX_CR_UNFL_CLR;
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}
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void
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e1_stop(int port)
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{
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struct e1_state *e1 = _get_state(port);
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/* Flow state */
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e1->rx.state = SHUTDOWN;
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e1->tx.state = SHUTDOWN;
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/* Nothing else to do, e1_poll will stop submitting data and
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* transition to IDLE when everything in-flight is done */
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}
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unsigned int
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e1_rx_need_data(int port, unsigned int usb_addr, unsigned int max_frames, unsigned int *pos)
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{
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struct e1_state *e1 = _get_state(port);
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bool rai_received = false;
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bool rai_possible = false;
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unsigned int ofs;
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int tot_frames = 0;
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int n_frames, i;
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while (max_frames) {
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/* Get some data from the FIFO */
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n_frames = e1f_frame_read(&e1->rx.fifo, &ofs, max_frames);
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if (!n_frames)
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break;
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/* Give pos */
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if (pos) {
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*pos = ofs & e1->rx.fifo.mask;
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pos = NULL;
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}
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/* Copy from FIFO to USB */
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dma_exec(e1f_ofs_to_dma(ofs), usb_addr, n_frames * (32 / 4), false, NULL, NULL);
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/* Prepare Next */
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usb_addr += n_frames * (32 / 4);
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max_frames -= n_frames;
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tot_frames += n_frames;
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/* While DMA is running: Determine if remote end indicates any alarms */
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for (i = 0; i < n_frames; i++) {
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unsigned int frame_nr = ofs + i;
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/* A bit is present in every odd frame TS0 */
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if (frame_nr & 1) {
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uint8_t ts0 = *e1_data_ptr(0, ofs + i, 0);
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rai_possible = true;
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if (ts0 & 0x20) {
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rai_received = true;
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break;
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}
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}
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}
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/* Wait for DMA completion */
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while (dma_poll());
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}
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if (rai_possible) {
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if (rai_received) {
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e1->errors.flags |= E1_ERR_F_RAI;
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e1_platform_led_set(port, E1P_LED_YELLOW, E1P_LED_ST_ON);
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} else {
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e1->errors.flags &= ~E1_ERR_F_RAI;
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e1_platform_led_set(port, E1P_LED_YELLOW, E1P_LED_ST_OFF);
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}
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}
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return tot_frames;
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}
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unsigned int
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e1_tx_feed_data(int port, unsigned int usb_addr, unsigned int frames)
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{
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struct e1_state *e1 = _get_state(port);
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unsigned int ofs;
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int n_frames;
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while (frames) {
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/* Get some space in FIFO */
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n_frames = e1f_frame_write(&e1->tx.fifo, &ofs, frames);
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if (!n_frames) {
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printf("[!] TX FIFO Overflow (port=%d, req=%d, done=%d)\n", port, frames, n_frames);
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e1f_debug(&e1->tx.fifo, "TX");
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break;
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}
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/* Copy from USB to FIFO */
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dma_exec(e1f_ofs_to_dma(ofs), usb_addr, n_frames * (32 / 4), true, NULL, NULL);
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/* Prepare next */
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usb_addr += n_frames * (32 / 4);
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frames -= n_frames;
|
|
|
|
/* Wait for DMA completion */
|
|
while (dma_poll());
|
|
}
|
|
|
|
return frames;
|
|
}
|
|
|
|
unsigned int
|
|
e1_rx_level(int port)
|
|
{
|
|
struct e1_state *e1 = _get_state(port);
|
|
return e1f_valid_frames(&e1->rx.fifo);
|
|
}
|
|
|
|
unsigned int
|
|
e1_tx_level(int port)
|
|
{
|
|
struct e1_state *e1 = _get_state(port);
|
|
return e1f_valid_frames(&e1->tx.fifo);
|
|
}
|
|
|
|
const struct e1_error_count *
|
|
e1_get_error_count(int port)
|
|
{
|
|
struct e1_state *e1 = _get_state(port);
|
|
return &e1->errors;
|
|
}
|
|
|
|
void
|
|
e1_poll(int port)
|
|
{
|
|
volatile struct e1_core *e1_regs = _get_regs(port);
|
|
struct e1_state *e1 = _get_state(port);
|
|
uint32_t bd;
|
|
unsigned int ofs;
|
|
|
|
/* HACK: LED link status */
|
|
if (e1_regs->rx.csr & E1_RX_SR_ALIGNED) {
|
|
e1_platform_led_set(port, E1P_LED_GREEN, E1P_LED_ST_ON);
|
|
led_color(0, 48, 0);
|
|
e1->errors.flags &= ~(E1_ERR_F_LOS|E1_ERR_F_ALIGN_ERR);
|
|
} else {
|
|
e1_platform_led_set(port, E1P_LED_GREEN, E1P_LED_ST_BLINK);
|
|
e1_platform_led_set(port, E1P_LED_YELLOW, E1P_LED_ST_OFF);
|
|
led_color(48, 0, 0);
|
|
e1->errors.flags |= E1_ERR_F_ALIGN_ERR;
|
|
/* TODO: completely off if rx tick counter not incrementing */
|
|
}
|
|
|
|
/* Active ? */
|
|
if ((e1->rx.state == IDLE) && (e1->tx.state == IDLE))
|
|
return;
|
|
|
|
/* Recover any done TX BD */
|
|
while ( (bd = e1_regs->tx.bd) & E1_BD_VALID ) {
|
|
e1f_multiframe_read_discard(&e1->tx.fifo);
|
|
e1->tx.in_flight--;
|
|
}
|
|
|
|
/* Recover any done RX BD */
|
|
while ( (bd = e1_regs->rx.bd) & E1_BD_VALID ) {
|
|
/* FIXME: CRC status ? */
|
|
e1f_multiframe_write_commit(&e1->rx.fifo);
|
|
if ((bd & (E1_BD_CRC0 | E1_BD_CRC1)) != (E1_BD_CRC0 | E1_BD_CRC1)) {
|
|
printf("[!] E1 crc err (port=%d, bd=%03x)\n", port, bd);
|
|
e1->errors.crc++;
|
|
}
|
|
e1->rx.in_flight--;
|
|
}
|
|
|
|
/* Boot procedure */
|
|
if (e1->tx.state == STARTING) {
|
|
if (e1f_unseen_frames(&e1->tx.fifo) < (16 * 5))
|
|
return;
|
|
/* HACK: LED flow status */
|
|
led_blink(true, 200, 1000);
|
|
led_breathe(true, 100, 200);
|
|
}
|
|
|
|
/* Handle RX */
|
|
/* Bypass if OFF */
|
|
if (e1->rx.state == IDLE)
|
|
goto done_rx;
|
|
|
|
/* Shutdown */
|
|
if (e1->rx.state == SHUTDOWN) {
|
|
if (e1->rx.in_flight == 0) {
|
|
e1->rx.state = IDLE;
|
|
_e1_update_cr_val(port);
|
|
e1_regs->rx.csr = e1->rx.cr.val;
|
|
}
|
|
goto done_rx;
|
|
}
|
|
|
|
/* Misalign ? */
|
|
if (e1->rx.state == RUN) {
|
|
if (!(e1_regs->rx.csr & E1_RX_SR_ALIGNED)) {
|
|
printf("[!] E1 rx misalign (port=%d)\n", port);
|
|
e1->rx.state = RECOVER;
|
|
e1->errors.align++;
|
|
}
|
|
}
|
|
|
|
/* Overflow ? */
|
|
if (e1->rx.state == RUN) {
|
|
if (e1_regs->rx.csr & E1_RX_SR_OVFL) {
|
|
printf("[!] E1 overflow (port=%d, inf=%d)\n", port, e1->rx.in_flight);
|
|
e1->rx.state = RECOVER;
|
|
e1->errors.ovfl++;
|
|
}
|
|
}
|
|
|
|
/* Recover ready ? */
|
|
if (e1->rx.state == RECOVER) {
|
|
if (e1->rx.in_flight != 0)
|
|
goto done_rx;
|
|
e1f_multiframe_empty_tail(&e1->rx.fifo);
|
|
}
|
|
|
|
/* Fill new RX BD */
|
|
while (e1->rx.in_flight < 4) {
|
|
if (!e1f_multiframe_write_prepare(&e1->rx.fifo, &ofs))
|
|
break;
|
|
e1_regs->rx.bd = e1f_ofs_to_mf(ofs);
|
|
e1->rx.in_flight++;
|
|
}
|
|
|
|
/* Clear overflow if needed */
|
|
if (e1->rx.state != RUN) {
|
|
e1_regs->rx.csr = e1->rx.cr.val | E1_RX_CR_OVFL_CLR;
|
|
e1->rx.state = RUN;
|
|
}
|
|
done_rx:
|
|
|
|
/* Handle TX */
|
|
/* Bypass if OFF */
|
|
if (e1->tx.state == IDLE)
|
|
return;
|
|
|
|
/* Shutdown */
|
|
if (e1->tx.state == SHUTDOWN) {
|
|
if (e1->tx.in_flight == 0) {
|
|
e1->tx.state = IDLE;
|
|
_e1_update_cr_val(port);
|
|
e1_regs->tx.csr = e1->tx.cr.val;
|
|
}
|
|
return;
|
|
}
|
|
|
|
/* Underflow ? */
|
|
if (e1->tx.state == RUN) {
|
|
if (e1_regs->tx.csr & E1_TX_SR_UNFL) {
|
|
printf("[!] E1 underflow (port=%d, inf=%d)\n", port, e1->tx.in_flight);
|
|
e1->tx.state = RECOVER;
|
|
e1->errors.unfl++;
|
|
}
|
|
}
|
|
|
|
/* Recover ready ? */
|
|
if (e1->tx.state == RECOVER) {
|
|
if (e1f_unseen_frames(&e1->tx.fifo) < (16 * 5))
|
|
return;
|
|
}
|
|
|
|
/* Fill new TX BD */
|
|
while (e1->tx.in_flight < 4) {
|
|
if (!e1f_multiframe_read_peek(&e1->tx.fifo, &ofs))
|
|
break;
|
|
e1_regs->tx.bd = e1f_ofs_to_mf(ofs);
|
|
e1->tx.in_flight++;
|
|
}
|
|
|
|
/* Clear underflow if needed */
|
|
if (e1->tx.state != RUN) {
|
|
e1_regs->tx.csr = e1->tx.cr.val | E1_TX_CR_UNFL_CLR;
|
|
e1->tx.state = RUN;
|
|
}
|
|
}
|
|
|
|
void
|
|
e1_linemon_update(void)
|
|
{
|
|
static int cycle = -1;
|
|
|
|
/* Initial boot */
|
|
if (cycle == -1) {
|
|
e1_tick_sel(TICK_RX_PULSE);
|
|
cycle = 0;
|
|
return;
|
|
}
|
|
|
|
/* Current cycle ? */
|
|
switch (cycle) {
|
|
/* Read initial values */
|
|
case 0:
|
|
case 2:
|
|
case 4:
|
|
for (int port=0; port<NUM_E1_PORTS; port++)
|
|
g_e1[port].linemon._val = e1_tick_read(port);
|
|
break;
|
|
|
|
/* Actual reading */
|
|
case 1:
|
|
for (int port=0; port<NUM_E1_PORTS; port++)
|
|
g_e1[port].linemon.rx_pulse = e1_tick_read(port) - g_e1[port].linemon._val;
|
|
e1_tick_sel(TICK_RX_SAMPLE);
|
|
break;
|
|
|
|
case 3:
|
|
for (int port=0; port<NUM_E1_PORTS; port++)
|
|
g_e1[port].linemon.rx_sample = e1_tick_read(port) - g_e1[port].linemon._val;
|
|
e1_tick_sel(TICK_RX_ONE);
|
|
break;
|
|
|
|
case 5:
|
|
for (int port=0; port<NUM_E1_PORTS; port++)
|
|
g_e1[port].linemon.rx_one = e1_tick_read(port) - g_e1[port].linemon._val;
|
|
e1_tick_sel(TICK_RX_PULSE);
|
|
break;
|
|
}
|
|
|
|
/* Next cycle */
|
|
if (++cycle == 6)
|
|
cycle = 0;
|
|
}
|
|
|
|
void
|
|
e1_debug_print(int port, bool data)
|
|
{
|
|
volatile struct e1_core *e1_regs = _get_regs(port);
|
|
struct e1_state *e1 = _get_state(port);
|
|
volatile uint8_t *p;
|
|
|
|
printf("E1 port %d\n", port);
|
|
printf("CSR: Rx %04x / Tx %04x\n", e1_regs->rx.csr, e1_regs->tx.csr);
|
|
printf("InF: Rx %d / Tx %d\n", e1->rx.in_flight, e1->tx.in_flight);
|
|
printf("Sta: Rx %d / Tx %d\n", e1->rx.state, e1->tx.state);
|
|
printf("Tck: P %d / S %d / O %d\n",
|
|
e1->linemon.rx_pulse, e1->linemon.rx_sample, e1->linemon.rx_one);
|
|
|
|
e1f_debug(&e1->rx.fifo, "Rx FIFO");
|
|
e1f_debug(&e1->tx.fifo, "Tx FIFO");
|
|
|
|
if (data) {
|
|
puts("\nE1 Data\n");
|
|
for (int f=0; f<16; f++) {
|
|
p = e1_data_ptr(0, f, 0);
|
|
for (int ts=0; ts<32; ts++)
|
|
printf(" %02x", p[ts]);
|
|
printf("\n");
|
|
}
|
|
}
|
|
}
|