58 lines
1.1 KiB
Verilog
58 lines
1.1 KiB
Verilog
/*
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* wb_epbuf.v
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*
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* vim: ts=4 sw=4
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*
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* Copyright (C) 2020 Sylvain Munaut <tnt@246tNt.com>
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* SPDX-License-Identifier: CERN-OHL-P-2.0
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*/
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`default_nettype none
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module wb_epbuf #(
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parameter integer AW = 9,
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parameter integer DW = 32
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)(
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// Wishbone slave
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input wire [AW-1:0] wb_addr,
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output wire [DW-1:0] wb_rdata,
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input wire [DW-1:0] wb_wdata,
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input wire wb_we,
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input wire wb_cyc,
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output wire wb_ack,
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// USB EP-Buf master
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output wire [AW-1:0] ep_tx_addr_0,
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output wire [DW-1:0] ep_tx_data_0,
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output wire ep_tx_we_0,
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output wire [AW-1:0] ep_rx_addr_0,
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input wire [DW-1:0] ep_rx_data_1,
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output wire ep_rx_re_0,
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// Clock / Reset
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input wire clk,
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input wire rst
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);
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reg ack_i;
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assign ep_tx_addr_0 = wb_addr;
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assign ep_rx_addr_0 = wb_addr;
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assign ep_tx_data_0 = wb_wdata;
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assign wb_rdata = ep_rx_data_1;
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assign ep_tx_we_0 = wb_cyc & wb_we & ~ack_i;
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assign ep_rx_re_0 = 1'b1;
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assign wb_ack = ack_i;
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always @(posedge clk or posedge rst)
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if (rst)
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ack_i <= 1'b0;
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else
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ack_i <= wb_cyc & ~ack_i;
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endmodule // wb_epbuf
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