Harald Welte
cdbcff9b18
CRC4: use proper CRC4 table to avoid bit-reversal of each byte
...
In commit 9bd2c9ffe7
we fixed the CRC4
computation by bit-reversing every byte before using it in the CRC
table. This is of course a waste of CPU cycles. Let's just compute
the CRC4 table slightly different (thanks to Dietter):
The following commands using pycrc from pycrc.org were used:
./pycrc.py --width=4 --poly=0x3 --reflect-in=false --reflect-out=false --xor-out=0 --xor-in=0 --algorithm table-driven --generate c -o crc4itu.c
./pycrc.py --width=4 --poly=0x3 --reflect-in=false --reflect-out=false --xor-out=0 --xor-in=0 --algorithm table-driven --generate h -o crc4itu.h
2018-05-12 09:44:03 +02:00
Harald Welte
ce18a04b27
add e1_test_dieter to deframe/decode dieters capture
2018-05-11 22:00:46 +02:00
Harald Welte
8a95fd5481
osmo_e1: Add HDLC framing/deframing
2018-05-11 22:00:18 +02:00
Harald Welte
37e2374545
osmo_e1: Silence the FSM logging
2018-05-11 21:21:01 +02:00
Harald Welte
9bd2c9ffe7
HACK to make CRC4 computation work
...
* reverse bit-order of every input byte when computing CRC4
* reverse bit-order of CRC4 value we receive in TS0 bits
I don't really understand why, but this makes the CRC check pass.
We probably need another table if we want to avoid this.
2018-05-11 20:48:31 +02:00
Harald Welte
d3941c6a98
osmo_e1.c: Fix handling of TS2..31 (use 'i', not '1')
2018-05-11 16:47:59 +02:00
Harald Welte
f01471d212
add some information related a SAM4S based USB-to-LIU adapter board idea
2018-05-07 15:37:26 +02:00
Harald Welte
0c756eb5ec
WIP: Software for E1 mux/demux
2018-05-07 15:37:26 +02:00
Harald Welte
5b15f681e5
add E1 tap hardware design
2012-07-21 20:22:23 +02:00
Harald Welte
ceb6ef1d21
laforge.lbr: fix amphenol sim reader footprint
2012-07-01 11:21:26 +02:00
Harald Welte
b59bfbc3cc
major update of laforge.lbr with lots of new components
2012-07-01 10:45:55 +02:00
Harald Welte
605e3e459f
add some glue code between the idt82 driver and at91lib SPI
2012-03-06 23:15:42 +01:00
Harald Welte
638afbb89b
'new' PCB routing by Christian Vogel
2012-03-06 21:53:51 +01:00
Harald Welte
28460ee9e5
major update of laforge.lbr with lots of new components
2012-02-20 23:42:18 +01:00
Harald Welte
da02f556e0
add initial driver skeleton for idt82v2081 chip
2012-01-14 18:18:31 +01:00
Harald Welte
ceb70a8260
give parts names without "$", use 47nH as L1 (1206)
2012-01-14 12:44:58 +01:00
Harald Welte
b8dfc48a37
approve lots of warnings about thinner wires
...
Christan has routed lots of wires thinner than what the network specific
rules state. We approve all of them as we don't care about thinner
wires.
2011-12-26 12:59:33 +01:00
Harald Welte
71ba939922
remove stray GNDIO wire, add junction, approve some warnings
2011-12-26 12:59:02 +01:00
Christian Vogel
5becd7e2fa
re-route complete board, add PWR jumper, LED series resistor
2011-12-26 12:57:31 +01:00
Harald Welte
a40a482b3d
add partlist/bom
2011-12-24 17:02:02 +01:00
Harald Welte
372a183036
update schematics and PCB layout
2011-12-24 17:01:54 +01:00
Harald Welte
07c856afa0
re-route pcb with LEDs
2011-12-24 17:00:12 +01:00
Harald Welte
f687f38c58
add two LEDs (power and LOS) plus required transistor
2011-12-24 16:51:35 +01:00
Harald Welte
a2c23eb8b1
re-route the entire board to add test pads and additional components
2011-12-24 16:23:08 +01:00
Harald Welte
8b0e886f73
just name some signals/networks
2011-12-24 16:22:54 +01:00
Harald Welte
311b277cf4
add solder jumper to bypass TPS736XX (if it is not populated)
2011-12-24 15:58:41 +01:00
Harald Welte
df93fb19f6
add 4 test pads for RTIP/RRING/TTIP/TRING
2011-12-24 15:56:40 +01:00
Harald Welte
e5fd58a292
re-wire SPI connector to reflect pin-out of Olimex devel board UEXT
2011-12-24 15:54:22 +01:00
Harald Welte
f4a1d02c6a
Add LDO, remove jumpers, 3nd RJ45, ...
2011-12-24 02:41:25 +01:00
Harald Welte
2f4c472899
add README file
2011-12-24 00:36:06 +01:00
Harald Welte
547bc5cdec
initial checkin
2011-12-23 20:57:21 +01:00