2020-09-14 08:19:49 +00:00
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/*
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* spi.c
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*
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* Copyright (C) 2019-2020 Sylvain Munaut <tnt@246tNt.com>
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* SPDX-License-Identifier: LGPL-3.0-or-later
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*/
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#include <stdbool.h>
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#include <stdint.h>
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#include "config.h"
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#include "spi.h"
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struct spi {
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uint32_t _rsvd0[6];
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uint32_t irq; /* 0110 - SPIIRQ - Interrupt Status Register */
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uint32_t irqen; /* 0111 - SPIIRQEN - Interrupt Control Register */
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uint32_t cr0; /* 1000 - CR0 - Control Register 0 */
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uint32_t cr1; /* 1001 - CR1 - Control Register 1 */
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uint32_t cr2; /* 1010 - CR2 - Control Register 2 */
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uint32_t br; /* 1011 - BR - Baud Rate Register */
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uint32_t sr; /* 1100 - SR - Status Register */
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uint32_t txdr; /* 1101 - TXDR - Transmit Data Register */
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uint32_t rxdr; /* 1110 - RXDR - Receive Data Register */
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uint32_t csr; /* 1111 - CSR - Chip Select Register */
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} __attribute__((packed,aligned(4)));
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#define SPI_CR0_TIDLE(xcnt) (((xcnt) & 3) << 6)
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#define SPI_CR0_TTRAIL(xcnt) (((xcnt) & 7) << 3)
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#define SPI_CR0_TLEAD(xcnt) (((xcnt) & 7) << 0)
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#define SPI_CR1_ENABLE (1 << 7)
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#define SPI_CR1_WKUPEN_USER (1 << 6)
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#define SPI_CR1_TXEDGE (1 << 4)
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#define SPI_CR2_MASTER (1 << 7)
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#define SPI_CR2_MCSH (1 << 6)
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#define SPI_CR2_SDBRE (1 << 5)
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#define SPI_CR2_CPOL (1 << 2)
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#define SPI_CR2_CPHA (1 << 1)
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#define SPI_CR2_LSBF (1 << 0)
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#define SPI_SR_TIP (1 << 7)
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#define SPI_SR_BUSY (1 << 6)
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#define SPI_SR_TRDY (1 << 4)
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#define SPI_SR_RRDY (1 << 3)
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#define SPI_SR_TOE (1 << 2)
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#define SPI_SR_ROE (1 << 1)
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#define SPI_SR_MDF (1 << 0)
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static volatile struct spi * const spi_regs[] = {
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(void*)(SPI_FLASH_BASE),
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#ifdef BOARD_E1_TRACER
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(void*)(SPI_LIU_BASE),
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#endif
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};
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void
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spi_init(void)
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{
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/* Channel 0: Flash */
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spi_regs[0]->cr0 = SPI_CR0_TIDLE(3) |
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SPI_CR0_TTRAIL(7) |
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SPI_CR0_TLEAD(7);
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spi_regs[0]->cr1 = SPI_CR1_ENABLE;
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spi_regs[0]->cr2 = SPI_CR2_MASTER | SPI_CR2_MCSH;
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spi_regs[0]->br = 3;
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spi_regs[0]->csr = 0xf;
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#ifdef BOARD_E1_TRACER
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/* Channel 1: LIU */
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spi_regs[1]->cr0 = SPI_CR0_TIDLE(3) |
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SPI_CR0_TTRAIL(7) |
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SPI_CR0_TLEAD(7);
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spi_regs[1]->cr1 = SPI_CR1_ENABLE | SPI_CR1_TXEDGE;
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spi_regs[1]->cr2 = SPI_CR2_MASTER | SPI_CR2_LSBF | SPI_CR2_MCSH | SPI_CR2_CPHA;
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spi_regs[1]->br = 3;
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spi_regs[1]->csr = 0xf;
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#endif
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}
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void
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spi_xfer(unsigned cs, const struct spi_xfer_chunk *xfer, unsigned n)
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{
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2020-10-28 20:59:29 +00:00
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uint8_t rxd;
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2020-09-14 08:19:49 +00:00
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unsigned chan = (cs >> 2);
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cs &= 3;
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/* Setup CS */
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spi_regs[chan]->csr = 0xf ^ (1 << cs);
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/* Run the chunks */
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while (n--) {
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2020-10-29 12:24:50 +00:00
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for (unsigned int i=0; i<xfer->len; i++)
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2020-09-14 08:19:49 +00:00
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{
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spi_regs[chan]->txdr = xfer->write ? xfer->data[i] : 0x00;
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while (!(spi_regs[chan]->sr & SPI_SR_RRDY));
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2020-10-28 20:59:29 +00:00
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rxd = spi_regs[chan]->rxdr;
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2020-09-14 08:19:49 +00:00
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if (xfer->read)
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2020-10-28 20:59:29 +00:00
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xfer->data[i] = rxd;
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2020-09-14 08:19:49 +00:00
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}
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xfer++;
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}
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/* Clear CS */
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spi_regs[chan]->csr = 0xf;
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}
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#define FLASH_CMD_DEEP_POWER_DOWN 0xb9
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#define FLASH_CMD_WAKE_UP 0xab
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#define FLASH_CMD_WRITE_ENABLE 0x06
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#define FLASH_CMD_WRITE_ENABLE_VOLATILE 0x50
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#define FLASH_CMD_WRITE_DISABLE 0x04
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#define FLASH_CMD_READ_MANUF_ID 0x9f
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#define FLASH_CMD_READ_UNIQUE_ID 0x4b
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#define FLASH_CMD_READ_SR1 0x05
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#define FLASH_CMD_WRITE_SR1 0x01
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#define FLASH_CMD_READ_DATA 0x03
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#define FLASH_CMD_PAGE_PROGRAM 0x02
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#define FLASH_CMD_CHIP_ERASE 0x60
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#define FLASH_CMD_SECTOR_ERASE 0x20
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void
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flash_cmd(uint8_t cmd)
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{
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struct spi_xfer_chunk xfer[1] = {
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{ .data = (void*)&cmd, .len = 1, .read = false, .write = true, },
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};
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spi_xfer(SPI_CS_FLASH, xfer, 1);
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}
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void
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flash_deep_power_down(void)
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{
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flash_cmd(FLASH_CMD_DEEP_POWER_DOWN);
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}
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void
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flash_wake_up(void)
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{
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flash_cmd(FLASH_CMD_WAKE_UP);
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}
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void
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flash_write_enable(void)
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{
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flash_cmd(FLASH_CMD_WRITE_ENABLE);
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}
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void
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flash_write_enable_volatile(void)
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{
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flash_cmd(FLASH_CMD_WRITE_ENABLE_VOLATILE);
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}
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void
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flash_write_disable(void)
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{
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flash_cmd(FLASH_CMD_WRITE_DISABLE);
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}
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void
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flash_manuf_id(void *manuf)
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{
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uint8_t cmd = FLASH_CMD_READ_MANUF_ID;
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struct spi_xfer_chunk xfer[2] = {
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{ .data = (void*)&cmd, .len = 1, .read = false, .write = true, },
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{ .data = (void*)manuf, .len = 3, .read = true, .write = false, },
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};
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spi_xfer(SPI_CS_FLASH, xfer, 2);
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}
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void
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flash_unique_id(void *id)
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{
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uint8_t cmd = FLASH_CMD_READ_UNIQUE_ID;
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struct spi_xfer_chunk xfer[3] = {
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{ .data = (void*)&cmd, .len = 1, .read = false, .write = true, },
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{ .data = (void*)0, .len = 4, .read = false, .write = false, },
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{ .data = (void*)id, .len = 8, .read = true, .write = false, },
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};
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spi_xfer(SPI_CS_FLASH, xfer, 3);
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}
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uint8_t
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flash_read_sr(void)
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{
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uint8_t cmd = FLASH_CMD_READ_SR1;
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uint8_t rv;
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struct spi_xfer_chunk xfer[2] = {
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{ .data = (void*)&cmd, .len = 1, .read = false, .write = true, },
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{ .data = (void*)&rv, .len = 1, .read = true, .write = false, },
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};
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spi_xfer(SPI_CS_FLASH, xfer, 2);
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return rv;
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}
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void
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flash_write_sr(uint8_t sr)
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{
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uint8_t cmd[2] = { FLASH_CMD_WRITE_SR1, sr };
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struct spi_xfer_chunk xfer[1] = {
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{ .data = (void*)cmd, .len = 2, .read = false, .write = true, },
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};
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spi_xfer(SPI_CS_FLASH, xfer, 1);
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}
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void
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flash_read(void *dst, uint32_t addr, unsigned len)
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{
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uint8_t cmd[4] = { FLASH_CMD_READ_DATA, ((addr >> 16) & 0xff), ((addr >> 8) & 0xff), (addr & 0xff) };
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struct spi_xfer_chunk xfer[2] = {
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{ .data = (void*)cmd, .len = 4, .read = false, .write = true, },
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{ .data = (void*)dst, .len = len, .read = true, .write = false, },
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};
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spi_xfer(SPI_CS_FLASH, xfer, 2);
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}
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void
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2020-10-28 20:58:57 +00:00
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flash_page_program(const void *src, uint32_t addr, unsigned len)
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2020-09-14 08:19:49 +00:00
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{
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uint8_t cmd[4] = { FLASH_CMD_PAGE_PROGRAM, ((addr >> 16) & 0xff), ((addr >> 8) & 0xff), (addr & 0xff) };
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struct spi_xfer_chunk xfer[2] = {
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{ .data = (void*)cmd, .len = 4, .read = false, .write = true, },
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{ .data = (void*)src, .len = len, .read = false, .write = true, },
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};
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spi_xfer(SPI_CS_FLASH, xfer, 2);
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}
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void
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flash_sector_erase(uint32_t addr)
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{
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uint8_t cmd[4] = { FLASH_CMD_SECTOR_ERASE, ((addr >> 16) & 0xff), ((addr >> 8) & 0xff), (addr & 0xff) };
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struct spi_xfer_chunk xfer[1] = {
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{ .data = (void*)cmd, .len = 4, .read = false, .write = true, },
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};
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spi_xfer(SPI_CS_FLASH, xfer, 1);
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}
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