82 lines
2.3 KiB
C
82 lines
2.3 KiB
C
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#ifndef _IDT82_REGS_H
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#define _IDT82_REGS_H
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/* Section 4.1 of Data Sheet */
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enum idt82v2081_reg {
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IDT_REG_ID, /* control */
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IDT_REG_RST,
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IDT_REG_GCF,
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IDT_REG_TERM,
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IDT_REG_JACF,
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IDT_REG_TCF0, /* Tx path control */
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IDT_REG_TCF1,
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IDT_REG_TCF2,
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IDT_REG_TCF3,
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IDT_REG_TCF4,
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IDT_REG_RCF0, /* Rx path control */
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IDT_REG_RCF1,
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IDT_REG_RCF2,
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IDT_REG_MAINT0, /* Net Diag Ctrl */
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IDT_REG_MAINT1,
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IDT_REG_MAINT2,
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IDT_REG_MAINT3,
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IDT_REG_MAINT4,
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IDT_REG_MAINT5,
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IDT_REG_MAINT6,
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IDT_REG_INTM0, /* Interrupt Control */
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IDT_REG_INTM1,
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IDT_REG_INTES,
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IDT_REG_STAT0, /* Line Status */
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IDT_REG_STAT1,
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IDT_REG_INTS0, /* Interrupt Status */
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IDT_REG_INTS1,
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IDT_REG_CNT0, /* Counter */
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IDT_REG_CNT1,
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};
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#define IDT_GCF_T1E1_E1 (0 << 2)
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#define IDT_GCF_T1E1_T1 (1 << 2)
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#define IDT_GCF_T1E1_MASK (1 << 2)
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#define IDT_TERM_T_SHIFT 3
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#define IDT_TERM_T_MASK (7 << IDT_TERM_T_SHIFT)
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#define IDT_TERM_R_SHIFT 0
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#define IDT_TERM_R_MASK (7 << IDT_TERM_R_SHIFT)
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#define IDT_TCF1_PULS_MASK 0xF
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#define IDT_TCF2_SCAL_MASK 0x3F
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#define IDT_RCF2_MG_MASK 3
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#define IDT_RCF2_UPDW_SHIFT 2
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#define IDT_RCF2_UPDW_MASK (3 << IDT_TERM_INT_75)
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#define IDT_RCF2_SLICE_SHIFT 4
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#define IDT_RCF2_SLICE_MASK (3 << IDT_RCF2_SLICE_SHIFT)
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#define IDT_INTM0_EQ (1 << 7) /* equalizer out of range */
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#define IDT_INTM0_IBLBA (1 << 6) /* in-band LB act detect */
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#define IDT_INTM0_IBLBD (1 << 5) /* in-band LB deact detect */
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#define IDT_INTM0_PRBS (1 << 4) /* prbs sync signal detect */
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#define IDT_INTM0_TCLK (1 << 3) /* tclk loss */
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#define IDT_INTM0_DF (1 << 2) /* driver failure */
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#define IDT_INTM0_AIS (1 << 1) /* Alarm Indication Signal */
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#define IDT_INTM0_LOS (1 << 0) /* Loss Of Signal */
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#define IDT_INTM1_DAC_OV (1 << 7) /* DAC arithmetic overflow */
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#define IDT_INTM1_JA_OV (1 << 6) /* JA overflow */
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#define IDT_INTM1_JA_UD (1 << 5) /* JA underflow */
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#define IDT_INTM1_ERR (1 << 4) /* PRBS/QRBS logic error detect */
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#define IDT_INTM1_EXZ (1 << 3) /* Receive excess zeros */
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#define IDT_INTM1_CV (1 << 2) /* Receive error */
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#define IDT_INTM1_TIMER (1 << 1) /* One second timer expiration */
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#define IDT_INTM1_CNT (1 << 0) /* Counter overflow */
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/* STAT0 == INTES == INTS0 == INTM0 */
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/* INTS1 == INTM1 */
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#define IDT_STAT1_RLP (1 << 5)
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#define IDT_STAT1_ATT_MASK 0x1F
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#endif /* _IDT82_REGS_H */
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