Martin Bachem
|
6541634bdf
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- using fifo wrirte/read 32 bit access
- optimized forced TE deactivation
|
2006-02-22 12:26:14 +00:00 |
|
Martin Bachem
|
44fc461e01
|
- new register header file
- correct chip ID's
|
2006-01-10 16:39:24 +00:00 |
|
Martin Bachem
|
ae2adf6c7f
|
slightly modified debug output, slightly code beautifications
|
2005-12-21 08:50:54 +00:00 |
|
Martin Bachem
|
2e887b0c04
|
improved layer1 state handling
|
2005-12-20 15:26:52 +00:00 |
|
Martin Bachem
|
9d40b9fb64
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- improved activation/deactivation timers (t3/t4)
|
2005-12-19 16:38:27 +00:00 |
|
Martin Bachem
|
5ccc714c19
|
- common HW layer channel model for B and D channel
|
2005-12-09 16:20:38 +00:00 |
|
Karsten Keil
|
0913082112
|
- common HW layer channel model for B and D channel
* reduce duplicated code
* not finished and tested for all drivers
|
2005-12-08 18:32:53 +00:00 |
|
Martin Bachem
|
e1b97ac317
|
- send transparent audio data asap to upper layer to reduce latency
|
2005-12-08 16:36:37 +00:00 |
|
Martin Bachem
|
e4442d1014
|
- directly linked to layer2 (omitting layer1.c)
- implement MGR_SHORTSTATUS messages
|
2005-12-08 15:54:18 +00:00 |
|
Karsten Keil
|
526c241c06
|
remove unused bch->st
|
2005-11-25 13:32:27 +00:00 |
|
Martin Bachem
|
c4a730317a
|
added support for Cologne Chip AG's XHFC Evaluation card
|
2005-11-09 18:09:38 +00:00 |