8a490422be
MPC5121 rev 2 silicon has a new register for controlling how long CS is asserted after deassertion of ALE in multiplexed mode. The default is to assert CS together with ALE. The alternative is to assert CS (ALEN+1)*LPC_CLK clocks after deassertion of ALE. The default is wrong for the NOR flash and CPLD on the ADS5121. This patch turns on the alternative for CS0 (NOR) and CS2 (CPLD) it does so conditionally based on silicon rev 2.0 or greater. Signed-off-by: Martha J Marx <mmarx@silicontkx.com> Signed-off-by: John Rigby <jrigby@freescale.com> |
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| .. | ||
| Makefile | ||
| README | ||
| ads5121.c | ||
| ads5121_diu.c | ||
| config.mk | ||
| pci.c | ||
| u-boot.lds | ||
README
To configure for the current (Rev 3.x) ADS5121 make ads5121_config This will automatically include PCI, the Real Time CLock, add backup flash ability and set the correct frequency and memory configuration. To configure for the older Rev 2 ADS5121 type (this will not have PCI) make ads5121_rev2_config