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Big white-space cleanup. 

This commit gets rid of a huge amount of silly white-space issues.
Especially, all sequences of SPACEs followed by TAB characters get
removed (unless they appear in print statements).

Also remove all embedded "vim:" and "vi:" statements which hide
indentation problems.

Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Wolfgang Denk 2008-05-20 16:00:29 +02:00
parent 727f633346
commit 53677ef18e
1010 changed files with 13324 additions and 13313 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

76
board/MAI/AmigaOneG3SE/AmigaOneG3SE.c
View File

@ -14,7 +14,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@ -30,48 +30,48 @@
#include "memio.h"
#include "via686.h"
__asm__(" .globl send_kb \n "
"send_kb: \n "
" lis r9, 0xfe00 \n "
" \n "
" li r4, 0x10 # retries \n "
" mtctr r4 \n "
" \n "
"idle: \n "
" lbz r4, 0x64(r9) \n "
" andi. r4, r4, 0x02 \n "
" bne idle \n "
__asm__(" .globl send_kb \n "
"send_kb: \n "
" lis r9, 0xfe00 \n "
" \n "
" li r4, 0x10 # retries \n "
" mtctr r4 \n "
" \n "
"idle: \n "
" lbz r4, 0x64(r9) \n "
" andi. r4, r4, 0x02 \n "
" bne idle \n "
"ready: \n "
" stb r3, 0x60(r9) \n "
" \n "
"check: \n "
" lbz r4, 0x64(r9) \n "
" andi. r4, r4, 0x01 \n "
" beq check \n "
" \n "
" lbz r4, 0x60(r9) \n "
" cmpwi r4, 0xfa \n "
" beq done \n "
"ready: \n "
" stb r3, 0x60(r9) \n "
" \n "
"check: \n "
" lbz r4, 0x64(r9) \n "
" andi. r4, r4, 0x01 \n "
" beq check \n "
" \n "
" lbz r4, 0x60(r9) \n "
" cmpwi r4, 0xfa \n "
" beq done \n "
" bdnz idle \n "
" bdnz idle \n "
" li r3, 0 \n "
" blr \n "
" li r3, 0 \n "
" blr \n "
"done: \n "
" li r3, 1 \n "
" blr \n "
"done: \n "
" li r3, 1 \n "
" blr \n "
".globl test_kb \n "
"test_kb: \n "
" mflr r10 \n "
" li r3, 0xed \n "
" bl send_kb \n "
" li r3, 0x01 \n "
" bl send_kb \n "
" mtlr r10 \n "
" blr "
".globl test_kb \n "
"test_kb: \n "
" mflr r10 \n "
" li r3, 0xed \n "
" bl send_kb \n "
" li r3, 0x01 \n "
" bl send_kb \n "
" mtlr r10 \n "
" blr \n "
);

593
board/MAI/AmigaOneG3SE/enet.c
View File

@ -90,8 +90,8 @@
#define DMADone (1<<8)
#define DownComplete (1<<9)
#define UpComplete (1<<10)
#define DMAInProgress (1<<11) /* DMA controller is still busy.*/
#define CmdInProgress (1<<12) /* EL3_CMD is still busy.*/
#define DMAInProgress (1<<11) /* DMA controller is still busy.*/
#define CmdInProgress (1<<12) /* EL3_CMD is still busy.*/
/* Polling Registers */
@ -100,17 +100,17 @@
/* Register window 0 offets */
#define Wn0EepromCmd 10 /* Window 0: EEPROM command register. */
#define Wn0EepromData 12 /* Window 0: EEPROM results register. */
#define IntrStatus 0x0E /* Valid in all windows. */
#define Wn0EepromCmd 10 /* Window 0: EEPROM command register. */
#define Wn0EepromData 12 /* Window 0: EEPROM results register. */
#define IntrStatus 0x0E /* Valid in all windows. */
/* Register window 0 EEPROM bits */
#define EEPROM_Read 0x80
#define EEPROM_WRITE 0x40
#define EEPROM_ERASE 0xC0
#define EEPROM_EWENB 0x30 /* Enable erasing/writing for 10 msec. */
#define EEPROM_EWDIS 0x00 /* Disable EWENB before 10 msec timeout. */
#define EEPROM_EWENB 0x30 /* Enable erasing/writing for 10 msec. */
#define EEPROM_EWDIS 0x00 /* Disable EWENB before 10 msec timeout. */
/* EEPROM locations. */
@ -135,7 +135,7 @@
#define RxStatus 0x18
#define Timer 0x1A
#define TxStatus 0x1B
#define TxFree 0x1C /* Remaining free bytes in Tx buffer. */
#define TxFree 0x1C /* Remaining free bytes in Tx buffer. */
/* Register Window 2 */
@ -143,23 +143,23 @@
/* Register Window 3: MAC/config bits */
#define Wn3_Config 0 /* Internal Configuration */
#define Wn3_Config 0 /* Internal Configuration */
#define Wn3_MAC_Ctrl 6
#define Wn3_Options 8
#define BFEXT(value, offset, bitcount) \
((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
#define BFINS(lhs, rhs, offset, bitcount) \
#define BFINS(lhs, rhs, offset, bitcount) \
(((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
(((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
#define RAM_SIZE(v) BFEXT(v, 0, 3)
#define RAM_SIZE(v) BFEXT(v, 0, 3)
#define RAM_WIDTH(v) BFEXT(v, 3, 1)
#define RAM_SPEED(v) BFEXT(v, 4, 2)
#define ROM_SIZE(v) BFEXT(v, 6, 2)
#define RAM_SPEED(v) BFEXT(v, 4, 2)
#define ROM_SIZE(v) BFEXT(v, 6, 2)
#define RAM_SPLIT(v) BFEXT(v, 16, 2)
#define XCVR(v) BFEXT(v, 20, 4)
#define XCVR(v) BFEXT(v, 20, 4)
#define AUTOSELECT(v) BFEXT(v, 24, 1)
/* Register Window 4: Xcvr/media bits */
@ -186,20 +186,20 @@
#define DownListPtr 0x24
#define FragAddr 0x28
#define FragLen 0x2c
#define TxFreeThreshold 0x2f
#define TxFreeThreshold 0x2f
#define UpPktStatus 0x30
#define UpListPtr 0x38
#define UpListPtr 0x38
/* The Rx and Tx descriptor lists. */
#define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
#define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
#define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
#define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
struct rx_desc_3com {
u32 next; /* Last entry points to 0 */
u32 status; /* FSH -> Frame Start Header */
u32 addr; /* Up to 63 addr/len pairs possible */
u32 length; /* Set LAST_FRAG to indicate last pair */
u32 next; /* Last entry points to 0 */
u32 status; /* FSH -> Frame Start Header */
u32 addr; /* Up to 63 addr/len pairs possible */
u32 length; /* Set LAST_FRAG to indicate last pair */
};
/* Values for the Rx status entry. */
@ -214,8 +214,8 @@ struct rx_desc_3com {
#define UDPChksumValid (1<<31)
struct tx_desc_3com {
u32 next; /* Last entry points to 0 */
u32 status; /* bits 0:12 length, others see below */
u32 next; /* Last entry points to 0 */
u32 status; /* bits 0:12 length, others see below */
u32 addr;
u32 length;
};
@ -227,7 +227,7 @@ struct tx_desc_3com {
#define AddIPChksum 0x02000000
#define AddTCPChksum 0x04000000
#define AddUDPChksum 0x08000000
#define TxIntrUploaded 0x80000000 /* IRQ when in FIFO, but maybe not sent. */
#define TxIntrUploaded 0x80000000 /* IRQ when in FIFO, but maybe not sent. */
/* XCVR Types */
@ -240,19 +240,19 @@ struct tx_desc_3com {
#define XCVR_MII 6
#define XCVR_NWAY 8
#define XCVR_ExtMII 9
#define XCVR_Default 10 /* I don't think this is correct -> should have been 0x10 if Auto Negotiate */
#define XCVR_Default 10 /* I don't think this is correct -> should have been 0x10 if Auto Negotiate */
struct descriptor { /* A generic descriptor. */
u32 next; /* Last entry points to 0 */
u32 status; /* FSH -> Frame Start Header */
u32 addr; /* Up to 63 addr/len pairs possible */
u32 length; /* Set LAST_FRAG to indicate last pair */
struct descriptor { /* A generic descriptor. */
u32 next; /* Last entry points to 0 */
u32 status; /* FSH -> Frame Start Header */
u32 addr; /* Up to 63 addr/len pairs possible */
u32 length; /* Set LAST_FRAG to indicate last pair */
};
/* Misc. definitions */
#define NUM_RX_DESC PKTBUFSRX * 10
#define NUM_TX_DESC 1 /* Number of TX descriptors */
#define NUM_RX_DESC PKTBUFSRX * 10
#define NUM_TX_DESC 1 /* Number of TX descriptors */
#define TOUT_LOOP 1000000
@ -266,17 +266,17 @@ struct descriptor { /* A generic descriptor. */
#undef ETH_DEBUG
#ifdef ETH_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
#define PRINTF(fmt,args...) printf (fmt ,##args)
#else
#define PRINTF(fmt,args...)
#endif
static struct rx_desc_3com *rx_ring; /* RX descriptor ring */
static struct tx_desc_3com *tx_ring; /* TX descriptor ring */
static u8 rx_buffer[NUM_RX_DESC][PKTSIZE_ALIGN]; /* storage for the incoming messages */
static int rx_next = 0; /* RX descriptor ring pointer */
static int tx_next = 0; /* TX descriptor ring pointer */
static struct rx_desc_3com *rx_ring; /* RX descriptor ring */
static struct tx_desc_3com *tx_ring; /* TX descriptor ring */
static u8 rx_buffer[NUM_RX_DESC][PKTSIZE_ALIGN];/* storage for the incoming messages */
static int rx_next = 0; /* RX descriptor ring pointer */
static int tx_next = 0; /* TX descriptor ring pointer */
static int tx_threshold;
static void init_rx_ring(struct eth_device* dev);
@ -369,171 +369,163 @@ static int issue_and_wait(struct eth_device* dev, int command)
return 0;
}
/* Determine network media type and set up 3com accordingly */
/* Determine network media type and set up 3com accordingly */
/* I think I'm going to start with something known first like 10baseT */
static int auto_negotiate(struct eth_device* dev)
static int auto_negotiate (struct eth_device *dev)
{
int i;
int i;
EL3WINDOW(dev, 1);
EL3WINDOW (dev, 1);
/* Wait for Auto negotiation to complete */
for (i = 0; i <= 1000; i++)
{
if (ETH_INW(dev, 2) & 0x04)
break;
udelay(100);
/* Wait for Auto negotiation to complete */
for (i = 0; i <= 1000; i++) {
if (ETH_INW (dev, 2) & 0x04)
break;
udelay (100);
if (i == 1000)
{
PRINTF("Error: Auto negotiation failed\n");
return 0;
if (i == 1000) {
PRINTF ("Error: Auto negotiation failed\n");
return 0;
}
}
}
return 1;
return 1;
}
void eth_interrupt(struct eth_device *dev)
void eth_interrupt (struct eth_device *dev)
{
u16 status = ETH_STATUS(dev);
u16 status = ETH_STATUS (dev);
printf("eth0: status = 0x%04x\n", status);
printf ("eth0: status = 0x%04x\n", status);
if (!(status & IntLatch))
return;
if (!(status & IntLatch))
return;
if (status & (1<<6))
{
ETH_CMD(dev, AckIntr | (1<<6));
printf("Acknowledged Interrupt command\n");
}
if (status & (1 << 6)) {
ETH_CMD (dev, AckIntr | (1 << 6));
printf ("Acknowledged Interrupt command\n");
}
if (status & DownComplete)
{
ETH_CMD(dev, AckIntr | DownComplete);
printf("Acknowledged DownComplete\n");
}
if (status & DownComplete) {
ETH_CMD (dev, AckIntr | DownComplete);
printf ("Acknowledged DownComplete\n");
}
if (status & UpComplete)
{
ETH_CMD(dev, AckIntr | UpComplete);
printf("Acknowledged UpComplete\n");
}
if (status & UpComplete) {
ETH_CMD (dev, AckIntr | UpComplete);
printf ("Acknowledged UpComplete\n");
}
ETH_CMD(dev, AckIntr | IntLatch);
printf("Acknowledged IntLatch\n");
ETH_CMD (dev, AckIntr | IntLatch);
printf ("Acknowledged IntLatch\n");
}
int eth_3com_initialize(bd_t *bis)
int eth_3com_initialize (bd_t * bis)
{
u32 eth_iobase = 0, status;
int card_number = 0, ret;
struct eth_device* dev;
struct eth_device *dev;
pci_dev_t devno;
char *s;
s = getenv("3com_base");
s = getenv ("3com_base");
/* Find ethernet controller on the PCI bus */
if ((devno = pci_find_device(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C, 0)) < 0)
{
PRINTF("Error: Cannot find the ethernet device on the PCI bus\n");
if ((devno =
pci_find_device (PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C,
0)) < 0) {
PRINTF ("Error: Cannot find the ethernet device on the PCI bus\n");
goto Done;
}
if (s)
{
unsigned long base = atoi(s);
pci_write_config_dword(devno, PCI_BASE_ADDRESS_0, base | 0x01);
if (s) {
unsigned long base = atoi (s);
pci_write_config_dword (devno, PCI_BASE_ADDRESS_0,
base | 0x01);
}
ret = pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &eth_iobase);
ret = pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &eth_iobase);
eth_iobase &= ~0xf;
PRINTF("eth: 3Com Found at Address: 0x%x\n", eth_iobase);
PRINTF ("eth: 3Com Found at Address: 0x%x\n", eth_iobase);
pci_write_config_dword(devno, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
pci_write_config_dword (devno, PCI_COMMAND,
PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER);
/* Check if I/O accesses and Bus Mastering are enabled */
/* Check if I/O accesses and Bus Mastering are enabled */
ret = pci_read_config_dword(devno, PCI_COMMAND, &status);
ret = pci_read_config_dword (devno, PCI_COMMAND, &status);
if (!(status & PCI_COMMAND_IO))
{
printf("Error: Cannot enable IO access.\n");
if (!(status & PCI_COMMAND_IO)) {
printf ("Error: Cannot enable IO access.\n");
goto Done;
}
if (!(status & PCI_COMMAND_MEMORY))
{
printf("Error: Cannot enable MEMORY access.\n");
if (!(status & PCI_COMMAND_MEMORY)) {
printf ("Error: Cannot enable MEMORY access.\n");
goto Done;
}
if (!(status & PCI_COMMAND_MASTER))
{
printf("Error: Cannot enable Bus Mastering.\n");
if (!(status & PCI_COMMAND_MASTER)) {
printf ("Error: Cannot enable Bus Mastering.\n");
goto Done;
}
dev = (struct eth_device*) malloc(sizeof(*dev)); /*struct eth_device)); */
dev = (struct eth_device *) malloc (sizeof (*dev)); /*struct eth_device)); */
sprintf(dev->name, "3Com 3c920c#%d", card_number);
sprintf (dev->name, "3Com 3c920c#%d", card_number);
dev->iobase = eth_iobase;
dev->priv = (void*) devno;
dev->init = eth_3com_init;
dev->halt = eth_3com_halt;
dev->send = eth_3com_send;
dev->recv = eth_3com_recv;
dev->priv = (void *) devno;
dev->init = eth_3com_init;
dev->halt = eth_3com_halt;
dev->send = eth_3com_send;
dev->recv = eth_3com_recv;
eth_register(dev);
eth_register (dev);
/* { */
/* char interrupt; */
/* devno = pci_find_device(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C, 0); */
/* pci_read_config_byte(devno, PCI_INTERRUPT_LINE, &interrupt); */
/* { */
/* char interrupt; */
/* devno = pci_find_device(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C, 0); */
/* pci_read_config_byte(devno, PCI_INTERRUPT_LINE, &interrupt); */
/* printf("Installing eth0 interrupt handler to %d\n", interrupt); */
/* irq_install_handler(interrupt, eth_interrupt, dev); */
/* } */
/* printf("Installing eth0 interrupt handler to %d\n", interrupt); */
/* irq_install_handler(interrupt, eth_interrupt, dev); */
/* } */
card_number++;
/* Set the latency timer for value */
s = getenv("3com_latency");
if (s)
{
ret = pci_write_config_byte(devno, PCI_LATENCY_TIMER, (unsigned char)atoi(s));
}
else ret = pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x0a);
s = getenv ("3com_latency");
if (s) {
ret = pci_write_config_byte (devno, PCI_LATENCY_TIMER,
(unsigned char) atoi (s));
} else
ret = pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x0a);
read_hw_addr(dev, bis); /* get the MAC address from Window 2*/
read_hw_addr (dev, bis); /* get the MAC address from Window 2 */
/* Reset the ethernet controller */
PRINTF ("Issuing reset command....\n");
if (!issue_and_wait(dev, TotalReset))
{
printf("Error: Cannot reset ethernet controller.\n");
if (!issue_and_wait (dev, TotalReset)) {
printf ("Error: Cannot reset ethernet controller.\n");
goto Done;
}
else
} else
PRINTF ("Ethernet controller reset.\n");
/* allocate memory for rx and tx rings */
if(!(rx_ring = memalign(sizeof(struct rx_desc_3com) * NUM_RX_DESC, 16)))
{
if (!(rx_ring = memalign (sizeof (struct rx_desc_3com) * NUM_RX_DESC, 16))) {
PRINTF ("Cannot allocate memory for RX_RING.....\n");
goto Done;
}
if (!(tx_ring = memalign(sizeof(struct tx_desc_3com) * NUM_TX_DESC, 16)))
{
if (!(tx_ring = memalign (sizeof (struct tx_desc_3com) * NUM_TX_DESC, 16))) {
PRINTF ("Cannot allocate memory for TX_RING.....\n");
goto Done;
}
@ -543,219 +535,208 @@ Done:
}
static int eth_3com_init(struct eth_device* dev, bd_t *bis)
static int eth_3com_init (struct eth_device *dev, bd_t * bis)
{
int i, status = 0;
int tx_cur, loop;
u16 status_enable, intr_enable;
struct descriptor *ias_cmd;
/* Determine what type of network the machine is connected to */
/* presently drops the connect to 10Mbps */
/* Determine what type of network the machine is connected to */
/* presently drops the connect to 10Mbps */
if (!auto_negotiate(dev))
{
printf("Error: Cannot determine network media.\n");
if (!auto_negotiate (dev)) {
printf ("Error: Cannot determine network media.\n");
goto Done;
}
issue_and_wait(dev, TxReset);
issue_and_wait(dev, RxReset|0x04);
issue_and_wait (dev, TxReset);
issue_and_wait (dev, RxReset | 0x04);
/* Switch to register set 7 for normal use. */
EL3WINDOW(dev, 7);
EL3WINDOW (dev, 7);
/* Initialize Rx and Tx rings */
init_rx_ring(dev);
purge_tx_ring(dev);
init_rx_ring (dev);
purge_tx_ring (dev);
ETH_CMD(dev, SetRxFilter | RxStation | RxBroadcast | RxProm);
ETH_CMD (dev, SetRxFilter | RxStation | RxBroadcast | RxProm);
issue_and_wait(dev,SetTxStart|0x07ff);
issue_and_wait (dev, SetTxStart | 0x07ff);
/* Below sets which indication bits to be seen. */
status_enable = SetStatusEnb | HostError | DownComplete | UpComplete | (1<<6);
ETH_CMD(dev, status_enable);
status_enable =
SetStatusEnb | HostError | DownComplete | UpComplete | (1 <<
6);
ETH_CMD (dev, status_enable);
/* Below sets no bits are to cause an interrupt since this is just polling */
intr_enable = SetIntrEnb;
intr_enable = SetIntrEnb;
/* intr_enable = SetIntrEnb | (1<<9) | (1<<10) | (1<<6); */
ETH_CMD(dev, intr_enable);
ETH_OUTB(dev, 127, UpPoll);
ETH_CMD (dev, intr_enable);
ETH_OUTB (dev, 127, UpPoll);
/* Ack all pending events, and set active indicator mask */
ETH_CMD(dev, AckIntr | IntLatch | TxAvailable | RxEarly | IntReq);
ETH_CMD(dev, intr_enable);
ETH_CMD (dev, AckIntr | IntLatch | TxAvailable | RxEarly | IntReq);
ETH_CMD (dev, intr_enable);
/* Tell the adapter where the RX ring is located */
issue_and_wait(dev,UpStall); /* Stall and set the UplistPtr */
ETH_OUTL(dev, (u32)&rx_ring[rx_next], UpListPtr);
ETH_CMD(dev, RxEnable); /* Enable the receiver. */
issue_and_wait(dev,UpUnstall);
issue_and_wait (dev, UpStall); /* Stall and set the UplistPtr */
ETH_OUTL (dev, (u32) & rx_ring[rx_next], UpListPtr);
ETH_CMD (dev, RxEnable); /* Enable the receiver. */
issue_and_wait (dev, UpUnstall);
/* Send the Individual Address Setup frame */
tx_cur = tx_next;
tx_next = ((tx_next+1) % NUM_TX_DESC);
tx_cur = tx_next;
tx_next = ((tx_next + 1) % NUM_TX_DESC);
ias_cmd = (struct descriptor *)&tx_ring[tx_cur];
ias_cmd->status = cpu_to_le32(1<<31); /* set DnIndicate bit. */
ias_cmd->next = 0;
ias_cmd->addr = cpu_to_le32((u32)&bis->bi_enetaddr[0]);
ias_cmd->length = cpu_to_le32(6 | LAST_FRAG);
ias_cmd = (struct descriptor *) &tx_ring[tx_cur];
ias_cmd->status = cpu_to_le32 (1 << 31); /* set DnIndicate bit. */
ias_cmd->next = 0;
ias_cmd->addr = cpu_to_le32 ((u32) & bis->bi_enetaddr[0]);
ias_cmd->length = cpu_to_le32 (6 | LAST_FRAG);
/* Tell the adapter where the TX ring is located */
ETH_CMD(dev, TxEnable); /* Enable transmitter. */
issue_and_wait(dev, DownStall); /* Stall and set the DownListPtr. */
ETH_OUTL(dev, (u32)&tx_ring[tx_cur], DownListPtr);
issue_and_wait(dev, DownUnstall);
for (i=0; !(ETH_STATUS(dev) & DownComplete); i++)
{
if (i >= TOUT_LOOP)
{
PRINTF("TX Ring status (Init): 0x%4x\n", le32_to_cpu(tx_ring[tx_cur].status));
PRINTF("ETH_STATUS: 0x%x\n", ETH_STATUS(dev));
ETH_CMD (dev, TxEnable); /* Enable transmitter. */
issue_and_wait (dev, DownStall); /* Stall and set the DownListPtr. */
ETH_OUTL (dev, (u32) & tx_ring[tx_cur], DownListPtr);
issue_and_wait (dev, DownUnstall);
for (i = 0; !(ETH_STATUS (dev) & DownComplete); i++) {
if (i >= TOUT_LOOP) {
PRINTF ("TX Ring status (Init): 0x%4x\n",
le32_to_cpu (tx_ring[tx_cur].status));
PRINTF ("ETH_STATUS: 0x%x\n", ETH_STATUS (dev));
goto Done;
}
}
if (ETH_STATUS(dev) & DownComplete) /* If DownLoad Complete ACK the bit */
{
ETH_CMD(dev, AckIntr | DownComplete); /* acknowledge the indication bit */
issue_and_wait(dev, DownStall); /* stall and clear DownListPtr */
ETH_OUTL(dev, 0, DownListPtr);
issue_and_wait(dev, DownUnstall);
if (ETH_STATUS (dev) & DownComplete) { /* If DownLoad Complete ACK the bit */
ETH_CMD (dev, AckIntr | DownComplete); /* acknowledge the indication bit */
issue_and_wait (dev, DownStall); /* stall and clear DownListPtr */
ETH_OUTL (dev, 0, DownListPtr);
issue_and_wait (dev, DownUnstall);
}
status = 1;
Done:
return status;
}
int eth_3com_send(struct eth_device* dev, volatile void *packet, int length)
int eth_3com_send (struct eth_device *dev, volatile void *packet, int length)
{
int i, status = 0;
int tx_cur;
if (length <= 0)
{
PRINTF("eth: bad packet size: %d\n", length);
if (length <= 0) {
PRINTF ("eth: bad packet size: %d\n", length);
goto Done;
}
tx_cur = tx_next;
tx_next = (tx_next+1) % NUM_TX_DESC;
tx_cur = tx_next;
tx_next = (tx_next + 1) % NUM_TX_DESC;
tx_ring[tx_cur].status = cpu_to_le32(1<<31); /* set DnIndicate bit */
tx_ring[tx_cur].next = 0;
tx_ring[tx_cur].addr = cpu_to_le32(((u32) packet));
tx_ring[tx_cur].length = cpu_to_le32(length | LAST_FRAG);
tx_ring[tx_cur].status = cpu_to_le32 (1 << 31); /* set DnIndicate bit */
tx_ring[tx_cur].next = 0;
tx_ring[tx_cur].addr = cpu_to_le32 (((u32) packet));
tx_ring[tx_cur].length = cpu_to_le32 (length | LAST_FRAG);
/* Send the packet */
issue_and_wait(dev, DownStall); /* stall and set the DownListPtr */
ETH_OUTL(dev, (u32) &tx_ring[tx_cur], DownListPtr);
issue_and_wait(dev, DownUnstall);
issue_and_wait (dev, DownStall); /* stall and set the DownListPtr */
ETH_OUTL (dev, (u32) & tx_ring[tx_cur], DownListPtr);
issue_and_wait (dev, DownUnstall);
for (i=0; !(ETH_STATUS(dev) & DownComplete); i++)
{
if (i >= TOUT_LOOP)
{
PRINTF("TX Ring status (send): 0x%4x\n", le32_to_cpu(tx_ring[tx_cur].status));
for (i = 0; !(ETH_STATUS (dev) & DownComplete); i++) {
if (i >= TOUT_LOOP) {
PRINTF ("TX Ring status (send): 0x%4x\n",
le32_to_cpu (tx_ring[tx_cur].status));
goto Done;
}
}
if (ETH_STATUS(dev) & DownComplete) /* If DownLoad Complete ACK the bit */
{
ETH_CMD(dev, AckIntr | DownComplete); /* acknowledge the indication bit */
issue_and_wait(dev, DownStall); /* stall and clear DownListPtr */
ETH_OUTL(dev, 0, DownListPtr);
issue_and_wait(dev, DownUnstall);
if (ETH_STATUS (dev) & DownComplete) { /* If DownLoad Complete ACK the bit */
ETH_CMD (dev, AckIntr | DownComplete); /* acknowledge the indication bit */
issue_and_wait (dev, DownStall); /* stall and clear DownListPtr */
ETH_OUTL (dev, 0, DownListPtr);
issue_and_wait (dev, DownUnstall);
}
status=1;
Done:
status = 1;
Done:
return status;
}
void PrintPacket (uchar *packet, int length)
void PrintPacket (uchar * packet, int length)
{
int loop;
uchar *ptr;
int loop;
uchar *ptr;
printf ("Printing packet of length %x.\n\n", length);
ptr = packet;
for (loop = 1; loop <= length; loop++)
{
for (loop = 1; loop <= length; loop++) {
printf ("%2x ", *ptr++);
if ((loop % 40)== 0)
if ((loop % 40) == 0)
printf ("\n");
}
}
int eth_3com_recv(struct eth_device* dev)
int eth_3com_recv (struct eth_device *dev)
{
u16 stat = 0;
u32 status;
int rx_prev, length = 0;
while (!(ETH_STATUS(dev) & UpComplete)) /* wait on receipt of packet */
while (!(ETH_STATUS (dev) & UpComplete)) /* wait on receipt of packet */
;
status = le32_to_cpu(rx_ring[rx_next].status); /* packet status */
status = le32_to_cpu (rx_ring[rx_next].status); /* packet status */
while (status & (1<<15))
{
while (status & (1 << 15)) {
/* A packet has been received */
if (status & (1<<15))
{
if (status & (1 << 15)) {
/* A valid frame received */
length = le32_to_cpu(rx_ring[rx_next].status) & 0x1fff; /* length is in bits 0 - 12 */
length = le32_to_cpu (rx_ring[rx_next].status) & 0x1fff; /* length is in bits 0 - 12 */
/* Pass the packet up to the protocol layers */
NetReceive((uchar *)le32_to_cpu(rx_ring[rx_next].addr), length);
rx_ring[rx_next].status = 0; /* clear the status word */
ETH_CMD(dev, AckIntr | UpComplete);
issue_and_wait(dev, UpUnstall);
}
else
if (stat & HostError)
{
NetReceive ((uchar *)
le32_to_cpu (rx_ring[rx_next].addr),
length);
rx_ring[rx_next].status = 0; /* clear the status word */
ETH_CMD (dev, AckIntr | UpComplete);
issue_and_wait (dev, UpUnstall);
} else if (stat & HostError) {
/* There was an error */
printf("Rx error status: 0x%4x\n", stat);
init_rx_ring(dev);
printf ("Rx error status: 0x%4x\n", stat);
init_rx_ring (dev);
goto Done;
}
rx_prev = rx_next;
rx_next = (rx_next + 1) % NUM_RX_DESC;
stat = ETH_STATUS(dev); /* register status */
status = le32_to_cpu(rx_ring[rx_next].status); /* packet status */
stat = ETH_STATUS (dev); /* register status */
status = le32_to_cpu (rx_ring[rx_next].status); /* packet status */
}
Done:
return length;
}
void eth_3com_halt(struct eth_device* dev)
void eth_3com_halt (struct eth_device *dev)
{
if (!(dev->iobase))
{
if (!(dev->iobase)) {
goto Done;
}
issue_and_wait(dev, DownStall); /* shut down transmit and receive */
issue_and_wait(dev, UpStall);
issue_and_wait(dev, RxDisable);
issue_and_wait(dev, TxDisable);
issue_and_wait (dev, DownStall); /* shut down transmit and receive */
issue_and_wait (dev, UpStall);
issue_and_wait (dev, RxDisable);
issue_and_wait (dev, TxDisable);
/* free(tx_ring); /###* release memory allocated to the DPD and UPD rings */
/* free(rx_ring); */
@ -764,41 +745,41 @@ Done:
return;
}
static void init_rx_ring(struct eth_device* dev)
static void init_rx_ring (struct eth_device *dev)
{
int i;
PRINTF("Initializing rx_ring. rx_buffer = %p\n", rx_buffer);
issue_and_wait(dev, UpStall);
PRINTF ("Initializing rx_ring. rx_buffer = %p\n", rx_buffer);
issue_and_wait (dev, UpStall);
for (i = 0; i < NUM_RX_DESC; i++)
{
rx_ring[i].next = cpu_to_le32(((u32) &rx_ring[(i+1) % NUM_RX_DESC]));
rx_ring[i].status = 0;
rx_ring[i].addr = cpu_to_le32(((u32) &rx_buffer[i][0]));
rx_ring[i].length = cpu_to_le32(PKTSIZE_ALIGN | LAST_FRAG);
for (i = 0; i < NUM_RX_DESC; i++) {
rx_ring[i].next =
cpu_to_le32 (((u32) &
rx_ring[(i + 1) % NUM_RX_DESC]));
rx_ring[i].status = 0;
rx_ring[i].addr = cpu_to_le32 (((u32) & rx_buffer[i][0]));
rx_ring[i].length = cpu_to_le32 (PKTSIZE_ALIGN | LAST_FRAG);
}
rx_next = 0;
}
static void purge_tx_ring(struct eth_device* dev)
static void purge_tx_ring (struct eth_device *dev)
{
int i;
PRINTF("Purging tx_ring.\n");
PRINTF ("Purging tx_ring.\n");
tx_next = 0;
tx_next = 0;
for (i = 0; i < NUM_TX_DESC; i++)
{
tx_ring[i].next = 0;
tx_ring[i].status = 0;
tx_ring[i].addr = 0;
tx_ring[i].length = 0;
for (i = 0; i < NUM_TX_DESC; i++) {
tx_ring[i].next = 0;
tx_ring[i].status = 0;
tx_ring[i].addr = 0;
tx_ring[i].length = 0;
}
}
static void read_hw_addr(struct eth_device* dev, bd_t *bis)
static void read_hw_addr (struct eth_device *dev, bd_t * bis)
{
u8 hw_addr[ETH_ALEN];
unsigned int eeprom[0x40];
@ -807,77 +788,77 @@ static void read_hw_addr(struct eth_device* dev, bd_t *bis)
/* Read the station address from the EEPROM. */
EL3WINDOW(dev, 0);
for (i = 0; i < 0x40; i++)
{
ETH_OUTW(dev, EEPROM_Read + i, Wn0EepromCmd);
EL3WINDOW (dev, 0);
for (i = 0; i < 0x40; i++) {
ETH_OUTW (dev, EEPROM_Read + i, Wn0EepromCmd);
/* Pause for at least 162 us. for the read to take place. */
for (timer = 10; timer >= 0; timer--)
{
udelay(162);
if ((ETH_INW(dev, Wn0EepromCmd) & 0x8000) == 0)
for (timer = 10; timer >= 0; timer--) {
udelay (162);
if ((ETH_INW (dev, Wn0EepromCmd) & 0x8000) == 0)
break;
}
eeprom[i] = ETH_INW(dev, Wn0EepromData);
eeprom[i] = ETH_INW (dev, Wn0EepromData);
}
/* Checksum calculation. I'm not sure about this part and there seems to be a bug on the 3com side of things */
for (i = 0; i < 0x21; i++)
checksum ^= eeprom[i];
checksum ^= eeprom[i];
checksum = (checksum ^ (checksum >> 8)) & 0xff;
if (checksum != 0xbb)
printf(" *** INVALID EEPROM CHECKSUM %4.4x *** \n", checksum);
printf (" *** INVALID EEPROM CHECKSUM %4.4x *** \n",
checksum);
for (i = 0, j = 0; i < 3; i++)
{
hw_addr[j++] = (u8)((eeprom[i+10] >> 8) & 0xff);
hw_addr[j++] = (u8)(eeprom[i+10] & 0xff);
for (i = 0, j = 0; i < 3; i++) {
hw_addr[j++] = (u8) ((eeprom[i + 10] >> 8) & 0xff);
hw_addr[j++] = (u8) (eeprom[i + 10] & 0xff);
}
/* MAC Address is in window 2, write value from EEPROM to window 2 */
EL3WINDOW(dev, 2);
EL3WINDOW (dev, 2);
for (i = 0; i < 6; i++)
ETH_OUTB(dev, hw_addr[i], i);
ETH_OUTB (dev, hw_addr[i], i);
for (j = 0; j < ETH_ALEN; j+=2)
{
hw_addr[j] = (u8)(ETH_INW(dev, j) & 0xff);
hw_addr[j+1] = (u8)((ETH_INW(dev, j) >> 8) & 0xff);
for (j = 0; j < ETH_ALEN; j += 2) {
hw_addr[j] = (u8) (ETH_INW (dev, j) & 0xff);
hw_addr[j + 1] = (u8) ((ETH_INW (dev, j) >> 8) & 0xff);
}
for (i=0;i<ETH_ALEN;i++)
{
if (hw_addr[i] != bis->bi_enetaddr[i])
{
/* printf("Warning: HW address don't match:\n"); */
/* printf("Address in 3Com Window 2 is " */
/* "%02X:%02X:%02X:%02X:%02X:%02X\n", */
/* hw_addr[0], hw_addr[1], hw_addr[2], */
/* hw_addr[3], hw_addr[4], hw_addr[5]); */
/* printf("Address used by U-Boot is " */
/* "%02X:%02X:%02X:%02X:%02X:%02X\n", */
/* bis->bi_enetaddr[0], bis->bi_enetaddr[1], */
/* bis->bi_enetaddr[2], bis->bi_enetaddr[3], */
/* bis->bi_enetaddr[4], bis->bi_enetaddr[5]); */
/* goto Done; */
char buffer[256];
if (bis->bi_enetaddr[0] == 0 && bis->bi_enetaddr[1] == 0 &&
bis->bi_enetaddr[2] == 0 && bis->bi_enetaddr[3] == 0 &&
bis->bi_enetaddr[4] == 0 && bis->bi_enetaddr[5] == 0)
{
for (i = 0; i < ETH_ALEN; i++) {
if (hw_addr[i] != bis->bi_enetaddr[i]) {
/* printf("Warning: HW address don't match:\n"); */
/* printf("Address in 3Com Window 2 is " */
/* "%02X:%02X:%02X:%02X:%02X:%02X\n", */
/* hw_addr[0], hw_addr[1], hw_addr[2], */
/* hw_addr[3], hw_addr[4], hw_addr[5]); */
/* printf("Address used by U-Boot is " */
/* "%02X:%02X:%02X:%02X:%02X:%02X\n", */
/* bis->bi_enetaddr[0], bis->bi_enetaddr[1], */
/* bis->bi_enetaddr[2], bis->bi_enetaddr[3], */
/* bis->bi_enetaddr[4], bis->bi_enetaddr[5]); */
/* goto Done; */
char buffer[256];
sprintf(buffer, "%02X:%02X:%02X:%02X:%02X:%02X",
hw_addr[0], hw_addr[1], hw_addr[2],
hw_addr[3], hw_addr[4], hw_addr[5]);
setenv("ethaddr", buffer);
}
if (bis->bi_enetaddr[0] == 0
&& bis->bi_enetaddr[1] == 0
&& bis->bi_enetaddr[2] == 0
&& bis->bi_enetaddr[3] == 0
&& bis->bi_enetaddr[4] == 0
&& bis->bi_enetaddr[5] == 0) {
sprintf (buffer,
"%02X:%02X:%02X:%02X:%02X:%02X",
hw_addr[0], hw_addr[1], hw_addr[2],
hw_addr[3], hw_addr[4], hw_addr[5]);
setenv ("ethaddr", buffer);
}
}
}
for(i=0; i<ETH_ALEN; i++) dev->enetaddr[i] = hw_addr[i];
for (i = 0; i < ETH_ALEN; i++)
dev->enetaddr[i] = hw_addr[i];
Done:
return;

6
board/MAI/AmigaOneG3SE/interrupts.c
View File

@ -176,9 +176,9 @@ external_interrupt(struct pt_regs *regs)
else {
PRINTF ("\nBogus External Interrupt IRQ %d\n", irq);
/*
* turn off the bogus interrupt, otherwise it
* might repeat forever
*/
* turn off the bogus interrupt, otherwise it
* might repeat forever
*/
unmask = 0;
}

455
board/MAI/AmigaOneG3SE/ps2kbd.c
View File

@ -58,7 +58,7 @@ void i8259_unmask_irq(unsigned int irq);
#define KBD_STAT_KOBF 0x01
#define KBD_STAT_IBF 0x02
#define KBD_STAT_SYS 0x04
#define KBD_STAT_CD 0x08
#define KBD_STAT_CD 0x08
#define KBD_STAT_LOCK 0x10
#define KBD_STAT_MOBF 0x20
#define KBD_STAT_TI_OUT 0x40
@ -71,50 +71,50 @@ void i8259_unmask_irq(unsigned int irq);
* Keyboard Controller Commands
*/
#define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */
#define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */
#define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */
#define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */
#define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */
#define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */
#define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */
#define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */
#define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */
#define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */
#define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */
#define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */
#define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */
#define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */
#define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */
#define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */
#define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */
#define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */
#define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */
#define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if
initiated by the auxiliary device */
#define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */
#define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */
/*
* Keyboard Commands
*/
#define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */
#define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */
#define KBD_CMD_ENABLE 0xF4 /* Enable scanning */
#define KBD_CMD_DISABLE 0xF5 /* Disable scanning */
#define KBD_CMD_RESET 0xFF /* Reset */
#define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */
#define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */
#define KBD_CMD_ENABLE 0xF4 /* Enable scanning */
#define KBD_CMD_DISABLE 0xF5 /* Disable scanning */
#define KBD_CMD_RESET 0xFF /* Reset */
/*
* Keyboard Replies
*/
#define KBD_REPLY_POR 0xAA /* Power on reset */
#define KBD_REPLY_ACK 0xFA /* Command ACK */
#define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */
#define KBD_REPLY_POR 0xAA /* Power on reset */
#define KBD_REPLY_ACK 0xFA /* Command ACK */
#define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */
/*
* Status Register Bits
*/
#define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */
#define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */
#define KBD_STAT_SELFTEST 0x04 /* Self test successful */
#define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */
#define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */
#define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */
#define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */
#define KBD_STAT_PERR 0x80 /* Parity error */
#define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */
#define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */
#define KBD_STAT_SELFTEST 0x04 /* Self test successful */
#define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */
#define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */
#define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */
#define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */
#define KBD_STAT_PERR 0x80 /* Parity error */
#define AUX_STAT_OBF (KBD_STAT_OBF | KBD_STAT_MOUSE_OBF)
@ -122,24 +122,24 @@ void i8259_unmask_irq(unsigned int irq);
* Controller Mode Register Bits
*/
#define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */
#define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */
#define KBD_MODE_SYS 0x04 /* The system flag (?) */
#define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */
#define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */
#define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */
#define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */
#define KBD_MODE_SYS 0x04 /* The system flag (?) */
#define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */
#define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */
#define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */
#define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */
#define KBD_MODE_RFU 0x80
#define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */
#define KBD_MODE_RFU 0x80
#define KDB_DATA_PORT 0x60
#define KDB_DATA_PORT 0x60
#define KDB_COMMAND_PORT 0x64
#define LED_SCR 0x01 /* scroll lock led */
#define LED_CAP 0x04 /* caps lock led */
#define LED_NUM 0x02 /* num lock led */
#define LED_SCR 0x01 /* scroll lock led */
#define LED_CAP 0x04 /* caps lock led */
#define LED_NUM 0x02 /* num lock led */
#define KBD_BUFFER_LEN 0x20 /* size of the keyboardbuffer */
#define KBD_BUFFER_LEN 0x20 /* size of the keyboardbuffer */
static volatile char kbd_buffer[KBD_BUFFER_LEN];
@ -194,21 +194,22 @@ static unsigned char kbd_ctrl_xlate[] = {
* Init
******************************************************************/
int isa_kbd_init(void)
int isa_kbd_init (void)
{
char* result;
result=kbd_initialize();
if (result != NULL)
{
result = kbd_initialize();
char *result;
result = kbd_initialize ();
if (result != NULL) {
result = kbd_initialize ();
}
if(result==NULL) {
printf("AT Keyboard initialized\n");
irq_install_handler(KBD_INTERRUPT, (interrupt_handler_t *)kbd_interrupt, NULL);
if (result == NULL) {
printf ("AT Keyboard initialized\n");
irq_install_handler (KBD_INTERRUPT,
(interrupt_handler_t *) kbd_interrupt,
NULL);
return (1);
}
else {
printf("%s\n",result);
} else {
printf ("%s\n", result);
return (-1);
}
}
@ -225,20 +226,20 @@ int overwrite_console (void)
int drv_isa_kbd_init (void)
{
int error;
device_t kbddev ;
device_t kbddev ;
char *stdinname = getenv ("stdin");
if(isa_kbd_init()==-1)
return -1;
memset (&kbddev, 0, sizeof(kbddev));
strcpy(kbddev.name, DEVNAME);
kbddev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
kbddev.putc = NULL ;
memset (&kbddev, 0, sizeof(kbddev));
strcpy(kbddev.name, DEVNAME);
kbddev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
kbddev.putc = NULL ;
kbddev.puts = NULL ;
kbddev.getc = kbd_getc ;
kbddev.tstc = kbd_testc ;
error = device_register (&kbddev);
error = device_register (&kbddev);
if(error==0) {
/* check if this is the standard input device */
if(strcmp(stdinname,DEVNAME)==0) {
@ -301,7 +302,6 @@ int kbd_getc(void)
}
/* set LEDs */
void kbd_set_leds(void)
@ -322,140 +322,139 @@ void kbd_set_leds(void)
kbd_send_data(leds);
}
void handle_keyboard_event(unsigned char scancode)
void handle_keyboard_event (unsigned char scancode)
{
unsigned char keycode;
/* Convert scancode to keycode */
PRINTF("scancode %x\n",scancode);
if(scancode==0xe0) {
e0=1; /* special charakters */
PRINTF ("scancode %x\n", scancode);
if (scancode == 0xe0) {
e0 = 1; /* special charakters */
return;
}
if(e0==1) {
e0=0; /* delete flag */
if(!( ((scancode&0x7F)==0x38)|| /* the right ctrl key */
((scancode&0x7F)==0x1D)|| /* the right alt key */
((scancode&0x7F)==0x35)|| /* the right '/' key */
((scancode&0x7F)==0x1C)|| /* the right enter key */
((scancode)==0x48)|| /* arrow up */
((scancode)==0x50)|| /* arrow down */
((scancode)==0x4b)|| /* arrow left */
((scancode)==0x4d))) /* arrow right */
if (e0 == 1) {
e0 = 0; /* delete flag */
if (!(((scancode & 0x7F) == 0x38) || /* the right ctrl key */
((scancode & 0x7F) == 0x1D) || /* the right alt key */
((scancode & 0x7F) == 0x35) || /* the right '/' key */
((scancode & 0x7F) == 0x1C) || /* the right enter key */
((scancode) == 0x48) || /* arrow up */
((scancode) == 0x50) || /* arrow down */
((scancode) == 0x4b) || /* arrow left */
((scancode) == 0x4d)))
/* arrow right */
/* we swallow unknown e0 codes */
return;
}
/* special cntrl keys */
switch(scancode)
{
switch (scancode) {
case 0x48:
kbd_put_queue(27);
kbd_put_queue(91);
kbd_put_queue('A');
return;
kbd_put_queue (27);
kbd_put_queue (91);
kbd_put_queue ('A');
return;
case 0x50:
kbd_put_queue(27);
kbd_put_queue(91);
kbd_put_queue('B');
return;
kbd_put_queue (27);
kbd_put_queue (91);
kbd_put_queue ('B');
return;
case 0x4b:
kbd_put_queue(27);
kbd_put_queue(91);
kbd_put_queue('D');
return;
kbd_put_queue (27);
kbd_put_queue (91);
kbd_put_queue ('D');
return;
case 0x4D:
kbd_put_queue(27);
kbd_put_queue(91);
kbd_put_queue('C');
return;
case 0x58: /* F12 key */
if (ctrl == 1)
{
extern int console_changed;
setenv("stdin", DEVNAME);
setenv("stdout", "vga");
console_changed = 1;
}
return;
kbd_put_queue (27);
kbd_put_queue (91);
kbd_put_queue ('C');
return;
case 0x58: /* F12 key */
if (ctrl == 1) {
extern int console_changed;
setenv ("stdin", DEVNAME);
setenv ("stdout", "vga");
console_changed = 1;
}
return;
case 0x2A:
case 0x36: /* shift pressed */
shift=1;
return; /* do nothing else */
case 0xAA:
case 0xB6: /* shift released */
shift=0;
return; /* do nothing else */
case 0x38: /* alt pressed */
alt=1;
return; /* do nothing else */
case 0xB8: /* alt released */
alt=0;
return; /* do nothing else */
case 0x1d: /* ctrl pressed */
ctrl=1;
return; /* do nothing else */
case 0x9d: /* ctrl released */
ctrl=0;
return; /* do nothing else */
case 0x46: /* scrollock pressed */
scroll_lock=~scroll_lock;
kbd_set_leds();
return; /* do nothing else */
case 0x3A: /* capslock pressed */
caps_lock=~caps_lock;
kbd_set_leds();
return;
case 0x45: /* numlock pressed */
num_lock=~num_lock;
kbd_set_leds();
return;
case 0xC6: /* scroll lock released */
case 0xC5: /* num lock released */
case 0xBA: /* caps lock released */
return; /* just swallow */
case 0x36: /* shift pressed */
shift = 1;
return; /* do nothing else */
case 0xAA:
case 0xB6: /* shift released */
shift = 0;
return; /* do nothing else */
case 0x38: /* alt pressed */
alt = 1;
return; /* do nothing else */
case 0xB8: /* alt released */
alt = 0;
return; /* do nothing else */
case 0x1d: /* ctrl pressed */
ctrl = 1;
return; /* do nothing else */
case 0x9d: /* ctrl released */
ctrl = 0;
return; /* do nothing else */
case 0x46: /* scrollock pressed */
scroll_lock = ~scroll_lock;
kbd_set_leds ();
return; /* do nothing else */
case 0x3A: /* capslock pressed */
caps_lock = ~caps_lock;
kbd_set_leds ();
return;
case 0x45: /* numlock pressed */
num_lock = ~num_lock;
kbd_set_leds ();
return;
case 0xC6: /* scroll lock released */
case 0xC5: /* num lock released */
case 0xBA: /* caps lock released */
return; /* just swallow */
}
if((scancode&0x80)==0x80) /* key released */
if ((scancode & 0x80) == 0x80) /* key released */
return;
/* now, decide which table we need */
if(scancode > (sizeof(kbd_plain_xlate)/sizeof(kbd_plain_xlate[0]))) { /* scancode not in list */
PRINTF("unkown scancode %X\n",scancode);
return; /* swallow it */
if (scancode > (sizeof (kbd_plain_xlate) / sizeof (kbd_plain_xlate[0]))) { /* scancode not in list */
PRINTF ("unkown scancode %X\n", scancode);
return; /* swallow it */
}
/* setup plain code first */
keycode=kbd_plain_xlate[scancode];
if(caps_lock==1) { /* caps_lock is pressed, overwrite plain code */
if(scancode > (sizeof(kbd_shift_xlate)/sizeof(kbd_shift_xlate[0]))) { /* scancode not in list */
PRINTF("unkown caps-locked scancode %X\n",scancode);
return; /* swallow it */
keycode = kbd_plain_xlate[scancode];
if (caps_lock == 1) { /* caps_lock is pressed, overwrite plain code */
if (scancode > (sizeof (kbd_shift_xlate) / sizeof (kbd_shift_xlate[0]))) { /* scancode not in list */
PRINTF ("unkown caps-locked scancode %X\n", scancode);
return; /* swallow it */
}
keycode=kbd_shift_xlate[scancode];
if(keycode<'A') { /* we only want the alphas capital */
keycode=kbd_plain_xlate[scancode];
keycode = kbd_shift_xlate[scancode];
if (keycode < 'A') { /* we only want the alphas capital */
keycode = kbd_plain_xlate[scancode];
}
}
if(shift==1) { /* shift overwrites caps_lock */
if(scancode > (sizeof(kbd_shift_xlate)/sizeof(kbd_shift_xlate[0]))) { /* scancode not in list */
PRINTF("unkown shifted scancode %X\n",scancode);
return; /* swallow it */
if (shift == 1) { /* shift overwrites caps_lock */
if (scancode > (sizeof (kbd_shift_xlate) / sizeof (kbd_shift_xlate[0]))) { /* scancode not in list */
PRINTF ("unkown shifted scancode %X\n", scancode);
return; /* swallow it */
}
keycode=kbd_shift_xlate[scancode];
keycode = kbd_shift_xlate[scancode];
}
if(ctrl==1) { /* ctrl overwrites caps_lock and shift */
if(scancode > (sizeof(kbd_ctrl_xlate)/sizeof(kbd_ctrl_xlate[0]))) { /* scancode not in list */
PRINTF("unkown ctrl scancode %X\n",scancode);
return; /* swallow it */
if (ctrl == 1) { /* ctrl overwrites caps_lock and shift */
if (scancode > (sizeof (kbd_ctrl_xlate) / sizeof (kbd_ctrl_xlate[0]))) { /* scancode not in list */
PRINTF ("unkown ctrl scancode %X\n", scancode);
return; /* swallow it */
}
keycode=kbd_ctrl_xlate[scancode];
keycode = kbd_ctrl_xlate[scancode];
}
/* check if valid keycode */
if(keycode==0xff) {
PRINTF("unkown scancode %X\n",scancode);
return; /* swallow unknown codes */
if (keycode == 0xff) {
PRINTF ("unkown scancode %X\n", scancode);
return; /* swallow unknown codes */
}
kbd_put_queue(keycode);
PRINTF("%x\n",keycode);
kbd_put_queue (keycode);
PRINTF ("%x\n", keycode);
}
/*
@ -463,34 +462,31 @@ void handle_keyboard_event(unsigned char scancode)
* appropriate action.
*
*/
unsigned char handle_kbd_event(void)
unsigned char handle_kbd_event (void)
{
unsigned char status = kbd_read_status();
unsigned char status = kbd_read_status ();
unsigned int work = 10000;
while ((--work > 0) && (status & KBD_STAT_OBF)) {
unsigned char scancode;
scancode = kbd_read_input();
scancode = kbd_read_input ();
/* Error bytes must be ignored to make the
Synaptics touchpads compaq use work */
/* Ignore error bytes */
if (!(status & (KBD_STAT_GTO | KBD_STAT_PERR)))
{
if (status & KBD_STAT_MOUSE_OBF)
; /* not supported: handle_mouse_event(scancode); */
if (!(status & (KBD_STAT_GTO | KBD_STAT_PERR))) {
if (status & KBD_STAT_MOUSE_OBF); /* not supported: handle_mouse_event(scancode); */
else
handle_keyboard_event(scancode);
handle_keyboard_event (scancode);
}
status = kbd_read_status();
status = kbd_read_status ();
}
if (!work)
PRINTF("pc_keyb: controller jammed (0x%02X).\n", status);
PRINTF ("pc_keyb: controller jammed (0x%02X).\n", status);
return status;
}
/******************************************************************************
* Lowlevel Part of keyboard section
*/
@ -529,90 +525,91 @@ int kbd_read_data(void)
return val;
}
int kbd_wait_for_input(void)
int kbd_wait_for_input (void)
{
unsigned long timeout;
int val;
timeout = KBD_TIMEOUT;
val=kbd_read_data();
while(val < 0)
{
if(timeout--==0)
val = kbd_read_data ();
while (val < 0) {
if (timeout-- == 0)
return -1;
udelay(1000);
val=kbd_read_data();
udelay (1000);
val = kbd_read_data ();
}
return val;
}
int kb_wait(void)
int kb_wait (void)
{
unsigned long timeout = KBC_TIMEOUT * 10;
do {
unsigned char status = handle_kbd_event();
unsigned char status = handle_kbd_event ();
if (!(status & KBD_STAT_IBF))
return 0; /* ok */
udelay(1000);
return 0; /* ok */
udelay (1000);
timeout--;
} while (timeout);
return 1;
}
void kbd_write_command_w(int data)
void kbd_write_command_w (int data)
{
if(kb_wait())
PRINTF("timeout in kbd_write_command_w\n");
kbd_write_command(data);
if (kb_wait ())
PRINTF ("timeout in kbd_write_command_w\n");
kbd_write_command (data);
}
void kbd_write_output_w(int data)
void kbd_write_output_w (int data)
{
if(kb_wait())
PRINTF("timeout in kbd_write_output_w\n");
kbd_write_output(data);
if (kb_wait ())
PRINTF ("timeout in kbd_write_output_w\n");
kbd_write_output (data);
}
void kbd_send_data(unsigned char data)
void kbd_send_data (unsigned char data)
{
unsigned char status;
i8259_mask_irq(KBD_INTERRUPT); /* disable interrupt */
kbd_write_output_w(data);
status = kbd_wait_for_input();
i8259_mask_irq (KBD_INTERRUPT); /* disable interrupt */
kbd_write_output_w (data);
status = kbd_wait_for_input ();
if (status == KBD_REPLY_ACK)
i8259_unmask_irq(KBD_INTERRUPT); /* enable interrupt */
i8259_unmask_irq (KBD_INTERRUPT); /* enable interrupt */
}
char * kbd_initialize(void)
char *kbd_initialize (void)
{
int status;
in_pointer = 0; /* delete in Buffer */
in_pointer = 0; /* delete in Buffer */
out_pointer = 0;
/*
* Test the keyboard interface.
* This seems to be the only way to get it going.
* If the test is successful a x55 is placed in the input buffer.
*/
kbd_write_command_w(KBD_CCMD_SELF_TEST);
if (kbd_wait_for_input() != 0x55)
kbd_write_command_w (KBD_CCMD_SELF_TEST);
if (kbd_wait_for_input () != 0x55)
return "Kbd: failed self test";
/*
* Perform a keyboard interface test. This causes the controller
* to test the keyboard clock and data lines. The results of the
* test are placed in the input buffer.
*/
kbd_write_command_w(KBD_CCMD_KBD_TEST);
if (kbd_wait_for_input() != 0x00)
kbd_write_command_w (KBD_CCMD_KBD_TEST);
if (kbd_wait_for_input () != 0x00)
return "Kbd: interface failed self test";
/*
* Enable the keyboard by allowing the keyboard clock to run.
*/
kbd_write_command_w(KBD_CCMD_KBD_ENABLE);
status = kbd_wait_for_input();
kbd_write_command_w (KBD_CCMD_KBD_ENABLE);
status = kbd_wait_for_input ();
/*
* Reset keyboard. If the read times out
* then the assumption is that no keyboard is
@ -622,17 +619,16 @@ char * kbd_initialize(void)
* Set up to try again if the keyboard asks for RESEND.
*/
do {
kbd_write_output_w(KBD_CMD_RESET);
status = kbd_wait_for_input();
kbd_write_output_w (KBD_CMD_RESET);
status = kbd_wait_for_input ();
if (status == KBD_REPLY_ACK)
break;
if (status != KBD_REPLY_RESEND)
{
PRINTF("status: %X\n",status);
if (status != KBD_REPLY_RESEND) {
PRINTF ("status: %X\n", status);
return "Kbd: reset failed, no ACK";
}
} while (1);
if (kbd_wait_for_input() != KBD_REPLY_POR)
if (kbd_wait_for_input () != KBD_REPLY_POR)
return "Kbd: reset failed, no POR";
/*
@ -642,44 +638,43 @@ char * kbd_initialize(void)
* Set up to try again if the keyboard asks for RESEND.
*/
do {
kbd_write_output_w(KBD_CMD_DISABLE);
status = kbd_wait_for_input();
kbd_write_output_w (KBD_CMD_DISABLE);
status = kbd_wait_for_input ();
if (status == KBD_REPLY_ACK)
break;
if (status != KBD_REPLY_RESEND)
return "Kbd: disable keyboard: no ACK";
} while (1);
kbd_write_command_w(KBD_CCMD_WRITE_MODE);
kbd_write_output_w(KBD_MODE_KBD_INT
| KBD_MODE_SYS
| KBD_MODE_DISABLE_MOUSE
| KBD_MODE_KCC);
kbd_write_command_w (KBD_CCMD_WRITE_MODE);
kbd_write_output_w (KBD_MODE_KBD_INT
| KBD_MODE_SYS
| KBD_MODE_DISABLE_MOUSE | KBD_MODE_KCC);
/* AMCC powerpc portables need this to use scan-code set 1 -- Cort */
kbd_write_command_w(KBD_CCMD_READ_MODE);
if (!(kbd_wait_for_input() & KBD_MODE_KCC)) {
kbd_write_command_w (KBD_CCMD_READ_MODE);
if (!(kbd_wait_for_input () & KBD_MODE_KCC)) {
/*
* If the controller does not support conversion,
* Set the keyboard to scan-code set 1.
*/
kbd_write_output_w(0xF0);
kbd_wait_for_input();
kbd_write_output_w(0x01);
kbd_wait_for_input();
kbd_write_output_w (0xF0);
kbd_wait_for_input ();
kbd_write_output_w (0x01);
kbd_wait_for_input ();
}
kbd_write_output_w(KBD_CMD_ENABLE);
if (kbd_wait_for_input() != KBD_REPLY_ACK)
kbd_write_output_w (KBD_CMD_ENABLE);
if (kbd_wait_for_input () != KBD_REPLY_ACK)
return "Kbd: enable keyboard: no ACK";
/*
* Finally, set the typematic rate to maximum.
*/
kbd_write_output_w(KBD_CMD_SET_RATE);
if (kbd_wait_for_input() != KBD_REPLY_ACK)
kbd_write_output_w (KBD_CMD_SET_RATE);
if (kbd_wait_for_input () != KBD_REPLY_ACK)
return "Kbd: Set rate: no ACK";
kbd_write_output_w(0x00);
if (kbd_wait_for_input() != KBD_REPLY_ACK)
kbd_write_output_w (0x00);
if (kbd_wait_for_input () != KBD_REPLY_ACK)
return "Kbd: Set rate: no ACK";
return NULL;
}

4
board/MAI/AmigaOneG3SE/start.txt
View File

@ -39,11 +39,11 @@
DIM0_TIM_CTL_0 = 0x737d737d (0xc9)
/* DRAM timing control for dimm0 & dimm1; set wait one clock */
/* cycle for next data access */
/* cycle for next data access */
DIM2_TIM_CTL_0 = 0x737d737d (0xca)
/* DRAM timing control for dimm2 & dimm3; set wait one clock */
/* cycle for next data access */
/* cycle for next data access */
DIM0_BNK0_CTL_0 = BNK0_RAM_SIZ_128MB (0x90)
/* set dimm0 bank0 for 128 MB */

8
board/MAI/AmigaOneG3SE/u-boot.lds
View File

@ -40,11 +40,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }

2
board/MAI/AmigaOneG3SE/usb_uhci.c
View File

@ -522,7 +522,7 @@ void usb_check_int_chain(void)
link=swap_32(td_int[i].link) & 0xfffffff0; /* next in chain */
td=(uhci_td_t *)link; /* assign it */
/* all interrupt TDs are finally linked to the td_int[0].
* so we process all until we find the td_int[0].
* so we process all until we find the td_int[0].
* if int0 chain points to a QH, we're also done
*/
while(((i>0) && (link != (unsigned long)&td_int[0])) ||

8
board/MAI/AmigaOneG3SE/via686.c
View File

@ -97,7 +97,7 @@ void via_isa_init(pci_dev_t dev, struct pci_config_table *table)
pci_write_config_byte(dev, 0x80, 0);
pci_write_config_byte(dev, 0x85, 0x01);
/* pci_write_config_byte(dev, 0x77, 0x00); */
/* pci_write_config_byte(dev, 0x77, 0x00); */
}
}
@ -212,7 +212,7 @@ void via_cfgfunc_via686(struct pci_controller *host, pci_dev_t dev, struct pci_c
}
__asm (" .globl via_calibrate_time_base \n"
"via_calibrate_time_base: \n"
"via_calibrate_time_base: \n"
" lis 9, 0xfe00 \n"
" li 0, 0x00 \n"
" mttbu 0 \n"
@ -262,9 +262,9 @@ void ide_led(uchar led, uchar status)
/* unsigned char c = in_byte(0x92); */
/* if (!status) */
/* out_byte(0x92, c | 0xC0); */
/* out_byte(0x92, c | 0xC0); */
/* else */
/* out_byte(0x92, c & ~0xC0); */
/* out_byte(0x92, c & ~0xC0); */
}

90
board/MAI/menu/menu.h
View File

@ -4,15 +4,14 @@
/* A single menu */
typedef void (*menu_finish_callback)(struct menu_s *menu);
typedef struct menu_s
{
char *name; /* Menu name */
int num_options; /* Number of options in this menu */
int flags; /* Various flags - see below */
int option_align; /* Aligns options to a field width of this much characters if != 0 */
typedef struct menu_s {
char *name; /* Menu name */
int num_options; /* Number of options in this menu */
int flags; /* Various flags - see below */
int option_align; /* Aligns options to a field width of this much characters if != 0 */
struct menu_option_s **options; /* Pointer to this menu's options */
menu_finish_callback callback; /* Called when the menu closes */
struct menu_option_s **options; /* Pointer to this menu's options */
menu_finish_callback callback; /* Called when the menu closes */
} menu_t;
/*
@ -23,13 +22,12 @@ typedef struct menu_s
* sys : pointer for system-specific data, init to NULL and don't touch
*/
#define OPTION_PREAMBLE \
int type; \
char *name; \
char *help; \
int id; \
void *sys; \
#define OPTION_PREAMBLE \
int type; \
char *name; \
char *help; \
int id; \
void *sys;
/*
* Menu option types.
@ -110,59 +108,49 @@ typedef struct menu_text_s
#define MENU_SELECTION_TYPE 3
typedef struct menu_select_option_s
{
char *map_from; /* Map this variable contents ... */
char *map_to; /* ... to this menu text and vice versa */
typedef struct menu_select_option_s {
char *map_from; /* Map this variable contents ... */
char *map_to; /* ... to this menu text and vice versa */
} menu_select_option_t;
typedef struct menu_select_s
{
OPTION_PREAMBLE
int num_options; /* Number of mappings */
menu_select_option_t **options;
/* Option list array */
typedef struct menu_select_s {
OPTION_PREAMBLE int num_options; /* Number of mappings */
menu_select_option_t **options;
/* Option list array */
} menu_select_t;
#define MENU_ROUTINE_TYPE 4
typedef void (*menu_routine_callback)(struct menu_routine_s *);
typedef void (*menu_routine_callback) (struct menu_routine_s *);
typedef struct menu_routine_s
{
OPTION_PREAMBLE
menu_routine_callback callback;
/* routine to be called */
void *user_data; /* User data, don't care for system */
typedef struct menu_routine_s {
OPTION_PREAMBLE menu_routine_callback callback;
/* routine to be called */
void *user_data; /* User data, don't care for system */
} menu_routine_t;
#define MENU_CUSTOM_TYPE 5
typedef void (*menu_custom_draw)(struct menu_custom_s *);
typedef void (*menu_custom_key)(struct menu_custom_s *, int);
typedef void (*menu_custom_draw) (struct menu_custom_s *);
typedef void (*menu_custom_key) (struct menu_custom_s *, int);
typedef struct menu_custom_s
{
OPTION_PREAMBLE
menu_custom_draw drawfunc;
menu_custom_key keyfunc;
void *user_data;
typedef struct menu_custom_s {
OPTION_PREAMBLE menu_custom_draw drawfunc;
menu_custom_key keyfunc;
void *user_data;
} menu_custom_t;
/*
* The menu option superstructure
*/
typedef struct menu_option_s
{
union
{
menu_submenu_t m_sub_menu;
menu_boolean_t m_boolean;
menu_text_t m_text;
menu_select_t m_select;
menu_routine_t m_routine;
};
typedef struct menu_option_s {
union {
menu_submenu_t m_sub_menu;
menu_boolean_t m_boolean;
menu_text_t m_text;
menu_select_t m_select;
menu_routine_t m_routine;
};
} menu_option_t;
/* Init the menu system. Returns <0 on error */

4
board/Marvell/common/bootseq.txt
View File

@ -56,7 +56,7 @@ in_flash:
setup stack pointer (r1)
setup GOT
call cpu_init_f
debug leds
debug leds
board_init_f: (common/board.c)
board_early_init_f:
remap gt regs?
@ -74,7 +74,7 @@ in_flash:
dram_size()
setup PCI slave memory mappings
setup SCS
setup monitor
setup monitor
alloc board info struct
init bd struct
relocate_code: (cpu/mpc7xxx/start.S)

2
board/Marvell/common/flash.c
View File

@ -23,7 +23,7 @@
/*
* flash.c - flash support for the 512k, 8bit boot flash
and the 8MB 32bit extra flash on the DB64360
and the 8MB 32bit extra flash on the DB64360
* most of this file was based on the existing U-Boot
* flash drivers.
*

2
board/Marvell/db64360/mpsc.c
View File

@ -425,7 +425,7 @@ void mpsc_sdma_init (void)
(MV64360_SDMA_WIN_ACCESS_FULL <<
(MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
/* Setup MPSC internal address space base address */
/* Setup MPSC internal address space base address */
GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS);
/* no high address remap*/

6
board/Marvell/db64360/mpsc.h
View File

@ -67,9 +67,9 @@ extern int (*mpsc_test_char)(void);
#define TX_STOP 0x00010000
#define RX_ENABLE 0x00000080
#define SDMA_RX_ABORT (1 << 15)
#define SDMA_TX_ABORT (1 << 31)
#define MPSC_TX_ABORT (1 << 7)
#define SDMA_RX_ABORT (1 << 15)
#define SDMA_TX_ABORT (1 << 31)
#define MPSC_TX_ABORT (1 << 7)
#define MPSC_RX_ABORT (1 << 23)
#define MPSC_ENTER_HUNT (1 << 31)

62
board/Marvell/db64360/mv_eth.c
View File

@ -1391,7 +1391,7 @@ u32 mv_get_internal_sram_base (void)
* port_phy_addr).
*
* INPUT:
* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct
* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct
*
* OUTPUT:
* See description.
@ -1551,7 +1551,7 @@ static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl)
* ether_init_rx_desc_ring for Rx queues).
*
* INPUT:
* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct
* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct
*
* OUTPUT:
* Ethernet port is ready to receive and transmit.
@ -1641,7 +1641,7 @@ static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl)
* INPUT:
* ETH_PORT eth_port_num Port number.
* char * p_addr Address to be set
* ETH_QUEUE queue Rx queue number for this MAC address.
* ETH_QUEUE queue Rx queue number for this MAC address.
*
* OUTPUT:
* Set MAC address low and high registers. also calls eth_port_uc_addr()
@ -1679,10 +1679,10 @@ static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
* parameters.
*
* INPUT:
* ETH_PORT eth_port_num Port number.
* ETH_PORT eth_port_num Port number.
* unsigned char uc_nibble Unicast MAC Address last nibble.
* ETH_QUEUE queue Rx queue number for this MAC address.
* int option 0 = Add, 1 = remove address.
* ETH_QUEUE queue Rx queue number for this MAC address.
* int option 0 = Add, 1 = remove address.
*
* OUTPUT:
* This function add/removes MAC addresses from the port unicast address
@ -1761,10 +1761,10 @@ static bool eth_port_uc_addr (ETH_PORT eth_port_num,
* In this case, the function calculates the CRC-8bit value and calls
* eth_port_omc_addr() routine to set the Other Multicast Table.
* INPUT:
* ETH_PORT eth_port_num Port number.
* unsigned char *p_addr Unicast MAC Address.
* ETH_QUEUE queue Rx queue number for this MAC address.
* int option 0 = Add, 1 = remove address.
* ETH_PORT eth_port_num Port number.
* unsigned char *p_addr Unicast MAC Address.
* ETH_QUEUE queue Rx queue number for this MAC address.
* int option 0 = Add, 1 = remove address.
*
* OUTPUT:
* See description.
@ -1895,10 +1895,10 @@ static void eth_port_mc_addr (ETH_PORT eth_port_num,
* according to the argument given.
*
* INPUT:
* ETH_PORT eth_port_num Port number.
* unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits).
* ETH_QUEUE queue Rx queue number for this MAC address.
* int option 0 = Add, 1 = remove address.
* ETH_PORT eth_port_num Port number.
* unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits).
* ETH_QUEUE queue Rx queue number for this MAC address.
* int option 0 = Add, 1 = remove address.
*
* OUTPUT:
* See description.
@ -1959,10 +1959,10 @@ static bool eth_port_smc_addr (ETH_PORT eth_port_num,
* CRC-8 argument given.
*
* INPUT:
* ETH_PORT eth_port_num Port number.
* unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1).
* ETH_QUEUE queue Rx queue number for this MAC address.
* int option 0 = Add, 1 = remove address.
* ETH_PORT eth_port_num Port number.
* unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1).
* ETH_QUEUE queue Rx queue number for this MAC address.
* int option 0 = Add, 1 = remove address.
*
* OUTPUT:
* See description.
@ -2203,7 +2203,7 @@ static bool ethernet_phy_reset (ETH_PORT eth_port_num)
* eth_port_reset - Reset Ethernet port
*
* DESCRIPTION:
* This routine resets the chip by aborting any SDMA engine activity and
* This routine resets the chip by aborting any SDMA engine activity and
* clearing the MIB counters. The Receiver and the Transmit unit are in
* idle state after this command is performed and the port is disabled.
*
@ -2556,9 +2556,9 @@ static void eth_set_access_control (ETH_PORT eth_port_num,
*
* INPUT:
* ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
* ETH_QUEUE rx_queue Number of Rx queue.
* int rx_desc_num Number of Rx descriptors
* int rx_buff_size Size of Rx buffer
* ETH_QUEUE rx_queue Number of Rx queue.
* int rx_desc_num Number of Rx descriptors
* int rx_buff_size Size of Rx buffer
* unsigned int rx_desc_base_addr Rx descriptors memory area base addr.
* unsigned int rx_buff_base_addr Rx buffer memory area base addr.
*
@ -2650,9 +2650,9 @@ static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
*
* INPUT:
* ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
* ETH_QUEUE tx_queue Number of Tx queue.
* int tx_desc_num Number of Tx descriptors
* int tx_buff_size Size of Tx buffer
* ETH_QUEUE tx_queue Number of Tx queue.
* int tx_desc_num Number of Tx descriptors
* int tx_buff_size Size of Tx buffer
* unsigned int tx_desc_base_addr Tx descriptors memory area base addr.
* unsigned int tx_buff_base_addr Tx buffer memory area base addr.
*
@ -2745,7 +2745,7 @@ static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
*
* INPUT:
* ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
* ETH_QUEUE tx_queue Number of Tx queue.
* ETH_QUEUE tx_queue Number of Tx queue.
* PKT_INFO *p_pkt_info User packet buffer.
*
* OUTPUT:
@ -2861,7 +2861,7 @@ static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl,
*
* INPUT:
* ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
* ETH_QUEUE tx_queue Number of Tx queue.
* ETH_QUEUE tx_queue Number of Tx queue.
* PKT_INFO *p_pkt_info User packet buffer.
*
* OUTPUT:
@ -2930,7 +2930,7 @@ static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO *
* eth_port_receive - Get received information from Rx ring.
*
* DESCRIPTION:
* This routine returns the received data to the caller. There is no
* This routine returns the received data to the caller. There is no
* data copying during routine operation. All information is returned
* using pointer to packet information struct passed from the caller.
* If the routine exhausts Rx ring resources then the resource error flag
@ -2938,7 +2938,7 @@ static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO *
*
* INPUT:
* ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
* ETH_QUEUE rx_queue Number of Rx queue.
* ETH_QUEUE rx_queue Number of Rx queue.
* PKT_INFO *p_pkt_info User packet buffer.
*
* OUTPUT:
@ -2980,7 +2980,7 @@ static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl,
/* Nothing to receive... */
if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
/* DP(printf("Rx: command_status: %08x\n", command_status)); */
/* DP(printf("Rx: command_status: %08x\n", command_status)); */
D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
/* DP(printf("\nETH_END_OF_JOB ...\n"));*/
return ETH_END_OF_JOB;
@ -3019,7 +3019,7 @@ static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl,
*
* INPUT:
* ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
* ETH_QUEUE rx_queue Number of Rx queue.
* ETH_QUEUE rx_queue Number of Rx queue.
* PKT_INFO *p_pkt_info Information on the returned buffer.
*
* OUTPUT:

8
board/Marvell/db64360/u-boot.lds
View File

@ -37,11 +37,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }

2
board/Marvell/db64460/mpsc.c
View File

@ -425,7 +425,7 @@ void mpsc_sdma_init (void)
(MV64460_SDMA_WIN_ACCESS_FULL <<
(MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
/* Setup MPSC internal address space base address */
/* Setup MPSC internal address space base address */
GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS);
/* no high address remap*/

6
board/Marvell/db64460/mpsc.h
View File

@ -67,9 +67,9 @@ extern int (*mpsc_test_char)(void);
#define TX_STOP 0x00010000
#define RX_ENABLE 0x00000080
#define SDMA_RX_ABORT (1 << 15)
#define SDMA_TX_ABORT (1 << 31)
#define MPSC_TX_ABORT (1 << 7)
#define SDMA_RX_ABORT (1 << 15)
#define SDMA_TX_ABORT (1 << 31)
#define MPSC_TX_ABORT (1 << 7)
#define MPSC_RX_ABORT (1 << 23)
#define MPSC_ENTER_HUNT (1 << 31)

62
board/Marvell/db64460/mv_eth.c
View File

@ -1390,7 +1390,7 @@ u32 mv_get_internal_sram_base (void)
* port_phy_addr).
*
* INPUT:
* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct
* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct
*
* OUTPUT:
* See description.
@ -1550,7 +1550,7 @@ static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl)
* ether_init_rx_desc_ring for Rx queues).
*
* INPUT:
* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct
* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct
*
* OUTPUT:
* Ethernet port is ready to receive and transmit.
@ -1640,7 +1640,7 @@ static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl)
* INPUT:
* ETH_PORT eth_port_num Port number.
* char * p_addr Address to be set
* ETH_QUEUE queue Rx queue number for this MAC address.
* ETH_QUEUE queue Rx queue number for this MAC address.
*
* OUTPUT:
* Set MAC address low and high registers. also calls eth_port_uc_addr()
@ -1678,10 +1678,10 @@ static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
* parameters.
*
* INPUT:
* ETH_PORT eth_port_num Port number.
* ETH_PORT eth_port_num Port number.
* unsigned char uc_nibble Unicast MAC Address last nibble.
* ETH_QUEUE queue Rx queue number for this MAC address.
* int option 0 = Add, 1 = remove address.
* ETH_QUEUE queue Rx queue number for this MAC address.
* int option 0 = Add, 1 = remove address.
*
* OUTPUT:
* This function add/removes MAC addresses from the port unicast address
@ -1760,10 +1760,10 @@ static bool eth_port_uc_addr (ETH_PORT eth_port_num,
* In this case, the function calculates the CRC-8bit value and calls
* eth_port_omc_addr() routine to set the Other Multicast Table.
* INPUT:
* ETH_PORT eth_port_num Port number.
* unsigned char *p_addr Unicast MAC Address.
* ETH_QUEUE queue Rx queue number for this MAC address.
* int option 0 = Add, 1 = remove address.
* ETH_PORT eth_port_num Port number.
* unsigned char *p_addr Unicast MAC Address.
* ETH_QUEUE queue Rx queue number for this MAC address.
* int option 0 = Add, 1 = remove address.
*
* OUTPUT:
* See description.
@ -1894,10 +1894,10 @@ static void eth_port_mc_addr (ETH_PORT eth_port_num,
* according to the argument given.
*
* INPUT:
* ETH_PORT eth_port_num Port number.
* unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits).
* ETH_QUEUE queue Rx queue number for this MAC address.
* int option 0 = Add, 1 = remove address.
* ETH_PORT eth_port_num Port number.
* unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits).
* ETH_QUEUE queue Rx queue number for this MAC address.
* int option 0 = Add, 1 = remove address.
*
* OUTPUT:
* See description.
@ -1958,10 +1958,10 @@ static bool eth_port_smc_addr (ETH_PORT eth_port_num,
* CRC-8 argument given.
*
* INPUT:
* ETH_PORT eth_port_num Port number.
* unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1).
* ETH_QUEUE queue Rx queue number for this MAC address.
* int option 0 = Add, 1 = remove address.
* ETH_PORT eth_port_num Port number.
* unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1).
* ETH_QUEUE queue Rx queue number for this MAC address.
* int option 0 = Add, 1 = remove address.
*
* OUTPUT:
* See description.
@ -2202,7 +2202,7 @@ static bool ethernet_phy_reset (ETH_PORT eth_port_num)
* eth_port_reset - Reset Ethernet port
*
* DESCRIPTION:
* This routine resets the chip by aborting any SDMA engine activity and
* This routine resets the chip by aborting any SDMA engine activity and
* clearing the MIB counters. The Receiver and the Transmit unit are in
* idle state after this command is performed and the port is disabled.
*
@ -2555,9 +2555,9 @@ static void eth_set_access_control (ETH_PORT eth_port_num,
*
* INPUT:
* ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
* ETH_QUEUE rx_queue Number of Rx queue.
* int rx_desc_num Number of Rx descriptors
* int rx_buff_size Size of Rx buffer
* ETH_QUEUE rx_queue Number of Rx queue.
* int rx_desc_num Number of Rx descriptors
* int rx_buff_size Size of Rx buffer
* unsigned int rx_desc_base_addr Rx descriptors memory area base addr.
* unsigned int rx_buff_base_addr Rx buffer memory area base addr.
*
@ -2649,9 +2649,9 @@ static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
*
* INPUT:
* ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
* ETH_QUEUE tx_queue Number of Tx queue.
* int tx_desc_num Number of Tx descriptors
* int tx_buff_size Size of Tx buffer
* ETH_QUEUE tx_queue Number of Tx queue.
* int tx_desc_num Number of Tx descriptors
* int tx_buff_size Size of Tx buffer
* unsigned int tx_desc_base_addr Tx descriptors memory area base addr.
* unsigned int tx_buff_base_addr Tx buffer memory area base addr.
*
@ -2744,7 +2744,7 @@ static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
*
* INPUT:
* ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
* ETH_QUEUE tx_queue Number of Tx queue.
* ETH_QUEUE tx_queue Number of Tx queue.
* PKT_INFO *p_pkt_info User packet buffer.
*
* OUTPUT:
@ -2860,7 +2860,7 @@ static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl,
*
* INPUT:
* ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
* ETH_QUEUE tx_queue Number of Tx queue.
* ETH_QUEUE tx_queue Number of Tx queue.
* PKT_INFO *p_pkt_info User packet buffer.
*
* OUTPUT:
@ -2929,7 +2929,7 @@ static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO *
* eth_port_receive - Get received information from Rx ring.
*
* DESCRIPTION:
* This routine returns the received data to the caller. There is no
* This routine returns the received data to the caller. There is no
* data copying during routine operation. All information is returned
* using pointer to packet information struct passed from the caller.
* If the routine exhausts Rx ring resources then the resource error flag
@ -2937,7 +2937,7 @@ static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO *
*
* INPUT:
* ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
* ETH_QUEUE rx_queue Number of Rx queue.
* ETH_QUEUE rx_queue Number of Rx queue.
* PKT_INFO *p_pkt_info User packet buffer.
*
* OUTPUT:
@ -2979,7 +2979,7 @@ static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl,
/* Nothing to receive... */
if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
/* DP(printf("Rx: command_status: %08x\n", command_status)); */
/* DP(printf("Rx: command_status: %08x\n", command_status)); */
D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
/* DP(printf("\nETH_END_OF_JOB ...\n"));*/
return ETH_END_OF_JOB;
@ -3018,7 +3018,7 @@ static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl,
*
* INPUT:
* ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
* ETH_QUEUE rx_queue Number of Rx queue.
* ETH_QUEUE rx_queue Number of Rx queue.
* PKT_INFO *p_pkt_info Information on the returned buffer.
*
* OUTPUT:

8
board/Marvell/db64460/u-boot.lds
View File

@ -37,11 +37,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
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.rel.ctors : { *(.rel.ctors) }

24
board/MigoR/lowlevel_init.S
View File

@ -87,7 +87,7 @@ lowlevel_init:
mov.w r0, @r1
mov.l DLLFRQ_A, r1 ! 20080115
mov.l DLLFRQ_D, r0 ! 20080115
mov.l DLLFRQ_D, r0 ! 20080115
mov.l r0, @r1
mov.l FRQCR_A, r1 ! 0xA4150000 Frequency control register
@ -100,11 +100,11 @@ lowlevel_init:
bsc_init:
mov.l CMNCR_A, r1 ! CMNCR address -> R1
mov.l CMNCR_D, r0 ! CMNCR data -> R0
mov.l CMNCR_D, r0 ! CMNCR data -> R0
mov.l r0, @r1 ! CMNCR set
mov.l CS0BCR_A, r1 ! CS0BCR address -> R1
mov.l CS0BCR_D, r0 ! CS0BCR data -> R0
mov.l CS0BCR_D, r0 ! CS0BCR data -> R0
mov.l r0, @r1 ! CS0BCR set
mov.l CS4BCR_A, r1 ! CS4BCR address -> R1
@ -112,35 +112,35 @@ bsc_init:
mov.l r0, @r1 ! CS4BCR set
mov.l CS5ABCR_A, r1 ! CS5ABCR address -> R1
mov.l CS5ABCR_D, r0 ! CS5ABCR data -> R0
mov.l CS5ABCR_D, r0 ! CS5ABCR data -> R0
mov.l r0, @r1 ! CS5ABCR set
mov.l CS5BBCR_A, r1 ! CS5BBCR address -> R1
mov.l CS5BBCR_D, r0 ! CS5BBCR data -> R0
mov.l CS5BBCR_D, r0 ! CS5BBCR data -> R0
mov.l r0, @r1 ! CS5BBCR set
mov.l CS6ABCR_A, r1 ! CS6ABCR address -> R1
mov.l CS6ABCR_D, r0 ! CS6ABCR data -> R0
mov.l CS6ABCR_D, r0 ! CS6ABCR data -> R0
mov.l r0, @r1 ! CS6ABCR set
mov.l CS0WCR_A, r1 ! CS0WCR address -> R1
mov.l CS0WCR_D, r0 ! CS0WCR data -> R0
mov.l CS0WCR_D, r0 ! CS0WCR data -> R0
mov.l r0, @r1 ! CS0WCR set
mov.l CS4WCR_A, r1 ! CS4WCR address -> R1
mov.l CS4WCR_D, r0 ! CS4WCR data -> R0
mov.l CS4WCR_D, r0 ! CS4WCR data -> R0
mov.l r0, @r1 ! CS4WCR set
mov.l CS5AWCR_A, r1 ! CS5AWCR address -> R1
mov.l CS5AWCR_D, r0 ! CS5AWCR data -> R0
mov.l CS5AWCR_D, r0 ! CS5AWCR data -> R0
mov.l r0, @r1 ! CS5AWCR set
mov.l CS5BWCR_A, r1 ! CS5BWCR address -> R1
mov.l CS5BWCR_D, r0 ! CS5BWCR data -> R0
mov.l CS5BWCR_D, r0 ! CS5BWCR data -> R0
mov.l r0, @r1 ! CS5BWCR set
mov.l CS6AWCR_A, r1 ! CS6AWCR address -> R1
mov.l CS6AWCR_D, r0 ! CS6AWCR data -> R0
mov.l CS6AWCR_D, r0 ! CS6AWCR data -> R0
mov.l r0, @r1 ! CS6AWCR set
! SDRAM initialization
@ -173,7 +173,7 @@ bsc_init:
mov.l r0, @r1
mov.l SDMR3_A, r1 ! SDMR3 address -> R1
mov #0x00, r0 ! SDMR3 data -> R0
mov #0x00, r0 ! SDMR3 data -> R0
mov.b r0, @r1 ! SDMR3 set
! BL bit off (init = ON) (?!?)

8
board/RPXClassic/u-boot.lds
View File

@ -33,11 +33,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
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.rel.ctors : { *(.rel.ctors) }

8
board/RPXClassic/u-boot.lds.debug
View File

@ -33,11 +33,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
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.rel.ctors : { *(.rel.ctors) }

2
board/RPXlite/flash.c
View File

@ -31,7 +31,7 @@
* are not tested.
*
* (?) Does an RPXLite board which
* does not use AM29LV800 flash memory exist ?
* does not use AM29LV800 flash memory exist ?
* I don't know...
*/

8
board/RPXlite/u-boot.lds
View File

@ -33,11 +33,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
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8
board/RPXlite/u-boot.lds.debug
View File

@ -33,11 +33,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
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.rel.ctors : { *(.rel.ctors) }

2
board/RPXlite_dw/RPXlite_dw.c
View File

@ -124,7 +124,7 @@ long int initdram (int board_type)
memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */
/*Disable Periodic timer A. */
udelay(200);
udelay(200);
/* perform SDRAM initializsation sequence */

6
board/RPXlite_dw/flash.c
View File

@ -31,7 +31,7 @@
* are not tested.
*
* (?) Does an RPXLite board which
* does not use AM29LV800 flash memory exist ?
* does not use AM29LV800 flash memory exist ?
* I don't know...
*/
@ -178,8 +178,8 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
value = addr[0] ;
switch (value & 0x00FF00FF) {
case AMD_MANUFACT: /* AMD_MANUFACT=0x00010001 in flash.h. */
info->flash_id = FLASH_MAN_AMD; /* FLASH_MAN_AMD=0x00000000 in flash.h.*/
case AMD_MANUFACT: /* AMD_MANUFACT =0x00010001 in flash.h */
info->flash_id = FLASH_MAN_AMD; /* FLASH_MAN_AMD=0x00000000 in flash.h */
break;
case FUJ_MANUFACT:
info->flash_id = FLASH_MAN_FUJ;

8
board/RPXlite_dw/u-boot.lds
View File

@ -33,11 +33,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }

8
board/RPXlite_dw/u-boot.lds.debug
View File

@ -33,11 +33,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
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.rela.rodata : { *(.rela.rodata) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }

8
board/RRvision/u-boot.lds
View File

@ -33,11 +33,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
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.rela.rodata : { *(.rela.rodata) }
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.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }

2
board/a3000/Makefile
View File

@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o flash.o
COBJS = $(BOARD).o flash.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

2
board/a3000/a3000.c
View File

@ -82,7 +82,7 @@ static struct pci_config_table pci_a3000_config_table[] = {
PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER }},
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
PCI_ANY_ID, 0x15, PCI_ANY_ID, /* PCI slot2 */
PCI_ANY_ID, 0x15, PCI_ANY_ID, /* PCI slot2 */
pci_cfgfunc_config_device, { PCI_ENET2_IOADDR,
PCI_ENET2_MEMADDR,
PCI_COMMAND_IO |

8
board/adder/u-boot.lds
View File

@ -33,11 +33,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
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.rela.rodata : { *(.rela.rodata) }
.rela.data : { *(.rela.data) }
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.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }

8
board/ads5121/u-boot.lds
View File

@ -30,11 +30,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
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.rela.data : { *(.rela.data) }
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.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }

8
board/amcc/acadia/u-boot-nand.lds
View File

@ -31,11 +31,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }

8
board/amcc/acadia/u-boot.lds
View File

@ -38,11 +38,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }

126
board/amcc/bamboo/bamboo.c
View File

@ -280,86 +280,86 @@ const unsigned char cfg_simulate_spd_eeprom[128] = {
#define EBC0_BNAP_SMALL_FLASH \
EBC0_BNAP_BME_DISABLED | \
EBC0_BNAP_TWT_ENCODE(6) | \
EBC0_BNAP_CSN_ENCODE(0) | \
EBC0_BNAP_OEN_ENCODE(1) | \
EBC0_BNAP_WBN_ENCODE(1) | \
EBC0_BNAP_WBF_ENCODE(3) | \
EBC0_BNAP_TH_ENCODE(1) | \
EBC0_BNAP_RE_ENABLED | \
EBC0_BNAP_SOR_DELAYED | \
EBC0_BNAP_BEM_WRITEONLY | \
EBC0_BNAP_CSN_ENCODE(0) | \
EBC0_BNAP_OEN_ENCODE(1) | \
EBC0_BNAP_WBN_ENCODE(1) | \
EBC0_BNAP_WBF_ENCODE(3) | \
EBC0_BNAP_TH_ENCODE(1) | \
EBC0_BNAP_RE_ENABLED | \
EBC0_BNAP_SOR_DELAYED | \
EBC0_BNAP_BEM_WRITEONLY | \
EBC0_BNAP_PEN_DISABLED
#define EBC0_BNCR_SMALL_FLASH_CS0 \
EBC0_BNCR_BAS_ENCODE(0xFFF00000) | \
EBC0_BNCR_BS_1MB | \
EBC0_BNCR_BU_RW | \
EBC0_BNCR_BAS_ENCODE(0xFFF00000) | \
EBC0_BNCR_BS_1MB | \
EBC0_BNCR_BU_RW | \
EBC0_BNCR_BW_8BIT
#define EBC0_BNCR_SMALL_FLASH_CS4 \
EBC0_BNCR_BAS_ENCODE(0x87F00000) | \
EBC0_BNCR_BS_1MB | \
EBC0_BNCR_BU_RW | \
EBC0_BNCR_BAS_ENCODE(0x87F00000) | \
EBC0_BNCR_BS_1MB | \
EBC0_BNCR_BU_RW | \
EBC0_BNCR_BW_8BIT
/* Large Flash or SRAM */
#define EBC0_BNAP_LARGE_FLASH_OR_SRAM \
EBC0_BNAP_BME_DISABLED | \
EBC0_BNAP_TWT_ENCODE(8) | \
EBC0_BNAP_CSN_ENCODE(0) | \
EBC0_BNAP_OEN_ENCODE(1) | \
EBC0_BNAP_WBN_ENCODE(1) | \
EBC0_BNAP_WBF_ENCODE(1) | \
EBC0_BNAP_TH_ENCODE(2) | \
EBC0_BNAP_SOR_DELAYED | \
EBC0_BNAP_BEM_RW | \
EBC0_BNAP_BME_DISABLED | \
EBC0_BNAP_TWT_ENCODE(8) | \
EBC0_BNAP_CSN_ENCODE(0) | \
EBC0_BNAP_OEN_ENCODE(1) | \
EBC0_BNAP_WBN_ENCODE(1) | \
EBC0_BNAP_WBF_ENCODE(1) | \
EBC0_BNAP_TH_ENCODE(2) | \
EBC0_BNAP_SOR_DELAYED | \
EBC0_BNAP_BEM_RW | \
EBC0_BNAP_PEN_DISABLED
#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0 \
EBC0_BNCR_BAS_ENCODE(0xFF800000) | \
EBC0_BNCR_BS_8MB | \
EBC0_BNCR_BU_RW | \
#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0 \
EBC0_BNCR_BAS_ENCODE(0xFF800000) | \
EBC0_BNCR_BS_8MB | \
EBC0_BNCR_BU_RW | \
EBC0_BNCR_BW_16BIT
#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4 \
EBC0_BNCR_BAS_ENCODE(0x87800000) | \
EBC0_BNCR_BS_8MB | \
EBC0_BNCR_BU_RW | \
#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4 \
EBC0_BNCR_BAS_ENCODE(0x87800000) | \
EBC0_BNCR_BS_8MB | \
EBC0_BNCR_BU_RW | \
EBC0_BNCR_BW_16BIT
/* NVRAM - FPGA */
#define EBC0_BNAP_NVRAM_FPGA \
EBC0_BNAP_BME_DISABLED | \
EBC0_BNAP_TWT_ENCODE(9) | \
EBC0_BNAP_CSN_ENCODE(0) | \
EBC0_BNAP_OEN_ENCODE(1) | \
EBC0_BNAP_WBN_ENCODE(1) | \
EBC0_BNAP_WBF_ENCODE(0) | \
EBC0_BNAP_TH_ENCODE(2) | \
EBC0_BNAP_RE_ENABLED | \
EBC0_BNAP_SOR_DELAYED | \
EBC0_BNAP_BEM_WRITEONLY | \
EBC0_BNAP_BME_DISABLED | \
EBC0_BNAP_TWT_ENCODE(9) | \
EBC0_BNAP_CSN_ENCODE(0) | \
EBC0_BNAP_OEN_ENCODE(1) | \
EBC0_BNAP_WBN_ENCODE(1) | \
EBC0_BNAP_WBF_ENCODE(0) | \
EBC0_BNAP_TH_ENCODE(2) | \
EBC0_BNAP_RE_ENABLED | \
EBC0_BNAP_SOR_DELAYED | \
EBC0_BNAP_BEM_WRITEONLY | \
EBC0_BNAP_PEN_DISABLED
#define EBC0_BNCR_NVRAM_FPGA_CS5 \
EBC0_BNCR_BAS_ENCODE(0x80000000) | \
EBC0_BNCR_BS_1MB | \
EBC0_BNCR_BU_RW | \
EBC0_BNCR_BAS_ENCODE(0x80000000) | \
EBC0_BNCR_BS_1MB | \
EBC0_BNCR_BU_RW | \
EBC0_BNCR_BW_8BIT
/* Nand Flash */
#define EBC0_BNAP_NAND_FLASH \
EBC0_BNAP_BME_DISABLED | \
EBC0_BNAP_TWT_ENCODE(3) | \
EBC0_BNAP_CSN_ENCODE(0) | \
EBC0_BNAP_OEN_ENCODE(0) | \
EBC0_BNAP_WBN_ENCODE(0) | \
EBC0_BNAP_WBF_ENCODE(0) | \
EBC0_BNAP_TH_ENCODE(1) | \
EBC0_BNAP_RE_ENABLED | \
EBC0_BNAP_SOR_NOT_DELAYED | \
EBC0_BNAP_BEM_RW | \
EBC0_BNAP_BME_DISABLED | \
EBC0_BNAP_TWT_ENCODE(3) | \
EBC0_BNAP_CSN_ENCODE(0) | \
EBC0_BNAP_OEN_ENCODE(0) | \
EBC0_BNAP_WBN_ENCODE(0) | \
EBC0_BNAP_WBF_ENCODE(0) | \
EBC0_BNAP_TH_ENCODE(1) | \
EBC0_BNAP_RE_ENABLED | \
EBC0_BNAP_SOR_NOT_DELAYED | \
EBC0_BNAP_BEM_RW | \
EBC0_BNAP_PEN_DISABLED
@ -367,22 +367,22 @@ const unsigned char cfg_simulate_spd_eeprom[128] = {
/* NAND0 */
#define EBC0_BNCR_NAND_FLASH_CS1 \
EBC0_BNCR_BAS_ENCODE(0x90000000) | \
EBC0_BNCR_BS_1MB | \
EBC0_BNCR_BU_RW | \
EBC0_BNCR_BAS_ENCODE(0x90000000) | \
EBC0_BNCR_BS_1MB | \
EBC0_BNCR_BU_RW | \
EBC0_BNCR_BW_32BIT
/* NAND1 - Bank2 */
#define EBC0_BNCR_NAND_FLASH_CS2 \
EBC0_BNCR_BAS_ENCODE(0x94000000) | \
EBC0_BNCR_BS_1MB | \
EBC0_BNCR_BU_RW | \
EBC0_BNCR_BAS_ENCODE(0x94000000) | \
EBC0_BNCR_BS_1MB | \
EBC0_BNCR_BU_RW | \
EBC0_BNCR_BW_32BIT
/* NAND1 - Bank3 */
#define EBC0_BNCR_NAND_FLASH_CS3 \
EBC0_BNCR_BAS_ENCODE(0x94000000) | \
EBC0_BNCR_BS_1MB | \
EBC0_BNCR_BU_RW | \
EBC0_BNCR_BAS_ENCODE(0x94000000) | \
EBC0_BNCR_BS_1MB | \
EBC0_BNCR_BU_RW | \
EBC0_BNCR_BW_32BIT
int board_early_init_f(void)

8
board/amcc/bamboo/u-boot-nand.lds
View File

@ -31,11 +31,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }

8
board/amcc/bamboo/u-boot.lds
View File

@ -43,11 +43,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }

8
board/amcc/bubinga/u-boot.lds
View File

@ -38,11 +38,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }

8
board/amcc/canyonlands/u-boot-nand.lds
View File

@ -31,11 +31,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }

8
board/amcc/canyonlands/u-boot.lds
View File

@ -43,11 +43,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }

8
board/amcc/ebony/u-boot.lds
View File

@ -43,11 +43,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }

22
board/amcc/katmai/katmai.c
View File

@ -441,27 +441,27 @@ void pcie_setup_hoses(int busno)
pci_register_hose(hose);
if (is_end_point(i)) {
ppc4xx_setup_pcie_endpoint(hose, i);
ppc4xx_setup_pcie_endpoint(hose, i);
/*
* Reson for no scanning is endpoint can not generate
* upstream configuration accesses.
*/
*/
} else {
ppc4xx_setup_pcie_rootpoint(hose, i);
ppc4xx_setup_pcie_rootpoint(hose, i);
env = getenv ("pciscandelay");
if (env != NULL) {
delay = simple_strtoul(env, NULL, 10);
if (env != NULL) {
delay = simple_strtoul(env, NULL, 10);
if (delay > 5)
printf("Warning, expect noticable delay before "
printf("Warning, expect noticable delay before "
"PCIe scan due to 'pciscandelay' value!\n");
mdelay(delay * 1000);
}
/*
* Config access can only go down stream
*/
hose->last_busno = pci_hose_scan(hose);
bus = hose->last_busno + 1;
/*
* Config access can only go down stream
*/
hose->last_busno = pci_hose_scan(hose);
bus = hose->last_busno + 1;
}
}
}

2
board/amcc/kilauea/Makefile
View File

@ -28,7 +28,7 @@ LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o cmd_pll.o memory.o
SOBJS = init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
$(LIB): $(obj).depend $(OBJS)

6
board/amcc/kilauea/init.S
View File

@ -29,10 +29,10 @@
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#define mtsdram_as(reg, value) \
addi r4,0,reg ; \
#define mtsdram_as(reg, value) \
addi r4,0,reg ; \
mtdcr memcfga,r4 ; \
addis r4,0,value@h ; \
addis r4,0,value@h ; \
ori r4,r4,value@l ; \
mtdcr memcfgd,r4 ;

22
board/amcc/kilauea/kilauea.c
View File

@ -338,27 +338,27 @@ void pcie_setup_hoses(int busno)
pci_register_hose(hose);
if (is_end_point(i)) {
ppc4xx_setup_pcie_endpoint(hose, i);
ppc4xx_setup_pcie_endpoint(hose, i);
/*
* Reson for no scanning is endpoint can not generate
* upstream configuration accesses.
*/
*/
} else {
ppc4xx_setup_pcie_rootpoint(hose, i);
ppc4xx_setup_pcie_rootpoint(hose, i);
env = getenv ("pciscandelay");
if (env != NULL) {
delay = simple_strtoul(env, NULL, 10);
if (env != NULL) {
delay = simple_strtoul(env, NULL, 10);
if (delay > 5)
printf("Warning, expect noticable delay before "
printf("Warning, expect noticable delay before "
"PCIe scan due to 'pciscandelay' value!\n");
mdelay(delay * 1000);
}
/*
* Config access can only go down stream
*/
hose->last_busno = pci_hose_scan(hose);
bus = hose->last_busno + 1;
/*
* Config access can only go down stream
*/
hose->last_busno = pci_hose_scan(hose);
bus = hose->last_busno + 1;
}
}
}

8
board/amcc/kilauea/u-boot-nand.lds
View File

@ -31,11 +31,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
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.rel.ctors : { *(.rel.ctors) }

8
board/amcc/kilauea/u-boot.lds
View File

@ -42,11 +42,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
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.rel.ctors : { *(.rel.ctors) }

8
board/amcc/luan/u-boot.lds
View File

@ -43,11 +43,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
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2
board/amcc/makalu/Makefile
View File

@ -28,7 +28,7 @@ LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o cmd_pll.o memory.o
SOBJS = init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
$(LIB): $(obj).depend $(OBJS)

6
board/amcc/makalu/init.S
View File

@ -29,10 +29,10 @@
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#define mtsdram_as(reg, value) \
addi r4,0,reg ; \
#define mtsdram_as(reg, value) \
addi r4,0,reg ; \
mtdcr memcfga,r4 ; \
addis r4,0,value@h ; \
addis r4,0,value@h ; \
ori r4,r4,value@l ; \
mtdcr memcfgd,r4 ;

22
board/amcc/makalu/makalu.c
View File

@ -294,27 +294,27 @@ void pcie_setup_hoses(int busno)
pci_register_hose(hose);
if (is_end_point(i)) {
ppc4xx_setup_pcie_endpoint(hose, i);
ppc4xx_setup_pcie_endpoint(hose, i);
/*
* Reson for no scanning is endpoint can not generate
* upstream configuration accesses.
*/
*/
} else {
ppc4xx_setup_pcie_rootpoint(hose, i);
ppc4xx_setup_pcie_rootpoint(hose, i);
env = getenv ("pciscandelay");
if (env != NULL) {
delay = simple_strtoul(env, NULL, 10);
if (env != NULL) {
delay = simple_strtoul(env, NULL, 10);
if (delay > 5)
printf("Warning, expect noticable delay before "
printf("Warning, expect noticable delay before "
"PCIe scan due to 'pciscandelay' value!\n");
mdelay(delay * 1000);
}
/*
* Config access can only go down stream
*/
hose->last_busno = pci_hose_scan(hose);
bus = hose->last_busno + 1;
/*
* Config access can only go down stream
*/
hose->last_busno = pci_hose_scan(hose);
bus = hose->last_busno + 1;
}
}
}

8
board/amcc/makalu/u-boot.lds
View File

@ -42,11 +42,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
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.rel.ctors : { *(.rel.ctors) }

8
board/amcc/ocotea/u-boot.lds
View File

@ -43,11 +43,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
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.rel.ctors : { *(.rel.ctors) }

8
board/amcc/sequoia/u-boot-nand.lds
View File

@ -31,11 +31,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
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.rel.ctors : { *(.rel.ctors) }

8
board/amcc/sequoia/u-boot.lds
View File

@ -43,11 +43,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
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.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }

8
board/amcc/taihu/u-boot.lds
View File

@ -38,11 +38,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
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.rel.ctors : { *(.rel.ctors) }

8
board/amcc/taishan/u-boot.lds
View File

@ -43,11 +43,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
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8
board/amcc/walnut/u-boot.lds
View File

@ -38,11 +38,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
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8
board/amcc/yosemite/u-boot.lds
View File

@ -43,11 +43,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
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.rel.ctors : { *(.rel.ctors) }

30
board/amcc/yucca/yucca.c
View File

@ -737,27 +737,27 @@ void yucca_setup_pcie_fpga_rootpoint(int port)
case 0:
rootpoint = FPGA_REG1C_PE0_ROOTPOINT;
endpoint = 0;
power = FPGA_REG1A_PE0_PWRON;
power = FPGA_REG1A_PE0_PWRON;
green_led = FPGA_REG1A_PE0_GLED;
clock = FPGA_REG1A_PE0_REFCLK_ENABLE;
clock = FPGA_REG1A_PE0_REFCLK_ENABLE;
yellow_led = FPGA_REG1A_PE0_YLED;
reset_off = FPGA_REG1C_PE0_PERST;
break;
case 1:
rootpoint = 0;
endpoint = FPGA_REG1C_PE1_ENDPOINT;
power = FPGA_REG1A_PE1_PWRON;
power = FPGA_REG1A_PE1_PWRON;
green_led = FPGA_REG1A_PE1_GLED;
clock = FPGA_REG1A_PE1_REFCLK_ENABLE;
clock = FPGA_REG1A_PE1_REFCLK_ENABLE;
yellow_led = FPGA_REG1A_PE1_YLED;
reset_off = FPGA_REG1C_PE1_PERST;
break;
case 2:
rootpoint = 0;
endpoint = FPGA_REG1C_PE2_ENDPOINT;
power = FPGA_REG1A_PE2_PWRON;
power = FPGA_REG1A_PE2_PWRON;
green_led = FPGA_REG1A_PE2_GLED;
clock = FPGA_REG1A_PE2_REFCLK_ENABLE;
clock = FPGA_REG1A_PE2_REFCLK_ENABLE;
yellow_led = FPGA_REG1A_PE2_YLED;
reset_off = FPGA_REG1C_PE2_PERST;
break;
@ -794,27 +794,27 @@ void yucca_setup_pcie_fpga_endpoint(int port)
case 0:
rootpoint = FPGA_REG1C_PE0_ROOTPOINT;
endpoint = 0;
power = FPGA_REG1A_PE0_PWRON;
power = FPGA_REG1A_PE0_PWRON;
green_led = FPGA_REG1A_PE0_GLED;
clock = FPGA_REG1A_PE0_REFCLK_ENABLE;
clock = FPGA_REG1A_PE0_REFCLK_ENABLE;
yellow_led = FPGA_REG1A_PE0_YLED;
reset_off = FPGA_REG1C_PE0_PERST;
break;
case 1:
rootpoint = 0;
endpoint = FPGA_REG1C_PE1_ENDPOINT;
power = FPGA_REG1A_PE1_PWRON;
power = FPGA_REG1A_PE1_PWRON;
green_led = FPGA_REG1A_PE1_GLED;
clock = FPGA_REG1A_PE1_REFCLK_ENABLE;
clock = FPGA_REG1A_PE1_REFCLK_ENABLE;
yellow_led = FPGA_REG1A_PE1_YLED;
reset_off = FPGA_REG1C_PE1_PERST;
break;
case 2:
rootpoint = 0;
endpoint = FPGA_REG1C_PE2_ENDPOINT;
power = FPGA_REG1A_PE2_PWRON;
power = FPGA_REG1A_PE2_PWRON;
green_led = FPGA_REG1A_PE2_GLED;
clock = FPGA_REG1A_PE2_REFCLK_ENABLE;
clock = FPGA_REG1A_PE2_REFCLK_ENABLE;
yellow_led = FPGA_REG1A_PE2_YLED;
reset_off = FPGA_REG1C_PE2_PERST;
break;
@ -884,21 +884,21 @@ void pcie_setup_hoses(int busno)
/*
* Reson for no scanning is endpoint can not generate
* upstream configuration accesses.
*/
*/
} else {
ppc4xx_setup_pcie_rootpoint(hose, i);
env = getenv("pciscandelay");
if (env != NULL) {
delay = simple_strtoul(env, NULL, 10);
if (delay > 5)
printf("Warning, expect noticable delay before "
printf("Warning, expect noticable delay before "
"PCIe scan due to 'pciscandelay' value!\n");
mdelay(delay * 1000);
}
/*
* Config access can only go down stream
*/
*/
hose->last_busno = pci_hose_scan(hose);
bus = hose->last_busno + 1;
}

8
board/amirix/ap1000/u-boot.lds
View File

@ -33,11 +33,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
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.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }

2
board/apollon/apollon.c
View File

@ -140,7 +140,7 @@ void wait_for_command_complete(unsigned int wd_base)
/*******************************************************************
* Routine:ether_init
* Description: take the Ethernet controller out of reset and wait
* for the EEPROM load to complete.
* for the EEPROM load to complete.
******************************************************************/
void ether_init(void)
{

4
board/armadillo/lowlevel_init.S
View File

@ -29,8 +29,8 @@
/* some parameters for the board */
/* setting up the memory */
#define SRAM_START 0x60000000
#define SRAM_SIZE 0x0000c000
#define SRAM_START 0x60000000
#define SRAM_SIZE 0x0000c000
.globl lowlevel_init
lowlevel_init:

2
board/assabet/assabet.c
View File

@ -46,7 +46,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define ECSR_PWRDWN 0x04
#define ECSR_INT 0x02
#define SMC_IO_SHIFT 2
#define NCR_0 (*((volatile u_char *)(0x100000a0)))
#define NCR_0 (*((volatile u_char *)(0x100000a0)))
#define NCR_ENET_OSC_EN (1<<3)
static inline u8

2
board/atmel/at91sam9260ek/at91sam9260ek.c
View File

@ -126,7 +126,7 @@ static void at91sam9260ek_macb_hw_init(void)
/*
* Disable pull-up on:
* RXDV (PA17) => PHY normal mode (not Test mode)
* ERX0 (PA14) => PHY ADDR0
* ERX0 (PA14) => PHY ADDR0
* ERX1 (PA15) => PHY ADDR1
* ERX2 (PA25) => PHY ADDR2
* ERX3 (PA26) => PHY ADDR3

8
board/atum8548/u-boot.lds
View File

@ -42,11 +42,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
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.rel.ctors : { *(.rel.ctors) }

4
board/barco/speed.h
View File

@ -52,10 +52,10 @@
* SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1
*
* SPEED_FCOUNT2 timer 2 counting frequency
* GCLK CPU clock
* GCLK CPU clock
* SPEED_TMR2_PS prescaler
*/
#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */
#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */
/*-----------------------------------------------------------------------
* Timer value for PIT

2
board/bc3450/cmd_bc3450.c
View File

@ -69,7 +69,7 @@ struct therm {
#define SM501_POWER_MODE0_GATE 0x00000040UL
#define SM501_POWER_MODE1_GATE 0x00000048UL
#define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL
#define SM501_GPIO_DATA_LOW 0x00010000UL
#define SM501_GPIO_DATA_LOW 0x00010000UL
#define SM501_GPIO_DATA_HIGH 0x00010004UL
#define SM501_GPIO_DATA_DIR_LOW 0x00010008UL
#define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL

8
board/bf533-ezkit/flash-defines.h
View File

@ -44,11 +44,11 @@
#define ERASE_SECT 6
#define READ 7
#define GET_SECTNUM 8
#define FLASH_START_L 0x0000
#define FLASH_START_H 0x2000
#define FLASH_START_L 0x0000
#define FLASH_START_H 0x2000
#define FLASH_TOT_SECT 40
#define FLASH_SIZE 0x220000
#define FLASH_MAN_ST 2
#define FLASH_SIZE 0x220000
#define FLASH_MAN_ST 2
#define CFG_FLASH0_BASE 0x20000000
#define RESET_VAL 0xF0

10
board/bf533-stamp/bf533-stamp.h
View File

@ -38,13 +38,13 @@ extern unsigned long pll_div_fact;
extern void serial_setbrg(void);
/* Definitions used in Compact Flash Boot support */
#define FIO_EDGE_CF_BITS 0x0000
#define FIO_POLAR_CF_BITS 0x0000
#define FIO_EDGE_BITS 0x1E0
#define FIO_POLAR_BITS 0x160
#define FIO_EDGE_CF_BITS 0x0000
#define FIO_POLAR_CF_BITS 0x0000
#define FIO_EDGE_BITS 0x1E0
#define FIO_POLAR_BITS 0x160
/* Compact flash status bits in status register */
#define CF_STAT_BITS 0x00000060
#define CF_STAT_BITS 0x00000060
/* CF Flags used to switch between expansion and external
* memory banks

2
board/bmw/README
View File

@ -89,7 +89,7 @@ Interrupt Mappings
BMW uses MPC8245 discrete mode interrupts. With the following
hardwired mappings:
BCM5701 10/100/1000 Ethernet IRQ1
BCM5701 10/100/1000 Ethernet IRQ1
CompactPCI Interrupt A IRQ2
RTC/Watchdog Interrupt IRQ3
Internal NS16552 UART IRQ4

6
board/bmw/early_init.S
View File

@ -246,7 +246,7 @@ early_init_f:
#if 1 /* Turn off floating point (remove to keep FP on) */
andi. r3, r3, 0
sync
mtmsr r3
mtmsr r3
isync
#endif
@ -1137,7 +1137,7 @@ early_init_f:
/* delay */
lis r7, 1
mtctr r7
label1: bdnz label1
label1: bdnz label1
/* Set memgo bit */
/* MCCR1 */
@ -1151,7 +1151,7 @@ label1: bdnz label1
/* delay again */
lis r7, 1
mtctr r7
label2: bdnz label2
label2: bdnz label2
#if 0
/* DEBUG: Infinite loop, write then read */
loop:

4
board/c2mon/pcmcia.c
View File

@ -235,14 +235,14 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp)
sreg |= TPS2211_VPPD0 | TPS2211_VPPD1; /* VAVPP always Hi-Z */
switch(vcc) {
case 0: break; /* Switch off */
case 0: break; /* Switch off */
case 33: sreg |= TPS2211_VCCD0; /* Switch on 3.3V */
sreg &= ~TPS2211_VCCD1;
break;
case 50: sreg &= ~TPS2211_VCCD0; /* Switch on 5.0V */
sreg |= TPS2211_VCCD1;
break;
default: goto done;
default: goto done;
}
/* Checking supported voltages */

8
board/c2mon/u-boot.lds
View File

@ -33,11 +33,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
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8
board/c2mon/u-boot.lds.debug
View File

@ -33,11 +33,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
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.rel.ctors : { *(.rel.ctors) }

260
board/cerf250/lowlevel_init.S
View File

@ -40,7 +40,7 @@ DRAM_SIZE: .long CFG_DRAM_SIZE
/*
* Memory setup
* Memory setup
*/
.globl lowlevel_init
@ -48,69 +48,69 @@ lowlevel_init:
/* Set up GPIO pins first ----------------------------------------- */
ldr r0, =GPSR0
ldr r1, =CFG_GPSR0_VAL
str r1, [r0]
ldr r0, =GPSR0
ldr r1, =CFG_GPSR0_VAL
str r1, [r0]
ldr r0, =GPSR1
ldr r1, =CFG_GPSR1_VAL
str r1, [r0]
ldr r0, =GPSR1
ldr r1, =CFG_GPSR1_VAL
str r1, [r0]
ldr r0, =GPSR2
ldr r1, =CFG_GPSR2_VAL
str r1, [r0]
ldr r0, =GPSR2
ldr r1, =CFG_GPSR2_VAL
str r1, [r0]
ldr r0, =GPCR0
ldr r1, =CFG_GPCR0_VAL
str r1, [r0]
ldr r0, =GPCR0
ldr r1, =CFG_GPCR0_VAL
str r1, [r0]
ldr r0, =GPCR1
ldr r1, =CFG_GPCR1_VAL
str r1, [r0]
ldr r0, =GPCR1
ldr r1, =CFG_GPCR1_VAL
str r1, [r0]
ldr r0, =GPCR2
ldr r1, =CFG_GPCR2_VAL
str r1, [r0]
ldr r0, =GPCR2
ldr r1, =CFG_GPCR2_VAL
str r1, [r0]
ldr r0, =GPDR0
ldr r1, =CFG_GPDR0_VAL
str r1, [r0]
ldr r0, =GPDR0
ldr r1, =CFG_GPDR0_VAL
str r1, [r0]
ldr r0, =GPDR1
ldr r1, =CFG_GPDR1_VAL
str r1, [r0]
ldr r0, =GPDR1
ldr r1, =CFG_GPDR1_VAL
str r1, [r0]
ldr r0, =GPDR2
ldr r1, =CFG_GPDR2_VAL
str r1, [r0]
ldr r0, =GPDR2
ldr r1, =CFG_GPDR2_VAL
str r1, [r0]
ldr r0, =GAFR0_L
ldr r1, =CFG_GAFR0_L_VAL
str r1, [r0]
ldr r0, =GAFR0_L
ldr r1, =CFG_GAFR0_L_VAL
str r1, [r0]
ldr r0, =GAFR0_U
ldr r1, =CFG_GAFR0_U_VAL
str r1, [r0]
ldr r0, =GAFR0_U
ldr r1, =CFG_GAFR0_U_VAL
str r1, [r0]
ldr r0, =GAFR1_L
ldr r1, =CFG_GAFR1_L_VAL
str r1, [r0]
ldr r0, =GAFR1_L
ldr r1, =CFG_GAFR1_L_VAL
str r1, [r0]
ldr r0, =GAFR1_U
ldr r1, =CFG_GAFR1_U_VAL
str r1, [r0]
ldr r0, =GAFR1_U
ldr r1, =CFG_GAFR1_U_VAL
str r1, [r0]
ldr r0, =GAFR2_L
ldr r1, =CFG_GAFR2_L_VAL
str r1, [r0]
ldr r0, =GAFR2_L
ldr r1, =CFG_GAFR2_L_VAL
str r1, [r0]
ldr r0, =GAFR2_U
ldr r1, =CFG_GAFR2_U_VAL
str r1, [r0]
ldr r0, =GAFR2_U
ldr r1, =CFG_GAFR2_U_VAL
str r1, [r0]
ldr r0, =PSSR /* enable GPIO pins */
ldr r1, =CFG_PSSR_VAL
str r1, [r0]
ldr r0, =PSSR /* enable GPIO pins */
ldr r1, =CFG_PSSR_VAL
str r1, [r0]
/* ---------------------------------------------------------------- */
/* Enable memory interface */
@ -126,19 +126,19 @@ lowlevel_init:
/* FIXME: can be optimized later */
/* ---------------------------------------------------------------- */
ldr r3, =OSCR /* reset the OS Timer Count to zero */
mov r2, #0
str r2, [r3]
ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
/* so 0x300 should be plenty */
ldr r3, =OSCR /* reset the OS Timer Count to zero */
mov r2, #0
str r2, [r3]
ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
/* so 0x300 should be plenty */
1:
ldr r2, [r3]
cmp r4, r2
bgt 1b
ldr r2, [r3]
cmp r4, r2
bgt 1b
mem_init:
ldr r1, =MEMC_BASE /* get memory controller base addr. */
ldr r1, =MEMC_BASE /* get memory controller base addr. */
/* ---------------------------------------------------------------- */
/* Step 2a: Initialize Asynchronous static memory controller */
@ -147,58 +147,58 @@ mem_init:
/* MSC registers: timing, bus width, mem type */
/* MSC0: nCS(0,1) */
ldr r2, =CFG_MSC0_VAL
str r2, [r1, #MSC0_OFFSET]
ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
ldr r2, =CFG_MSC0_VAL
str r2, [r1, #MSC0_OFFSET]
ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
/* that data latches */
/* MSC1: nCS(2,3) */
ldr r2, =CFG_MSC1_VAL
str r2, [r1, #MSC1_OFFSET]
ldr r2, [r1, #MSC1_OFFSET]
ldr r2, =CFG_MSC1_VAL
str r2, [r1, #MSC1_OFFSET]
ldr r2, [r1, #MSC1_OFFSET]
/* MSC2: nCS(4,5) */
ldr r2, =CFG_MSC2_VAL
str r2, [r1, #MSC2_OFFSET]
ldr r2, [r1, #MSC2_OFFSET]
ldr r2, =CFG_MSC2_VAL
str r2, [r1, #MSC2_OFFSET]
ldr r2, [r1, #MSC2_OFFSET]
/* ---------------------------------------------------------------- */
/* Step 2b: Initialize Card Interface */
/* ---------------------------------------------------------------- */
/* MECR: Memory Expansion Card Register */
ldr r2, =CFG_MECR_VAL
str r2, [r1, #MECR_OFFSET]
ldr r2, [r1, #MECR_OFFSET]
ldr r2, =CFG_MECR_VAL
str r2, [r1, #MECR_OFFSET]
ldr r2, [r1, #MECR_OFFSET]
/* MCMEM0: Card Interface slot 0 timing */
ldr r2, =CFG_MCMEM0_VAL
str r2, [r1, #MCMEM0_OFFSET]
ldr r2, [r1, #MCMEM0_OFFSET]
ldr r2, =CFG_MCMEM0_VAL
str r2, [r1, #MCMEM0_OFFSET]
ldr r2, [r1, #MCMEM0_OFFSET]
/* MCMEM1: Card Interface slot 1 timing */
ldr r2, =CFG_MCMEM1_VAL
str r2, [r1, #MCMEM1_OFFSET]
ldr r2, [r1, #MCMEM1_OFFSET]
ldr r2, =CFG_MCMEM1_VAL
str r2, [r1, #MCMEM1_OFFSET]
ldr r2, [r1, #MCMEM1_OFFSET]
/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
ldr r2, =CFG_MCATT0_VAL
str r2, [r1, #MCATT0_OFFSET]
ldr r2, [r1, #MCATT0_OFFSET]
ldr r2, =CFG_MCATT0_VAL
str r2, [r1, #MCATT0_OFFSET]
ldr r2, [r1, #MCATT0_OFFSET]
/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
ldr r2, =CFG_MCATT1_VAL
str r2, [r1, #MCATT1_OFFSET]
ldr r2, [r1, #MCATT1_OFFSET]
ldr r2, =CFG_MCATT1_VAL
str r2, [r1, #MCATT1_OFFSET]
ldr r2, [r1, #MCATT1_OFFSET]
/* MCIO0: Card Interface I/O Space Timing, slot 0 */
ldr r2, =CFG_MCIO0_VAL
str r2, [r1, #MCIO0_OFFSET]
ldr r2, [r1, #MCIO0_OFFSET]
ldr r2, =CFG_MCIO0_VAL
str r2, [r1, #MCIO0_OFFSET]
ldr r2, [r1, #MCIO0_OFFSET]
/* MCIO1: Card Interface I/O Space Timing, slot 1 */
ldr r2, =CFG_MCIO1_VAL
str r2, [r1, #MCIO1_OFFSET]
ldr r2, [r1, #MCIO1_OFFSET]
ldr r2, =CFG_MCIO1_VAL
str r2, [r1, #MCIO1_OFFSET]
ldr r2, [r1, #MCIO1_OFFSET]
/* ---------------------------------------------------------------- */
/* Step 2c: Write FLYCNFG FIXME: what's that??? */
@ -212,16 +212,16 @@ mem_init:
/* Before accessing MDREFR we need a valid DRI field, so we set */
/* this to power on defaults + DRI field, set SDRAM clocks free running */
ldr r3, =CFG_MDREFR_VAL
ldr r2, =0xFFF
and r3, r3, r2
ldr r3, =CFG_MDREFR_VAL
ldr r2, =0xFFF
and r3, r3, r2
ldr r0, [r1, #MDREFR_OFFSET]
bic r0, r0, r2
bic r0, r0, #(MDREFR_K0FREE|MDREFR_K1FREE|MDREFR_K2FREE)
orr r0, r0, r3
ldr r0, [r1, #MDREFR_OFFSET]
bic r0, r0, r2
bic r0, r0, #(MDREFR_K0FREE|MDREFR_K1FREE|MDREFR_K2FREE)
orr r0, r0, r3
str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */
str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */
/* ---------------------------------------------------------------- */
@ -244,18 +244,18 @@ mem_init:
/* set MDREFR according to user define with exception of a few bits */
ldr r4, =CFG_MDREFR_VAL
ldr r2, =(MDREFR_K0RUN|MDREFR_K0DB2|MDREFR_K1RUN|MDREFR_K1DB2|\
ldr r2, =(MDREFR_K0RUN|MDREFR_K0DB2|MDREFR_K1RUN|MDREFR_K1DB2|\
MDREFR_K2RUN |MDREFR_K2DB2)
and r4, r4, r2
bic r0, r0, r2
orr r0, r0, r4
and r4, r4, r2
bic r0, r0, r2
orr r0, r0, r4
str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */
ldr r0, [r1, #MDREFR_OFFSET]
/* Step 4b: de-assert MDREFR:SLFRSH. */
bic r0, r0, #(MDREFR_SLFRSH)
bic r0, r0, #(MDREFR_SLFRSH)
str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */
ldr r0, [r1, #MDREFR_OFFSET]
@ -263,10 +263,10 @@ mem_init:
/* Step 4c: assert MDREFR:E1PIN and E0PIO as desired, set KXFREE */
ldr r4, =CFG_MDREFR_VAL
ldr r2, =(MDREFR_E0PIN|MDREFR_E1PIN|MDREFR_K0FREE| \
MDREFR_K1FREE | MDREFR_K2FREE)
and r4, r4, r2
orr r0, r0, r4
ldr r2, =(MDREFR_E0PIN|MDREFR_E1PIN|MDREFR_K0FREE| \
MDREFR_K1FREE | MDREFR_K2FREE)
and r4, r4, r2
orr r0, r0, r4
str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */
ldr r0, [r1, #MDREFR_OFFSET]
@ -274,9 +274,9 @@ mem_init:
/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
/* configure but not enable each SDRAM partition pair. */
ldr r4, =CFG_MDCNFG_VAL
bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
ldr r4, =CFG_MDCNFG_VAL
bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
ldr r4, [r1, #MDCNFG_OFFSET]
@ -284,15 +284,15 @@ mem_init:
/* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
/* 100..200 µsec. */
ldr r3, =OSCR /* reset the OS Timer Count to zero */
mov r2, #0
str r2, [r3]
ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
ldr r3, =OSCR /* reset the OS Timer Count to zero */
mov r2, #0
str r2, [r3]
ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
/* so 0x300 should be plenty */
1:
ldr r2, [r3]
cmp r4, r2
bgt 1b
ldr r2, [r3]
cmp r4, r2
bgt 1b
/* Step 4f: Trigger a number (usually 8) refresh cycles by */
@ -301,16 +301,16 @@ mem_init:
/* documented in SDRAM data sheets. The address(es) used */
/* for this purpose must not be cacheable. */
ldr r3, =CFG_DRAM_BASE
ldr r3, =CFG_DRAM_BASE
.rept 8
str r2, [r3]
str r2, [r3]
.endr
/* Step 4g: Write MDCNFG with enable bits asserted */
/* (MDCNFG:DEx set to 1). */
ldr r3, [r1, #MDCNFG_OFFSET]
orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
str r3, [r1, #MDCNFG_OFFSET]
/* Step 4h: Write MDMRS. */
@ -378,27 +378,27 @@ initclks:
/* ---------------------------------------------------------------- */
/* Save SDRAM size */
ldr r1, =DRAM_SIZE
str r8, [r1]
ldr r1, =DRAM_SIZE
str r8, [r1]
/* Interrupt init: Mask all interrupts */
ldr r0, =ICMR /* enable no sources */
mov r1, #0
str r1, [r0]
ldr r0, =ICMR /* enable no sources */
mov r1, #0
str r1, [r0]
/* FIXME */
#define NODEBUG
#ifdef NODEBUG
/*Disable software and data breakpoints */
mov r0,#0
mcr p15,0,r0,c14,c8,0 /* ibcr0 */
mcr p15,0,r0,c14,c9,0 /* ibcr1 */
mcr p15,0,r0,c14,c4,0 /* dbcon */
mov r0,#0
mcr p15,0,r0,c14,c8,0 /* ibcr0 */
mcr p15,0,r0,c14,c9,0 /* ibcr1 */
mcr p15,0,r0,c14,c4,0 /* dbcon */
/*Enable all debug functionality */
mov r0,#0x80000000
mcr p14,0,r0,c10,c0,0 /* dcsr */
mov r0,#0x80000000
mcr p14,0,r0,c10,c0,0 /* dcsr */
#endif
@ -408,4 +408,4 @@ initclks:
endlowlevel_init:
mov pc, lr
mov pc, lr

8
board/cm5200/u-boot.lds
View File

@ -31,11 +31,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }

2
board/cmc_pu2/cmc_pu2.c
View File

@ -73,7 +73,7 @@ int board_init (void)
pioc->PIO_PPUDR = AT91C_PIO_PC0 | AT91C_PIO_PC1 |
AT91C_PIO_PC2 | AT91C_PIO_PC3;
pioc->PIO_PER = AT91C_PIO_PC0 | AT91C_PIO_PC1 |
AT91C_PIO_PC2 | AT91C_PIO_PC3;
AT91C_PIO_PC2 | AT91C_PIO_PC3;
/*
* On CMC-PU2 board configure PB3-PB6 to input without pull ups to

8
board/cmi/flash.c
View File

@ -25,7 +25,7 @@
* File: flash.c
*
* Discription: This Driver is for 28F320J3A, 28F640J3A and
* 28F128J3A Intel flashs working in 16 Bit mode.
* 28F128J3A Intel flashs working in 16 Bit mode.
* They are single bank flashs.
*
* Most of this code is taken from existing u-boot
@ -67,9 +67,9 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
/*
* Local function prototypes
*/
static ulong flash_get_size (vu_short *addr, flash_info_t *info);
static int write_short (flash_info_t *info, ulong dest, ushort data);
static void flash_get_offsets (ulong base, flash_info_t *info);
static ulong flash_get_size (vu_short *addr, flash_info_t *info);
static int write_short (flash_info_t *info, ulong dest, ushort data);
static void flash_get_offsets (ulong base, flash_info_t *info);
/*
* Initialize flash

8
board/cobra5272/u-boot.lds
View File

@ -33,11 +33,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
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.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }

2
board/cogent/lcd.h
View File

@ -70,7 +70,7 @@
/* LCD status values */
#define LCD_OK 0x00
#define LCD_ERR 0x01
#define LCD_ERR 0x01
#define LCD_LINE0 0x00
#define LCD_LINE1 0x40

8
board/cogent/u-boot.lds
View File

@ -33,11 +33,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
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.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }

8
board/cogent/u-boot.lds.debug
View File

@ -33,11 +33,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rela.text : { *(.rela.text) }
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.rela.data : { *(.rela.data) }
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.rela.rodata : { *(.rela.rodata) }
.rela.data : { *(.rela.data) }
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.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }

6
board/cpc45/plx9030.c
View File

@ -54,7 +54,7 @@ registers (CS3) on CPC45.
/* PLX9030 register offsets */
#define P9030_LAS0RR 0x00
#define P9030_LAS1RR 0x04
#define P9030_LAS1RR 0x04
#define P9030_LAS2RR 0x08
#define P9030_LAS3RR 0x0c
#define P9030_EROMRR 0x10
@ -72,8 +72,8 @@ registers (CS3) on CPC45.
#define P9030_CS1BASE 0x40
#define P9030_CS2BASE 0x44
#define P9030_CS3BASE 0x48
#define P9030_INTCSR 0x4c
#define P9030_CNTRL 0x50
#define P9030_INTCSR 0x4c
#define P9030_CNTRL 0x50
#define P9030_GPIOC 0x54
/* typedefs */

4
board/cray/L1/L1.h
View File

@ -26,7 +26,7 @@
*
* Start Address Length
* +++++++++++++++++++++++++ 0xFFC0_0000 Start of Flash -----------------
* | Failsafe Linux Image | (1M)
* | Failsafe Linux Image | (1M)
* +=======================+ 0xFFD0_0000
* | (Reserved FlashFiles) | (1M)
* +=======================+ 0xFFE0_0000
@ -36,7 +36,7 @@
* | U N U S E D |
* | |
* +-----------------------+ 0xFFFD_0000 U-Boot image header (64 bytes)
* | environment settings | (64k)
* | environment settings | (64k)
* +-----------------------+ 0xFFFE_0000 U-Boot image header (64 bytes)
* | U-Boot | 0xFFFE_0040 _start of U-Boot
* | | 0xFFFE_FFFC reset vector - branch to _start

8
board/cray/L1/u-boot.lds
View File

@ -39,11 +39,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rela.text : { *(.rela.text) }
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.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }

8
board/cray/L1/u-boot.lds.debug
View File

@ -33,11 +33,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rela.text : { *(.rela.text) }
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.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }

8
board/csb226/lowlevel_init.S
View File

@ -43,7 +43,7 @@ _TEXT_BASE:
/*
* Memory setup
* Memory setup
*/
.globl lowlevel_init
@ -129,8 +129,8 @@ lowlevel_init:
/*loop: */
/* */
/* ldr r0, =0xB0070001 */
/* ldr r1, =_LED */
/* str r0, [r1] / hex display */
/* ldr r1, =_LED */
/* str r0, [r1] / hex display */
/* ---------------------------------------------------------------- */
@ -239,7 +239,7 @@ mem_init:
/* Before accessing MDREFR we need a valid DRI field, so we set */
/* this to power on defaults + DRI field. */
ldr r3, =CFG_MDREFR_VAL
ldr r3, =CFG_MDREFR_VAL
ldr r2, =0xFFF
and r3, r3, r2
ldr r4, =0x03ca4000

8
board/csb272/u-boot.lds
View File

@ -38,11 +38,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }

8
board/csb472/u-boot.lds
View File

@ -38,11 +38,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }

8
board/dave/B2/B2.c
View File

@ -78,16 +78,16 @@ int board_init (void)
INTCON = 0x05;
/*
Configure chip ethernet interrupt as High level
Port G EINT 0-7 EINT0 -> CHIP ETHERNET
Configure chip ethernet interrupt as High level
Port G EINT 0-7 EINT0 -> CHIP ETHERNET
*/
temp = EXTINT;
temp &= ~0x7;
temp &= ~0x7;
temp |= 0x1; /*LEVEL_HIGH*/
EXTINT = temp;
/*
Reset SMSC LAN91C96 chip
Reset SMSC LAN91C96 chip
*/
temp= PCONF;
temp |= 0x00000040;

8
board/dave/PPChameleonEVB/u-boot.lds
View File

@ -38,11 +38,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }

2
board/davinci/dv-evm/dv_board.c
View File

@ -73,7 +73,7 @@ void lpsc_on(unsigned int id)
(id == DAVINCI_LPSC_McBSP) ||
(id == DAVINCI_LPSC_GPIO)
)
*mdctl |= 0x200;
*mdctl |= 0x200;
REG(PSC_PTCMD) = 0x01;

2
board/davinci/schmoogie/dv_board.c
View File

@ -73,7 +73,7 @@ void lpsc_on(unsigned int id)
(id == DAVINCI_LPSC_McBSP) ||
(id == DAVINCI_LPSC_GPIO)
)
*mdctl |= 0x200;
*mdctl |= 0x200;
REG(PSC_PTCMD) = 0x01;

2
board/davinci/sonata/dv_board.c
View File

@ -73,7 +73,7 @@ void lpsc_on(unsigned int id)
(id == DAVINCI_LPSC_McBSP) ||
(id == DAVINCI_LPSC_GPIO)
)
*mdctl |= 0x200;
*mdctl |= 0x200;
REG(PSC_PTCMD) = 0x01;

8
board/eltec/bab7xx/u-boot.lds
View File

@ -37,11 +37,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }

8
board/eltec/elppc/u-boot.lds
View File

@ -37,11 +37,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }

8
board/eltec/mhpc/u-boot.lds
View File

@ -33,11 +33,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }

Some files were not shown because too many files have changed in this diff Show More