This patch adds gpio support of Altera PIO component to the
nios2-generic board. Though it drives only gpio_led at the
moment, it supports bidirectional port to control bit-banging
I2C, NAND flash busy status or button switches, etc.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Tested-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
This patch sets the SICRL_LBC bits in SICRL to change the function of the
associated pins to GPIO functionality.
Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net>
Add USB commands.
Rename autoscript to bootscript.
Add automatic bootscript image generation to makefile.
Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Added UPM array table, upmconfig, and Local Bus configuration support for SIMPC8313
Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Add ECC support for DDR RAM for MV64360 on esd CPCI-CPU/750 board.
This patch also adds the "pldver" command to display the CPLD
revision.
Signed-off-by: Reinhard Arlt <reinhard.arlt@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
The RTC is part of the Freescale's PMIC controller.
Use general function to access to PMIC internal registers.
Signed-off-by: Stefano Babic <sbabic@denx.de>
Tested-by: Magnus Lilja <lilja.magnus@gmail.com>
The NAND device is connected to the FPGA of the QONG board
and not to the NFC controller. For this reason, the FPGA must
be set and initialized before accessing to the NAND itself.
Signed-off-by: Stefano Babic <sbabic@denx.de>
moved CONFIG_CMD_FAT to filesystem section
swapped CONFIG_CMD_NAND and CONFIG_CMD_MII so they are alpha correct
Signed-off-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com>
This patch includes a few additional commands in the sheevaplug
version of u-boot:
- support for LONGHELP so you can get help messages
- auto completion and command editing
- ubi and mii support
- ext2 filesystem (convenient if you have an ext2 from which you want to boot)
- jffs2 and ubifs filesystems (if you want to use these in NAND)
This also makes it more similar to openrd client.
Side effect of this patch is that the code now needs 3 sectors i.s.o. 2
so an existing env is overwritten
Signed-off-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com>
The lowlevel_init file contained some hard-coded values
to setup the RAM. These board related values are moved into
the board configuration file.
Signed-off-by: Stefano Babic <sbabic@denx.de>
This patch adds support for the magnesium board from
projectiondesign. This board uses i.MX27 SoC and has
8MB NOR flash, 128MB NAND flash, FEC ethernet controller
integrated into i.MX27. As this port is based on
the imx27lite port, common config options are collected
in include/configs/imx27lite-common.h
Signed-off-by: Heiko Schocher <hs@denx.de>
This patch fixes APC405 build, by defining CONFIG_PPC4XX_I2C. This is
needed since the move of the PPC4xx I2C driver into the drivers/i2c
directory.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Matthias Fuchs <matthias.fuchs@esd.eu>
This patch adds support for the Mosaix Technologies, Inc. ICON board,
based on the AppliedMicro (AMCC) PPC440SPe. It's equipped with an SODIMM
(512MB standard) and 64MByte of NOR FLASH.
Support for the onboard SM502 will be added later.
Signed-off-by: Stefan Roese <sr@denx.de>
This is a generic approach to port u-boot for nios2 boards.
You may find the usage of this approach on the nioswiki,
http://nioswiki.com/DasUBoot
A fpga parameter file, which contains base address information
and drivers declaration, is generated from Altera's hardware system
description sopc file using tools.
The example fpga parameter file is compatible with EP1C20, EP1S10
and EP1S40 boards. So these boards can be removed after this commit.
Though epcs controller is removed to cut the dependency of altera_spi
driver.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
PDM360NG is a MPC5121E based board by ifm ecomatic gmbh.
Signed-off-by: Michael Weiss <michael.weiss@ifm.com>
Signed-off-by: Detlev Zundel <dzu@denx.de>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Configure CONFIG_SYS_MAX_RAM_SIZE address range in
DDR Local Access Window and determine the RAM size.
Fix DDR LAW afterwards using detected RAM size.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
before, MPC8349ITX boots u-boot in 4.3sec:
column1 is elapsed time since first message
column2 is elapsed time since previous message
column3 is the message
0.000 0.000: U-Boot 2010.03-00126-gfd4e49c (Apr 11 2010 - 17:25:29) MPC83XX
0.000 0.000:
0.000 0.000: Reset Status:
0.000 0.000:
0.032 0.032: CPU: e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz
0.032 0.000: Board: Freescale MPC8349E-mITX
0.032 0.000: UPMA: Configured for compact flash
0.032 0.000: I2C: ready
0.061 0.028: DRAM: 256 MB (DDR1, 64-bit, ECC off, 266.667 MHz)
1.516 1.456: FLASH: 16 MB
2.641 1.125: PCI: Bus Dev VenId DevId Class Int
2.652 0.011: 00 10 1095 3114 0180 00
2.652 0.000: PCI: Bus Dev VenId DevId Class Int
2.652 0.000: In: serial
2.652 0.000: Out: serial
2.652 0.000: Err: serial
2.682 0.030: Board revision: 1.0 (PCF8475A)
3.080 0.398: Net: TSEC1: No support for PHY id ffffffff; assuming generic
3.080 0.000: TSEC0, TSEC1
4.300 1.219: IDE: Bus 0: .** Timeout **
after, MPC8349ITX boots u-boot in 3.0sec:
0.010 0.010: U-Boot 2010.03-00127-g4b468cc-dirty (Apr 11 2010 - 17:47:29) MPC83XX
0.010 0.000:
0.010 0.000: Reset Status:
0.010 0.000:
0.017 0.007: CPU: e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz
0.017 0.000: Board: Freescale MPC8349E-mITX
0.038 0.020: UPMA: Configured for compact flash
0.038 0.000: I2C: ready
0.038 0.000: DRAM: 256 MB (DDR1, 64-bit, ECC off, 266.667 MHz)
0.260 0.222: FLASH: 16 MB
1.390 1.130: PCI: Bus Dev VenId DevId Class Int
1.390 0.000: 00 10 1095 3114 0180 00
1.390 0.000: PCI: Bus Dev VenId DevId Class Int
1.400 0.010: In: serial
1.400 0.000: Out: serial
1.400 0.000: Err: serial
1.400 0.000: Board revision: 1.0 (PCF8475A)
1.832 0.432: Net: TSEC1: No support for PHY id ffffffff; assuming generic
1.832 0.000: TSEC0, TSEC1
3.038 1.205: IDE: Bus 0: .** Timeout **
also tested on these boards (albeit with a less accurate
boottime measurement method):
seconds: before after
8349MDS ~2.6 ~2.2
8360MDS ~2.8 ~2.6
8313RDB ~2.5 ~2.3 #nand boot
837xRDB ~3.1 ~2.3
also tested on an 8323ERDB.
v2: also remove the delayed icache enablement assumption in arch ppc's
board.c, and add a CONFIG_MPC83xx define in the ITX config file for
consistency (even though it was already being defined in 83xx'
config.mk).
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
As discussed on the list, move "arch/ppc" to "arch/powerpc" to
better match the Linux directory structure.
Please note that this patch also changes the "ppc" target in
MAKEALL to "powerpc" to match this new infrastructure. But "ppc"
is kept as an alias for now, to not break compatibility with
scripts using this name.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Anatolij Gustschin <agust@denx.de>
The 440SPe Rev. A is quite old and newer 440SPe boards don't need support
for this CPU revision. Since removing support for this older version
simplifies the creation for newer U-Boot ports, this patch now enables
440SPe > Rev. A support by creating the CONFIG_440SPE_REVA define. By
defining this in the board config header, Rev. A will still be supported.
Otherwise (default for newer board ports), Rev. A will not be supported.
Signed-off-by: Stefan Roese <sr@denx.de>
The latest changes increased the size of the alpr image a bit more.
Now it doesn't fit into the 256k reserved for it. This patch now removes
the commands "loads" and "loadb" which are not needed in the production
systems.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pieter Voorthuijsen <pieter.voorthuijsen@prodrive.nl>
Thomas Chou