NAND finally working. Two bugs fixed:
* For READ_STATUS and READID commands always 8 bytes need to be read from NDDB. Otherwise they stay there and get send to flash as the first data word when writing. * In nand_base.c the oob variable is not reset so this->oob_buf is overwritten what eventually screws up the bad block descriptor table.
This commit is contained in:
Markus Klotzbcher
Markus Klotzbcher
parent
bf7cac033b
commit
f9e029184b
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@ -31,8 +31,13 @@
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/* mk@tbd move this to pxa-regs */
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#define OSCR_CLK_FREQ 3.250 /* MHz */
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/* usefull */
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#define CFG_DFC_DEBUG1
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#define CFG_DFC_DEBUG2
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/* noisy */
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#undef CFG_DFC_DEBUG2
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/* wild west */
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#undef CFG_DFC_DEBUG3
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#ifdef CFG_DFC_DEBUG1
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# define DFC_DEBUG1(fmt, args...) printf(fmt, ##args)
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@ -46,6 +51,12 @@
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# define DFC_DEBUG2(fmt, args...)
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#endif
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#ifdef CFG_DFC_DEBUG3
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# define DFC_DEBUG3(fmt, args...) printf(fmt, ##args)
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#else
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# define DFC_DEBUG3(fmt, args...)
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#endif
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static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
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static struct nand_bbt_descr delta_bbt_descr = {
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@ -56,7 +67,7 @@ static struct nand_bbt_descr delta_bbt_descr = {
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};
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static struct nand_oobinfo delta_oob = {
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.useecc = MTD_NANDECC_AUTOPLACE,
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.useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */
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.eccbytes = 6,
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.eccpos = {2, 3, 4, 5, 6, 7},
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.oobfree = { {8, 2}, {12, 4} }
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@ -90,7 +101,8 @@ static void delta_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
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unsigned long rest = len & 0x3;
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unsigned long *long_buf;
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int i;
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DFC_DEBUG2("delta_write_buf: writing %d bytes starting with 0x%x.\n", len, *((unsigned long*) buf));
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if(bytes_multi) {
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for(i=0; i<bytes_multi; i+=4) {
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long_buf = (unsigned long*) &buf[i];
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@ -138,6 +150,7 @@ static void delta_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
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unsigned long rest = len & 0x3;
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unsigned long *long_buf;
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DFC_DEBUG3("delta_read_buf: reading %d bytes.\n", len);
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/* if there are any, first copy multiple of 4 bytes */
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if(bytes_multi) {
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for(i=0; i<bytes_multi; i+=4) {
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@ -167,6 +180,7 @@ static u16 delta_read_word(struct mtd_info *mtd)
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/* global var, too bad: mk@tbd: move to ->priv pointer */
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static unsigned long read_buf = 0;
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static int bytes_read = -1;
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static unsigned long last_cmd = 0;
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/* read a byte from NDDB Because we can only read 4 bytes from NDDB at
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* a time, we buffer the remaining bytes. The buffer is reset when a
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@ -176,16 +190,18 @@ static u_char delta_read_byte(struct mtd_info *mtd)
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{
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/* struct nand_chip *this = mtd->priv; */
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unsigned char byte;
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unsigned long dummy;
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if(bytes_read < 0) {
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read_buf = NDDB;
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dummy = NDDB;
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bytes_read = 0;
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}
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byte = (unsigned char) (read_buf>>(8 * bytes_read++));
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if(bytes_read >= 4)
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bytes_read = -1;
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DFC_DEBUG2("delta_read_byte: byte %u: 0x%x of (0x%x).\n", bytes_read, byte, read_buf);
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DFC_DEBUG2("delta_read_byte: byte %u: 0x%x of (0x%x).\n", bytes_read - 1, byte, read_buf);
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return byte;
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}
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@ -330,13 +346,15 @@ static void delta_cmdfunc(struct mtd_info *mtd, unsigned command,
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/* clear the ugly byte read buffer */
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bytes_read = -1;
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read_buf = 0;
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last_cmd = 0;
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/* if command is a double byte cmd, we set bit double cmd bit 19 */
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/* command2 = (command>>8) & 0xFF; */
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/* ndcb0 = command | ((command2 ? 1 : 0) << 19); *\/ */
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switch (command) {
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case NAND_CMD_READ0:
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DFC_DEBUG3("delta_cmdfunc: NAND_CMD_READ0, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
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delta_new_cmd();
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ndcb0 = (NAND_CMD_READ0 | (4<<16));
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column >>= 1; /* adjust for 16 bit bus */
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@ -346,7 +364,14 @@ static void delta_cmdfunc(struct mtd_info *mtd, unsigned command,
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((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
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event = NDSR_RDDREQ;
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goto write_cmd;
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case NAND_CMD_READ1:
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DFC_DEBUG2("delta_cmdfunc: NAND_CMD_READ1 unimplemented!\n");
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goto end;
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case NAND_CMD_READOOB:
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DFC_DEBUG1("delta_cmdfunc: NAND_CMD_READOOB unimplemented!\n");
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goto end;
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case NAND_CMD_READID:
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last_cmd = NAND_CMD_READID;
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delta_new_cmd();
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DFC_DEBUG2("delta_cmdfunc: NAND_CMD_READID.\n");
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ndcb0 = (NAND_CMD_READID | (3 << 21) | (1 << 16)); /* addr cycles*/
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@ -357,7 +382,7 @@ static void delta_cmdfunc(struct mtd_info *mtd, unsigned command,
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DFC_DEBUG2("delta_cmdfunc: NAND_CMD_PAGEPROG empty due to multicmd.\n");
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goto end;
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case NAND_CMD_ERASE1:
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DFC_DEBUG2("delta_cmdfunc: NAND_CMD_ERASE1.\n");
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DFC_DEBUG2("delta_cmdfunc: NAND_CMD_ERASE1, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
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delta_new_cmd();
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ndcb0 = (0xd060 | (1<<25) | (2<<21) | (1<<19) | (3<<16));
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ndcb1 = (page_addr & 0x00ffffff);
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@ -368,7 +393,7 @@ static void delta_cmdfunc(struct mtd_info *mtd, unsigned command,
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case NAND_CMD_SEQIN:
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/* send PAGE_PROG command(0x1080) */
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delta_new_cmd();
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DFC_DEBUG2("delta_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG.\n");
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DFC_DEBUG2("delta_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
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ndcb0 = (0x1080 | (1<<25) | (1<<21) | (1<<19) | (4<<16));
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column >>= 1; /* adjust for 16 bit bus */
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ndcb1 = (((column>>1) & 0xff) |
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@ -562,6 +587,7 @@ void board_nand_init(struct nand_chip *nand)
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#define MIN(x, y) ((x < y) ? x : y)
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#undef CFG_TIMING_TIGHT
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#ifndef CFG_TIMING_TIGHT
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tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1),
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DFC_MAX_tCH);
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@ -646,7 +672,7 @@ void board_nand_init(struct nand_chip *nand)
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NDCR = (NDCR_SPARE_EN | /* use the spare area */
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NDCR_DWIDTH_C | /* 16bit DFC data bus width */
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NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */
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(7 << 16) | /* read id count = 7 ???? mk@tbd */
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(2 << 16) | /* read id count = 7 ???? mk@tbd */
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NDCR_ND_ARB_EN | /* enable bus arbiter */
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NDCR_RDYM | /* flash device ready ir masked */
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NDCR_CS0_PAGEDM | /* ND_nCSx page done ir masked */
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@ -489,6 +489,7 @@ static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
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return nand_write_oob (mtd, ofs , 2, &retlen, buf);
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}
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#if READ_STATUS_BUG
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/**
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* nand_check_wp - [GENERIC] check if the chip is write protected
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* @mtd: MTD device structure
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@ -503,7 +504,12 @@ static int nand_check_wp (struct mtd_info *mtd)
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this->cmdfunc (mtd, NAND_CMD_STATUS, -1, -1);
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return (this->read_byte(mtd) & 0x80) ? 0 : 1;
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}
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#else
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static int nand_check_wp (struct mtd_info *mtd)
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{
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return 0;
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}
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#endif
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/**
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* nand_block_checkbad - [GENERIC] Check if a block is marked bad
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* @mtd: MTD device structure
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@ -1721,6 +1727,8 @@ static int nand_write_ecc (struct mtd_info *mtd, loff_t to, size_t len,
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numpages = min (totalpages, ppblock);
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page &= this->pagemask;
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startpage = page;
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oob = 0;
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this->oobdirty = 1;
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oobbuf = nand_prepare_oobbuf (mtd, eccbuf, oobsel,
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autoplace, numpages);
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/* Check, if we cross a chip boundary */
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@ -2145,13 +2153,14 @@ int nand_erase_nand (struct mtd_info *mtd, struct erase_info *instr, int allowbb
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instr->state = MTD_ERASING;
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while (len) {
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#ifndef NAND_ALLOW_ERASE_ALL
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/* Check if we have a bad block, we do not erase bad blocks ! */
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if (nand_block_checkbad(mtd, ((loff_t) page) << this->page_shift, 0, allowbbt)) {
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printk (KERN_WARNING "nand_erase: attempt to erase a bad block at page 0x%08x\n", page);
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instr->state = MTD_ERASE_FAILED;
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goto erase_exit;
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}
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#endif
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/* Invalidate the page cache, if we erase the block which contains
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the current cached page */
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if (page <= this->pagebuf && this->pagebuf < (page + pages_per_block))
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@ -43,7 +43,7 @@
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/*
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* Size of malloc() pool
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*/
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#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
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#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 256*1024)
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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/*
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@ -164,7 +164,7 @@
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*/
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/* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */
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#define CONFIG_NEW_NAND_CODE
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#define CFG_NAND0_BASE 0x43100040 /* 0x10000000 */
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#define CFG_NAND0_BASE 0x0 /* 0x43100040 */ /* 0x10000000 */
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#undef CFG_NAND1_BASE
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#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE }
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@ -174,9 +174,13 @@
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#define NAND_DELAY_US 25 /* mk@tbd: could be 0, I guess */
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/* nand timeout values */
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#define CFG_NAND_PROG_ERASE_TO 300
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#define CFG_NAND_PROG_ERASE_TO 3000
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#define CFG_NAND_OTHER_TO 100
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#define CFG_NAND_SENDCMD_RETRY 3
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#define NAND_ALLOW_ERASE_ALL 1
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#define CONFIG_MTD_DEBUG
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#define CONFIG_MTD_DEBUG_VERBOSE 1
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#define ADDR_COLUMN 1
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#define ADDR_PAGE 2
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