Lots of new stuff:
* Debug message can be turned on and off. * Waiting for events now times out. * Implemented RESET command. * Added appropriate nand_bbt_descriptor and nand_oobinfo. Remaining Problems: * Read Status still behaves weird an returns invalid stuff sometimes. * ECC Placement does not respect our scheme in nand_oobinfo.
This commit is contained in:
Markus Klotzbcher
Markus Klotzbcher
parent
f8785e96c9
commit
bf7cac033b
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@ -28,6 +28,41 @@
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#include <nand.h>
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#include <asm/arch/pxa-regs.h>
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/* mk@tbd move this to pxa-regs */
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#define OSCR_CLK_FREQ 3.250 /* MHz */
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#define CFG_DFC_DEBUG1
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#define CFG_DFC_DEBUG2
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#ifdef CFG_DFC_DEBUG1
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# define DFC_DEBUG1(fmt, args...) printf(fmt, ##args)
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#else
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# define DFC_DEBUG1(fmt, args...)
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#endif
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#ifdef CFG_DFC_DEBUG2
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# define DFC_DEBUG2(fmt, args...) printf(fmt, ##args)
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#else
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# define DFC_DEBUG2(fmt, args...)
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#endif
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static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
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static struct nand_bbt_descr delta_bbt_descr = {
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.options = 0,
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.offs = 0,
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.len = 2,
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.pattern = scan_ff_pattern
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};
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static struct nand_oobinfo delta_oob = {
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.useecc = MTD_NANDECC_AUTOPLACE,
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.eccbytes = 6,
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.eccpos = {2, 3, 4, 5, 6, 7},
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.oobfree = { {8, 2}, {12, 4} }
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};
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/*
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* not required for Monahans DFC
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*/
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@ -121,6 +156,9 @@ static void delta_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
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return;
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}
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/*
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* read a word. Not implemented as not used in NAND code.
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*/
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static u16 delta_read_word(struct mtd_info *mtd)
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{
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printf("delta_write_byte: UNIMPLEMENTED.\n");
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@ -128,43 +166,86 @@ static u16 delta_read_word(struct mtd_info *mtd)
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/* global var, too bad: mk@tbd: move to ->priv pointer */
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static unsigned long read_buf = 0;
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static unsigned char bytes_read = 0;
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static int bytes_read = -1;
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/* read a byte from NDDB Because we can only read 4 bytes from NDDB at
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* a time, we buffer the remaining bytes. The buffer is reset when a
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* new command is sent to the chip.
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*/
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static u_char delta_read_byte(struct mtd_info *mtd)
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{
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/* struct nand_chip *this = mtd->priv; */
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unsigned char byte;
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if(bytes_read == 0) {
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if(bytes_read < 0) {
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read_buf = NDDB;
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printk("delta_read_byte: 0x%x.\n", read_buf);
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bytes_read = 0;
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}
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byte = (unsigned char) (read_buf>>(8 * bytes_read++));
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if(bytes_read >= 4)
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bytes_read = 0;
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bytes_read = -1;
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printf("delta_read_byte: returning 0x%x.\n", byte);
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DFC_DEBUG2("delta_read_byte: byte %u: 0x%x of (0x%x).\n", bytes_read, byte, read_buf);
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return byte;
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}
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/* delay function */
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static void wait(unsigned long us)
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/* calculate delta between OSCR values start and now */
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static unsigned long get_delta(unsigned long start)
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{
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#define OSCR_CLK_FREQ 3.250 /* kHz */
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unsigned long cur = OSCR;
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if(cur < start) /* OSCR overflowed */
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return (cur + (start^0xffffffff));
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else
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return (cur - start);
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}
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/* delay function, this doesn't belong here */
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static void wait_us(unsigned long us)
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{
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unsigned long start = OSCR;
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unsigned long delta = 0, cur;
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us *= OSCR_CLK_FREQ;
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while (delta < us) {
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cur = OSCR;
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if(cur < start) /* OSCR overflowed */
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delta = cur + (start^0xffffffff);
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else
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delta = cur - start;
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while (get_delta(start) < us) {
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/* do nothing */
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}
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}
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static void delta_clear_nddb()
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{
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NDCR &= ~NDCR_ND_RUN;
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wait_us(CFG_NAND_OTHER_TO);
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}
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/* wait_event with timeout */
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static unsigned long delta_wait_event2(unsigned long event)
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{
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unsigned long ndsr, timeout, start = OSCR;
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if(!event)
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return 0xff000000;
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else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD))
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timeout = CFG_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ;
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else
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timeout = CFG_NAND_OTHER_TO * OSCR_CLK_FREQ;
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while(1) {
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ndsr = NDSR;
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if(ndsr & event) {
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NDSR |= event;
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break;
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}
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if(get_delta(start) > timeout) {
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DFC_DEBUG1("delta_wait_event: TIMEOUT waiting for event: 0x%x.\n", event);
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return 0xff000000;
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}
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}
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return ndsr;
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}
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#if DEADCODE
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/* poll the NAND Controller Status Register for event */
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static void delta_wait_event(unsigned long event)
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{
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@ -178,45 +259,46 @@ static void delta_wait_event(unsigned long event)
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}
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}
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}
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static unsigned long delta_wait_event2(unsigned long event)
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{
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unsigned long ndsr;
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if(!event)
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return;
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while(1) {
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ndsr = NDSR;
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if(ndsr & event) {
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NDSR |= event;
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break;
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}
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}
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return ndsr;
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}
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#endif
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/* we don't always wan't to do this */
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static void delta_new_cmd()
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{
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/* Clear NDSR */
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NDSR = 0xFFF;
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/* apparently NDCR[NDRUN] needs to be set before writing to NDCBx */
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if(!(NDCR & NDCR_ND_RUN)) {
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NDCR |= NDCR_ND_RUN;
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int retry = 0;
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unsigned long status;
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while(retry++ <= CFG_NAND_SENDCMD_RETRY) {
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/* Clear NDSR */
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NDSR = 0xFFF;
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while(1) {
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if(NDSR & NDSR_WRCMDREQ) {
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NDSR |= NDSR_WRCMDREQ; /* Ack */
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break;
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}
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/* set NDCR[NDRUN] */
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if(!(NDCR & NDCR_ND_RUN))
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NDCR |= NDCR_ND_RUN;
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status = delta_wait_event2(NDSR_WRCMDREQ);
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if(status & NDSR_WRCMDREQ)
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return;
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DFC_DEBUG2("delta_new_cmd: FAILED to get WRITECMDREQ, retry: %d.\n", retry);
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delta_clear_nddb();
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}
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DFC_DEBUG1("delta_new_cmd: giving up after %d retries.\n", retry);
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#if DEADCODE
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while(1) {
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if(NDSR & NDSR_WRCMDREQ) {
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NDSR |= NDSR_WRCMDREQ; /* Ack */
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break;
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}
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}
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#endif
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}
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/* this function is called after Programm and Erase Operations to
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* check for success or failure */
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static int delta_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
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{
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/* unsigned long timeo; */
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unsigned long ndsr=0, event=0;
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/* mk@tbd set appropriate timeouts */
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ndsr = delta_wait_event2(event);
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if(ndsr & NDSR_CS0_BBD)
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if((ndsr & NDSR_CS0_BBD) || (ndsr & 0xff000000))
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return(0x1); /* Status Read error */
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return 0;
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}
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/* this is really monahans, not board specific ... */
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/* cmdfunc send commands to the DFC */
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static void delta_cmdfunc(struct mtd_info *mtd, unsigned command,
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int column, int page_addr)
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{
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@ -246,7 +328,7 @@ static void delta_cmdfunc(struct mtd_info *mtd, unsigned command,
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unsigned long what_the_hack;
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/* clear the ugly byte read buffer */
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bytes_read = 0;
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bytes_read = -1;
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read_buf = 0;
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/* if command is a double byte cmd, we set bit double cmd bit 19 */
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@ -263,30 +345,30 @@ static void delta_cmdfunc(struct mtd_info *mtd, unsigned command,
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((page_addr<<8) & 0xff0000) |
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((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
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event = NDSR_RDDREQ;
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break;
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goto write_cmd;
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case NAND_CMD_READID:
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delta_new_cmd();
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printk("delta_cmdfunc: NAND_CMD_READID.\n");
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DFC_DEBUG2("delta_cmdfunc: NAND_CMD_READID.\n");
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ndcb0 = (NAND_CMD_READID | (3 << 21) | (1 << 16)); /* addr cycles*/
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event = NDSR_RDDREQ;
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break;
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goto write_cmd;
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case NAND_CMD_PAGEPROG:
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/* sent as a multicommand in NAND_CMD_SEQIN */
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printk("delta_cmdfunc: NAND_CMD_PAGEPROG.\n");
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DFC_DEBUG2("delta_cmdfunc: NAND_CMD_PAGEPROG empty due to multicmd.\n");
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goto end;
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case NAND_CMD_ERASE1:
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printf("delta_cmdfunc: NAND_CMD_ERASE1.\n");
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DFC_DEBUG2("delta_cmdfunc: NAND_CMD_ERASE1.\n");
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delta_new_cmd();
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ndcb0 = (0xd060 | (1<<25) | (2<<21) | (1<<19) | (3<<16));
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ndcb1 = (page_addr & 0x00ffffff);
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break;
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goto write_cmd;
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case NAND_CMD_ERASE2:
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printf("delta_cmdfunc: NAND_CMD_ERASE1 empty due to multicmd.\n");
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DFC_DEBUG2("delta_cmdfunc: NAND_CMD_ERASE2 empty due to multicmd.\n");
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goto end;
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case NAND_CMD_SEQIN:
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/* send PAGE_PROG command(0x1080) */
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delta_new_cmd();
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printf("delta_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG.\n");
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DFC_DEBUG2("delta_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG.\n");
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ndcb0 = (0x1080 | (1<<25) | (1<<21) | (1<<19) | (4<<16));
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column >>= 1; /* adjust for 16 bit bus */
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ndcb1 = (((column>>1) & 0xff) |
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@ -294,7 +376,7 @@ static void delta_cmdfunc(struct mtd_info *mtd, unsigned command,
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((page_addr<<8) & 0xff0000) |
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((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
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event = NDSR_WRDREQ;
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break;
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goto write_cmd;
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/* case NAND_CMD_SEQIN_pointer_operation: */
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/* /\* This is confusing because the command names are */
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@ -329,6 +411,7 @@ static void delta_cmdfunc(struct mtd_info *mtd, unsigned command,
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/* event = NDSR_WRDREQ; */
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/* break; */
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case NAND_CMD_STATUS:
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DFC_DEBUG2("delta_cmdfunc: NAND_CMD_STATUS.\n");
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/* oh, this is not nice. for some reason the real
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* status byte is in the second read from the data
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* buffer. The hack is to read the first byte right
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@ -336,39 +419,47 @@ static void delta_cmdfunc(struct mtd_info *mtd, unsigned command,
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* yields the right one.
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*/
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delta_new_cmd();
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ndcb0 = (NAND_CMD_STATUS | (4<<21));
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ndcb0 = NAND_CMD_STATUS | (4<<21);
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event = NDSR_RDDREQ;
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/* #define READ_STATUS_BUG 1 */
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#undef READ_STATUS_BUG
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#ifdef READ_STATUS_BUG
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NDCB0 = ndcb0;
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NDCB0 = ndcb1;
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NDCB0 = ndcb2;
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delta_wait_event(event);
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delta_wait_event2(event);
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what_the_hack = NDDB;
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if(what_the_hack != 0xffffffff) {
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DFC_DEBUG2("what the hack.\n");
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read_buf = what_the_hack;
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bytes_read = 0;
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}
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goto end;
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#endif
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break;
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goto write_cmd;
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case NAND_CMD_RESET:
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printf("delta_cmdfunc: NAND_CMD_RESET unimplemented.\n");
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break;
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DFC_DEBUG2("delta_cmdfunc: NAND_CMD_RESET.\n");
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ndcb0 = NAND_CMD_RESET | (5<<21);
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event = NDSR_CS0_CMDD;
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goto write_cmd;
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default:
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printk("delta_cmdfunc: error, unsupported command.\n");
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return;
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goto end;
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}
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write_cmd:
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NDCB0 = ndcb0;
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NDCB0 = ndcb1;
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NDCB0 = ndcb2;
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wait_event:
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delta_wait_event(event);
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delta_wait_event2(event);
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end:
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return;
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}
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static void delta_dfc_gpio_init()
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{
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printf("Setting up DFC GPIO's.\n");
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DFC_DEBUG2("Setting up DFC GPIO's.\n");
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/* no idea what is done here, see zylonite.c */
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GPIO4 = 0x1;
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@ -442,14 +533,16 @@ void board_nand_init(struct nand_chip *nand)
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#define NAND_TIMING_tCS 0
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#define NAND_TIMING_tWH 20
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#define NAND_TIMING_tWP 40
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/* #define NAND_TIMING_tRH 20 */
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/* #define NAND_TIMING_tRP 40 */
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#define NAND_TIMING_tRH 25
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#define NAND_TIMING_tRP 50
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#define NAND_TIMING_tRH 20
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#define NAND_TIMING_tRP 40
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/* #define NAND_TIMING_tRH 25 */
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/* #define NAND_TIMING_tRP 50 */
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#define NAND_TIMING_tR 11123
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#define NAND_TIMING_tWHR 110
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/* #define NAND_TIMING_tWHR 110 */
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#define NAND_TIMING_tWHR 100
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#define NAND_TIMING_tAR 10
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/* Maximum values for NAND Interface Timing Registers in DFC clock
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@ -468,7 +561,8 @@ void board_nand_init(struct nand_chip *nand)
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#define DFC_CLK_PER_US DFC_CLOCK/1000 /* clock period in ns */
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#define MIN(x, y) ((x < y) ? x : y)
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#ifndef CFG_TIMING_TIGHT
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tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1),
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DFC_MAX_tCH);
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tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1),
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|
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@ -487,9 +581,30 @@ void board_nand_init(struct nand_chip *nand)
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DFC_MAX_tWHR);
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tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) + 1),
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DFC_MAX_tAR);
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#else /* this is the tight timing */
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printf("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH, tCS, tWH, tWP, tRH, tRP, tR, tWHR, tAR);
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tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US)),
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DFC_MAX_tCH);
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tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US)),
|
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DFC_MAX_tCS);
|
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tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US)),
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DFC_MAX_tWH);
|
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tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US)),
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DFC_MAX_tWP);
|
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tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US)),
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DFC_MAX_tRH);
|
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tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US)),
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DFC_MAX_tRP);
|
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tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) - tCH - 2),
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DFC_MAX_tR);
|
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tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) - tCH - 2),
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DFC_MAX_tWHR);
|
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tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) - 2),
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DFC_MAX_tAR);
|
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#endif /* CFG_TIMING_TIGHT */
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|
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|
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DFC_DEBUG2("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH, tCS, tWH, tWP, tRH, tRP, tR, tWHR, tAR);
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|
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/* tRP value is split in the register */
|
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if(tRP & (1 << 4)) {
|
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|
|
@ -548,7 +663,7 @@ void board_nand_init(struct nand_chip *nand)
|
|||
|
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|
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/* wait 10 us due to cmd buffer clear reset */
|
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/* wait(10); */
|
||||
/* wait(10); */
|
||||
|
||||
|
||||
nand->hwcontrol = delta_hwcontrol;
|
||||
|
|
@ -565,6 +680,8 @@ void board_nand_init(struct nand_chip *nand)
|
|||
nand->write_buf = delta_write_buf;
|
||||
|
||||
nand->cmdfunc = delta_cmdfunc;
|
||||
nand->autooob = &delta_oob;
|
||||
nand->badblock_pattern = &delta_bbt_descr;
|
||||
}
|
||||
|
||||
#else
|
||||
|
|
|
|||
|
|
@ -189,7 +189,7 @@ cpuspeed: .word CFG_CPUSPEED
|
|||
#else
|
||||
#error "You have to define CFG_CPUSPEED!!"
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/* takes care the CP15 update has taken place */
|
||||
.macro CPWAIT reg
|
||||
|
|
|
|||
|
|
@ -173,6 +173,11 @@
|
|||
/* #define NAND_NO_RB */
|
||||
#define NAND_DELAY_US 25 /* mk@tbd: could be 0, I guess */
|
||||
|
||||
/* nand timeout values */
|
||||
#define CFG_NAND_PROG_ERASE_TO 300
|
||||
#define CFG_NAND_OTHER_TO 100
|
||||
#define CFG_NAND_SENDCMD_RETRY 3
|
||||
|
||||
#define ADDR_COLUMN 1
|
||||
#define ADDR_PAGE 2
|
||||
#define ADDR_COLUMN_PAGE 3
|
||||
|
|
|
|||
Loading…
Reference in New Issue