POST: Add ppc405 support to cache and UART POST
Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese
parent
d4024bb72d
commit
eb2b4010ae
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@ -53,14 +53,25 @@ int cache_post_test6 (int tlb, void *p, int size);
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static int tlb = -1; /* index to the victim TLB entry */
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#ifdef CONFIG_440
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static unsigned char testarea[CACHE_POST_SIZE]
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__attribute__((__aligned__(CACHE_POST_SIZE)));
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#endif
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int cache_post_test (int flags)
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{
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void* virt = (void*)CFG_POST_CACHE_ADDR;
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int ints, i, res = 0;
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u32 word0;
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int ints;
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int res = 0;
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/*
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* All 44x variants deal with cache management differently
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* because they have the address translation always enabled.
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* The 40x ppc's don't use address translation in U-Boot at all,
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* so we have to distinguish here between 40x and 44x.
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*/
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#ifdef CONFIG_440
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int word0, i;
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if (tlb < 0) {
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/*
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@ -83,6 +94,7 @@ int cache_post_test (int flags)
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}
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}
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}
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#endif
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ints = disable_interrupts ();
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WATCHDOG_RESET ();
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@ -37,6 +37,13 @@
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.text
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/*
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* All 44x variants deal with cache management differently
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* because they have the address translation always enabled.
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* The 40x ppc's don't use address translation in U-Boot at all,
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* so we have to distinguish here between 40x and 44x.
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*/
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#ifdef CONFIG_440
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/* void cache_post_disable (int tlb)
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*/
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cache_post_disable:
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@ -68,6 +75,43 @@ cache_post_wb:
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sync
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isync
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blr
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#else
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/* void cache_post_disable (int tlb)
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*/
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cache_post_disable:
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lis r0, 0x0000
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ori r0, r0, 0x0000
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mtdccr r0
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sync
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isync
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blr
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/* void cache_post_wt (int tlb)
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*/
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cache_post_wt:
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lis r0, 0x8000
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ori r0, r0, 0x0000
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mtdccr r0
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lis r0, 0x8000
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ori r0, r0, 0x0000
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mtdcwr r0
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sync
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isync
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blr
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/* void cache_post_wb (int tlb)
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*/
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cache_post_wb:
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lis r0, 0x8000
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ori r0, r0, 0x0000
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mtdccr r0
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lis r0, 0x0000
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ori r0, r0, 0x0000
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mtdcwr r0
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sync
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isync
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blr
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#endif
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/* void cache_post_dinvalidate (void *p, int size)
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*/
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@ -38,24 +38,77 @@
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#if CONFIG_POST & CFG_POST_UART
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/*
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* This table defines the UART's that should be tested and can
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* be overridden in the board config file
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*/
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#ifndef CFG_POST_UART_TABLE
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#define CFG_POST_UART_TABLE {UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE}
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#endif
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#include <asm/processor.h>
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#include <serial.h>
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#if defined(CONFIG_440)
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#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000300
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#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000400
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#define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000500
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#define UART3_BASE CFG_PERIPHERAL_BASE + 0x00000600
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#else
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#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200
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#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300
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#endif
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#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
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#define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000600
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#endif
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#if defined(CONFIG_440GP)
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#define CR0_MASK 0x3fff0000
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#define CR0_EXTCLK_ENA 0x00600000
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#define CR0_UDIV_POS 16
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#define UDIV_SUBTRACT 1
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#define UART0_SDR cntrl0
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#define MFREG(a, d) d = mfdcr(a)
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#define MTREG(a, d) mtdcr(a, d)
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#else /* #if defined(CONFIG_440GP) */
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/* all other 440 PPC's access clock divider via sdr register */
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#define CR0_MASK 0xdfffffff
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#define CR0_EXTCLK_ENA 0x00800000
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#define CR0_UDIV_POS 0
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#define UDIV_SUBTRACT 0
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#define UART0_SDR sdr_uart0
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#define UART1_SDR sdr_uart1
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#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \
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defined(CONFIG_440GR) || defined(CONFIG_440GRx) || \
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defined(CONFIG_440SP) || defined(CONFIG_440SPe)
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#define UART2_SDR sdr_uart2
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#endif
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#if defined(CONFIG_440EP) || defined(CONFIG_440EPx) || \
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defined(CONFIG_440GR) || defined(CONFIG_440GRx)
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#define UART3_SDR sdr_uart3
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#endif
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#define MFREG(a, d) mfsdr(a, d)
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#define MTREG(a, d) mtsdr(a, d)
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#endif /* #if defined(CONFIG_440GP) */
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#elif defined(CONFIG_405EP) || defined(CONFIG_405EZ)
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#define UART0_BASE 0xef600300
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#define UART1_BASE 0xef600400
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#define UCR0_MASK 0x0000007f
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#define UCR1_MASK 0x00007f00
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#define UCR0_UDIV_POS 0
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#define UCR1_UDIV_POS 8
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#define UDIV_MAX 127
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#else /* CONFIG_405GP || CONFIG_405CR */
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#define UART0_BASE 0xef600300
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#define UART1_BASE 0xef600400
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#define CR0_MASK 0x00001fff
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#define CR0_EXTCLK_ENA 0x000000c0
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#define CR0_UDIV_POS 1
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#define UDIV_MAX 32
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#endif
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#define UART_RBR 0x00
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#define UART_THR 0x00
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@ -71,8 +124,8 @@
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#define UART_DLM 0x01
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/*
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Line Status Register.
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*/
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* Line Status Register.
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*/
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#define asyncLSRDataReady1 0x01
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#define asyncLSROverrunError1 0x02
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#define asyncLSRParityError1 0x04
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@ -84,6 +137,7 @@
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_440)
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static int uart_post_init (unsigned long dev_base)
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{
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unsigned long reg;
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@ -147,6 +201,77 @@ static int uart_post_init (unsigned long dev_base)
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return 0;
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}
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#else /* CONFIG_440 */
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static int uart_post_init (unsigned long dev_base)
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{
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unsigned long reg;
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unsigned long tmp;
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unsigned long clk;
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unsigned long udiv;
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unsigned short bdiv;
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volatile char val;
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int i;
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for (i = 0; i < 3500; i++) {
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if (in8 (dev_base + UART_LSR) & asyncLSRTxHoldEmpty1)
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break;
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udelay (100);
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}
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#if defined(CONFIG_405EZ)
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serial_divs(gd->baudrate, &udiv, &bdiv);
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clk = tmp = reg = 0;
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#else
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#ifdef CONFIG_405EP
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reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK);
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clk = gd->cpu_clk;
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tmp = CFG_BASE_BAUD * 16;
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udiv = (clk + tmp / 2) / tmp;
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if (udiv > UDIV_MAX) /* max. n bits for udiv */
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udiv = UDIV_MAX;
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reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */
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reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */
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mtdcr (cpc0_ucr, reg);
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#else /* CONFIG_405EP */
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reg = mfdcr(cntrl0) & ~CR0_MASK;
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#ifdef CFG_EXT_SERIAL_CLOCK
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clk = CFG_EXT_SERIAL_CLOCK;
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udiv = 1;
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reg |= CR0_EXTCLK_ENA;
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#else
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clk = gd->cpu_clk;
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#ifdef CFG_405_UART_ERRATA_59
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udiv = 31; /* Errata 59: stuck at 31 */
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#else
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tmp = CFG_BASE_BAUD * 16;
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udiv = (clk + tmp / 2) / tmp;
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if (udiv > UDIV_MAX) /* max. n bits for udiv */
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udiv = UDIV_MAX;
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#endif
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#endif
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reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
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mtdcr (cntrl0, reg);
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#endif /* CONFIG_405EP */
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tmp = gd->baudrate * udiv * 16;
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bdiv = (clk + tmp / 2) / tmp;
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#endif /* CONFIG_405EZ */
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out8(dev_base + UART_LCR, 0x80); /* set DLAB bit */
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out8(dev_base + UART_DLL, bdiv); /* set baudrate divisor */
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out8(dev_base + UART_DLM, bdiv >> 8); /* set baudrate divisor */
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out8(dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
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out8(dev_base + UART_FCR, 0x00); /* disable FIFO */
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out8(dev_base + UART_MCR, 0x10); /* enable loopback mode */
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val = in8(dev_base + UART_LSR); /* clear line status */
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val = in8(dev_base + UART_RBR); /* read receive buffer */
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out8(dev_base + UART_SCR, 0x00); /* set scratchpad */
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out8(dev_base + UART_IER, 0x00); /* set interrupt enable reg */
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return (0);
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}
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#endif /* CONFIG_440 */
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static void uart_post_putc (unsigned long dev_base, char c)
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{
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int i;
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@ -198,9 +323,7 @@ done:
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int uart_post_test (int flags)
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{
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int i, res = 0;
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static unsigned long base[] = {
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UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE
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};
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static unsigned long base[] = CFG_POST_UART_TABLE;
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for (i = 0; i < sizeof (base) / sizeof (base[0]); i++) {
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if (test_ctlr (base[i], i))
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