ppc4xx: Add support for AMCC 405EP Taihu board
Signed-off-by: John Otken <john@softadvances.com>
This commit is contained in:
John Otken
Stefan Roese
parent
9f24a808f1
commit
d4024bb72d
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@ -248,6 +248,7 @@ Tolunay Orkun <torkun@nextio.com>
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John Otken <jotken@softadvances.com>
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luan PPC440SP
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taihu PPC405EP
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Keith Outwater <Keith_Outwater@mvis.com>
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8
MAKEALL
8
MAKEALL
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@ -88,10 +88,10 @@ LIST_4xx=" \
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ml300 ocotea OCRTC ORSG \
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p3p440 PCI405 pcs440ep PIP405 \
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PLU405 PMC405 PPChameleonEVB sbc405 \
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sc3 sequoia sequoia_nand taishan \
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VOH405 VOM405 W7OLMC W7OLMG \
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walnut WUH405 XPEDITE1K yellowstone \
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yosemite yucca \
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sc3 sequoia sequoia_nand taihu \
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taishan VOH405 VOM405 W7OLMC \
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W7OLMG walnut WUH405 XPEDITE1K \
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yellowstone yosemite yucca \
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"
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#########################################################################
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3
Makefile
3
Makefile
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@ -1254,6 +1254,9 @@ rainier_nand_config: unconfig
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sc3_config:unconfig
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@./mkconfig $(@:_config=) ppc ppc4xx sc3
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taihu_config: unconfig
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@$(MKCONFIG) $(@:_config=) ppc ppc4xx taihu amcc
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taishan_config: unconfig
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@$(MKCONFIG) $(@:_config=) ppc ppc4xx taishan amcc
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@ -0,0 +1,49 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS = $(BOARD).o flash.o lcd.o update.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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$(LIB): $(OBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean:
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rm -f $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,24 @@
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#
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# (C) Copyright 2000
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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TEXT_BASE = 0xFFFC0000
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,257 @@
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/*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <common.h>
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#include <command.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#define LCD_CMD_ADDR 0x50100002
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#define LCD_DATA_ADDR 0x50100003
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#define LCD_BLK_CTRL CPLD_REG1_ADDR
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static char *amcc_logo = "AMCC 405EP TAIHU EVALUATION KIT";
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static int addr_flag = 0x80;
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static void lcd_bl_ctrl(char val)
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{
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out_8((u8 *) LCD_BLK_CTRL, in_8((u8 *) LCD_BLK_CTRL) | val);
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}
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static void lcd_putc(int val)
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{
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int i = 100;
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char addr;
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while (i--) {
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if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/
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udelay(50);
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break;
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}
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udelay(50);
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}
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if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) {
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printf("LCD is busy\n");
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return;
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}
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addr = in_8((u8 *) LCD_CMD_ADDR);
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udelay(50);
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if ((addr != 0) && (addr % 0x10 == 0)) {
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addr_flag ^= 0x40;
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out_8((u8 *) LCD_CMD_ADDR, addr_flag);
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}
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udelay(50);
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out_8((u8 *) LCD_DATA_ADDR, val);
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udelay(50);
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}
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static void lcd_puts(char *s)
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{
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char *p = s;
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int i = 100;
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while (i--) {
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if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/
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udelay(50);
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break;
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}
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udelay(50);
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}
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if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) {
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printf("LCD is busy\n");
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return;
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}
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while (*p)
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lcd_putc(*p++);
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}
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static void lcd_put_logo(void)
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{
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int i = 100;
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char *p = amcc_logo;
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while (i--) {
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if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/
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udelay(50);
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break;
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}
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udelay(50);
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}
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if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) {
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printf("LCD is busy\n");
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return;
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}
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out_8((u8 *) LCD_CMD_ADDR, 0x80);
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while (*p)
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lcd_putc(*p++);
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}
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int lcd_init(void)
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{
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puts("LCD: ");
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out_8((u8 *) LCD_CMD_ADDR, 0x38); /* set function:8-bit,2-line,5x7 font type */
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udelay(50);
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out_8((u8 *) LCD_CMD_ADDR, 0x0f); /* set display on,cursor on,blink on */
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udelay(50);
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out_8((u8 *) LCD_CMD_ADDR, 0x01); /* display clear */
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udelay(2000);
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out_8((u8 *) LCD_CMD_ADDR, 0x06); /* set entry */
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udelay(50);
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lcd_bl_ctrl(0x02); /* set backlight on */
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lcd_put_logo();
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puts("ready\n");
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return 0;
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}
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static int do_lcd_clear (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
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{
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out_8((u8 *) LCD_CMD_ADDR, 0x01);
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udelay(2000);
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return 0;
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}
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static int do_lcd_puts (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
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{
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if (argc < 2) {
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printf("%s", cmdtp->usage);
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return 1;
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}
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lcd_puts(argv[1]);
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return 0;
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}
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static int do_lcd_putc (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
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{
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if (argc < 2) {
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printf("%s", cmdtp->usage);
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return 1;
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}
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lcd_putc((char)argv[1][0]);
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return 0;
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}
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static int do_lcd_cur (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
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{
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ulong count;
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ulong dir;
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char cur_addr;
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if (argc < 3) {
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printf("%s", cmdtp->usage);
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return 1;
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}
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count = simple_strtoul(argv[1], NULL, 16);
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if (count > 31) {
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printf("unable to shift > 0x20\n");
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count = 0;
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}
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dir = simple_strtoul(argv[2], NULL, 16);
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cur_addr = in_8((u8 *) LCD_CMD_ADDR);
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udelay(50);
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if (dir == 0x0) {
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if (addr_flag == 0x80) {
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if (count >= (cur_addr & 0xf)) {
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out_8((u8 *) LCD_CMD_ADDR, 0x80);
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udelay(50);
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count = 0;
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}
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} else {
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if (count >= ((cur_addr & 0x0f) + 0x0f)) {
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out_8((u8 *) LCD_CMD_ADDR, 0x80);
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addr_flag = 0x80;
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udelay(50);
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count = 0x0;
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} else if (count >= ( cur_addr & 0xf)) {
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count -= cur_addr & 0xf ;
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out_8((u8 *) LCD_CMD_ADDR, 0x80 | 0xf);
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addr_flag = 0x80;
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udelay(50);
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}
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}
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} else {
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if (addr_flag == 0x80) {
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if (count >= (0x1f - (cur_addr & 0xf))) {
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count = 0x0;
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addr_flag = 0xc0;
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out_8((u8 *) LCD_CMD_ADDR, 0xc0 | 0xf);
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udelay(50);
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} else if ((count + (cur_addr & 0xf ))>= 0x0f) {
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count = count + (cur_addr & 0xf) - 0x0f;
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addr_flag = 0xc0;
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out_8((u8 *) LCD_CMD_ADDR, 0xc0);
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udelay(50);
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}
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} else if ((count + (cur_addr & 0xf )) >= 0x0f) {
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count = 0x0;
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out_8((u8 *) LCD_CMD_ADDR, 0xC0 | 0x0F);
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udelay(50);
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}
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}
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while (count--) {
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if (dir == 0)
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out_8((u8 *) LCD_CMD_ADDR, 0x10);
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else
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out_8((u8 *) LCD_CMD_ADDR, 0x14);
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udelay(50);
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}
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return 0;
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}
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U_BOOT_CMD(
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lcd_cls, 1, 1, do_lcd_clear,
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"lcd_cls - lcd clear display\n",
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NULL
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);
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U_BOOT_CMD(
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lcd_puts, 2, 1, do_lcd_puts,
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"lcd_puts - display string on lcd\n",
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"<string> - <string> to be displayed\n"
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);
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U_BOOT_CMD(
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lcd_putc, 2, 1, do_lcd_putc,
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"lcd_putc - display char on lcd\n",
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"<char> - <char> to be displayed\n"
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);
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U_BOOT_CMD(
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lcd_cur, 3, 1, do_lcd_cur,
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"lcd_cur - shift cursor on lcd\n",
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"<count> <dir> - shift cursor on lcd <count> times, direction is <dir> \n"
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" <count> - 0..31\n"
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" <dir> - 0=backward 1=forward\n"
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);
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@ -0,0 +1,234 @@
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/*
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* (C) Copyright 2000-2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2005-2007
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* Beijing UD Technology Co., Ltd., taihusupport@amcc.com
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*
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* See file CREDITS for list of people who contributed to this
|
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* project.
|
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*
|
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <spi.h>
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#include <asm/gpio.h>
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extern int lcd_init(void);
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/*
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* board_early_init_f
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*/
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int board_early_init_f(void)
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{
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lcd_init();
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
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mtdcr(uicer, 0x00000000); /* disable all ints */
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mtdcr(uiccr, 0x00000000);
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mtdcr(uicpr, 0xFFFF7F00); /* set int polarities */
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mtdcr(uictr, 0x00000000); /* set int trigger levels */
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
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mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
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mtebc(pb3ap, CFG_EBC_PB3AP); /* memory bank 3 (CPLD_LCM) initialization */
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mtebc(pb3cr, CFG_EBC_PB3CR);
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return 0;
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}
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/*
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* Check Board Identity:
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*/
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int checkboard(void)
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{
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char *s = getenv("serial#");
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puts("Board: Taihu - AMCC PPC405EP Evaluation Board");
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if (s != NULL) {
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puts(", serial# ");
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puts(s);
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}
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putc('\n');
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return 0;
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}
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/*************************************************************************
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* long int initdram
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*
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************************************************************************/
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long int initdram(int board)
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{
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return CFG_SDRAM_SIZE_PER_BANK * CFG_SDRAM_BANKS; /* 128Mbytes */
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}
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static int do_sw_stat(cmd_tbl_t* cmd_tp, int flags, int argc, char *argv[])
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{
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char stat;
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int i;
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stat = in_8((u8 *) CPLD_REG0_ADDR);
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printf("SW2 status: ");
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for (i=0; i<4; i++) /* 4-position */
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printf("%d:%s ", i, stat & (0x08 >> i)?"on":"off");
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printf("\n");
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return 0;
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}
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U_BOOT_CMD (
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sw2_stat, 1, 1, do_sw_stat,
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"sw2_stat - show status of switch 2\n",
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NULL
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);
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static int do_led_ctl(cmd_tbl_t* cmd_tp, int flags, int argc, char *argv[])
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{
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int led_no;
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if (argc != 3) {
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printf("%s", cmd_tp->usage);
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return -1;
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}
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led_no = simple_strtoul(argv[1], NULL, 16);
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if (led_no != 1 && led_no != 2) {
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printf("%s", cmd_tp->usage);
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return -1;
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}
|
||||
|
||||
if (strcmp(argv[2],"off") == 0x0) {
|
||||
if (led_no == 1)
|
||||
gpio_write_bit(30, 1);
|
||||
else
|
||||
gpio_write_bit(31, 1);
|
||||
} else if (strcmp(argv[2],"on") == 0x0) {
|
||||
if (led_no == 1)
|
||||
gpio_write_bit(30, 0);
|
||||
else
|
||||
gpio_write_bit(31, 0);
|
||||
} else {
|
||||
printf("%s", cmd_tp->usage);
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD (
|
||||
led_ctl, 3, 1, do_led_ctl,
|
||||
"led_ctl - make led 1 or 2 on or off\n",
|
||||
"<led_no> <on/off> - make led <led_no> on/off,\n"
|
||||
"\tled_no is 1 or 2\t"
|
||||
);
|
||||
|
||||
#define SPI_CS_GPIO0 0
|
||||
#define SPI_SCLK_GPIO14 14
|
||||
#define SPI_DIN_GPIO15 15
|
||||
#define SPI_DOUT_GPIO16 16
|
||||
|
||||
void spi_scl(int bit)
|
||||
{
|
||||
gpio_write_bit(SPI_SCLK_GPIO14, bit);
|
||||
}
|
||||
|
||||
void spi_sda(int bit)
|
||||
{
|
||||
gpio_write_bit(SPI_DOUT_GPIO16, bit);
|
||||
}
|
||||
|
||||
unsigned char spi_read(void)
|
||||
{
|
||||
return (unsigned char)gpio_read_out_bit(SPI_DIN_GPIO15);
|
||||
}
|
||||
|
||||
void taihu_spi_chipsel(int cs)
|
||||
{
|
||||
gpio_write_bit(SPI_CS_GPIO0, cs);
|
||||
}
|
||||
|
||||
spi_chipsel_type spi_chipsel[]= {
|
||||
taihu_spi_chipsel
|
||||
};
|
||||
|
||||
int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]);
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
static unsigned char int_lines[32] = {
|
||||
29, 30, 27, 28, 29, 30, 25, 27,
|
||||
29, 30, 27, 28, 29, 30, 27, 28,
|
||||
29, 30, 27, 28, 29, 30, 27, 28,
|
||||
29, 30, 27, 28, 29, 30, 27, 28};
|
||||
|
||||
static void taihu_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
|
||||
{
|
||||
unsigned char int_line = int_lines[PCI_DEV(dev) & 31];
|
||||
|
||||
pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
|
||||
}
|
||||
|
||||
int pci_pre_init(struct pci_controller *hose)
|
||||
{
|
||||
hose->fixup_irq = taihu_pci_fixup_irq;
|
||||
return 1;
|
||||
}
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
#ifdef CFG_DRAM_TEST
|
||||
int testdram(void)
|
||||
{
|
||||
unsigned long *mem = (unsigned long *)0;
|
||||
const unsigned long kend = (1024 / sizeof(unsigned long));
|
||||
unsigned long k, n;
|
||||
unsigned long msr;
|
||||
unsigned long total_kbytes = CFG_SDRAM_SIZE_PER_BANK * CFG_SDRAM_BANKS / 1024;
|
||||
|
||||
msr = mfmsr();
|
||||
mtmsr(msr & ~(MSR_EE));
|
||||
|
||||
for (k = 0; k < total_kbytes ;
|
||||
++k, mem += (1024 / sizeof(unsigned long))) {
|
||||
if ((k & 1023) == 0)
|
||||
printf("%3d MB\r", k / 1024);
|
||||
|
||||
memset(mem, 0xaaaaaaaa, 1024);
|
||||
for (n = 0; n < kend; ++n) {
|
||||
if (mem[n] != 0xaaaaaaaa) {
|
||||
printf("SDRAM test fails at: %08x\n",
|
||||
(uint) & mem[n]);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
memset(mem, 0x55555555, 1024);
|
||||
for (n = 0; n < kend; ++n) {
|
||||
if (mem[n] != 0x55555555) {
|
||||
printf("SDRAM test fails at: %08x\n",
|
||||
(uint) & mem[n]);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
printf("SDRAM test passes\n");
|
||||
mtmsr(msr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CFG_DRAM_TEST */
|
||||
|
|
@ -0,0 +1,150 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
.resetvec 0xFFFFFFFC :
|
||||
{
|
||||
*(.resetvec)
|
||||
} = 0xffff
|
||||
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
cpu/ppc4xx/start.o (.text)
|
||||
cpu/ppc4xx/kgdb.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/crc32.o (.text)
|
||||
lib_ppc/extable.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
|
||||
/* . = env_offset;*/
|
||||
/* common/environment.o(.text)*/
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
*(.eh_frame)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
|
|
@ -0,0 +1,132 @@
|
|||
/*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <asm/processor.h>
|
||||
#include <i2c.h>
|
||||
|
||||
#define PCI_M66EN 0x10
|
||||
|
||||
static uchar buf_33[] =
|
||||
{
|
||||
0xb5, /* 0x00:hce =1, bss = 0, pae=1, ppdv= 0b10,spe = 1,ebw=0b01*/
|
||||
0x80, /* 0x01~0x03:ptm1ms =0x80000001 */
|
||||
0x00,
|
||||
0x00,
|
||||
0x00, /* 0x04~0x06:ptm1la = 0x00000000 */
|
||||
0x00,
|
||||
0x00,
|
||||
0x00, /* 0x07~0x09:ptm2ma = 0x00000000 */
|
||||
0x00,
|
||||
0x00,
|
||||
0x00, /* 0x0a~0x0c:ptm2la = 0x00000000 */
|
||||
0x00,
|
||||
0x00,
|
||||
0x10, /* 0x0d~0x0e:vendor id 0x1014*/
|
||||
0x14,
|
||||
0x00, /* 0x0f~0x10:device id 0x0000*/
|
||||
0x00,
|
||||
0x00, /* 0x11:revision 0x00 */
|
||||
0x00, /* 0x12~0x14:class 0x000000 */
|
||||
0x00,
|
||||
0x00,
|
||||
0x10, /* 0x15~0x16:subsystem vendor id */
|
||||
0xe8,
|
||||
0x00, /* 0x17~0x18:subsystem device id */
|
||||
0x00,
|
||||
0x61, /* 0x19: opdv=0b01,cbdv=0b10,ccdv=0b00,ptm2ms_ena=0, ptm1ms_ena=1 */
|
||||
0x68, /* 0x1a: rpci=1,fbmul=0b1010,epdv=0b00 */
|
||||
0x2d, /* 0x1b: fwdvb=0b101,fwdva=0b101 */
|
||||
0x82, /* 0x1c: pllr=1,sscs=0,mpdv=0b00,tun[22-23]=0b10 */
|
||||
0xbe, /* 0x1d: tun[24-31]=0xbe */
|
||||
0x00,
|
||||
0x00
|
||||
};
|
||||
|
||||
static uchar buf_66[] =
|
||||
{
|
||||
0xb5, /* 0x00:hce =1, bss = 0, pae=1, ppdv= 0b10,spe = 1,ebw=0b01*/
|
||||
0x80, /* 0x01~0x03:ptm1ms =0x80000001 */
|
||||
0x00,
|
||||
0x00,
|
||||
0x00, /* 0x04~0x06:ptm1la = 0x00000000 */
|
||||
0x00,
|
||||
0x00,
|
||||
0x00, /* 0x07~0x09:ptm2ma = 0x00000000 */
|
||||
0x00,
|
||||
0x00,
|
||||
0x00, /* 0x0a~0x0c:ptm2la = 0x00000000 */
|
||||
0x00,
|
||||
0x00,
|
||||
0x10, /* 0x0d~0x0e:vendor id 0x1014*/
|
||||
0x14,
|
||||
0x00, /* 0x0f~0x10:device id 0x0000*/
|
||||
0x00,
|
||||
0x00, /* 0x11:revision 0x00 */
|
||||
0x00, /* 0x12~0x14:class 0x000000 */
|
||||
0x00,
|
||||
0x00,
|
||||
0x10, /* 0x15~0x16:subsystem vendor id */
|
||||
0xe8,
|
||||
0x00, /* 0x17~0x18:subsystem device id */
|
||||
0x00,
|
||||
0x61, /* 0x19: opdv=0b01,cbdv=0b10,ccdv=0b00,ptm2ms_ena=0, ptm1ms_ena=1 */
|
||||
0x68, /* 0x1a: rpci=1,fbmul=0b1010,epdv=0b00 */
|
||||
0x2d, /* 0x1b: fwdvb=0b101,fwdva=0b101 */
|
||||
0x82, /* 0x1c: pllr=1,sscs=0,mpdv=0b00,tun[22-23]=0b10 */
|
||||
0xbe, /* 0x1d: tun[24-31]=0xbe */
|
||||
0x00,
|
||||
0x00
|
||||
};
|
||||
|
||||
static int update_boot_eeprom(cmd_tbl_t* cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
ulong len = 0x20;
|
||||
uchar chip = CFG_I2C_EEPROM_ADDR;
|
||||
uchar *pbuf;
|
||||
uchar base;
|
||||
int i;
|
||||
|
||||
if ((*(volatile char*)CPLD_REG0_ADDR & PCI_M66EN) != PCI_M66EN) {
|
||||
pbuf = buf_33;
|
||||
base = 0x00;
|
||||
} else {
|
||||
pbuf = buf_66;
|
||||
base = 0x40;
|
||||
}
|
||||
|
||||
for (i = 0; i< len; i++, base++) {
|
||||
if (i2c_write(chip, base, 1, &pbuf[i],1)!= 0) {
|
||||
printf("i2c_write fail\n");
|
||||
return 1;
|
||||
}
|
||||
udelay(11000);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD (
|
||||
update_boot_eeprom, 1, 1, update_boot_eeprom,
|
||||
"update_boot_eeprom - update boot eeprom content\n",
|
||||
NULL
|
||||
);
|
||||
|
|
@ -79,7 +79,9 @@ void spi_init (void)
|
|||
*/
|
||||
int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din)
|
||||
{
|
||||
#ifdef CFG_IMMR
|
||||
volatile immap_t *immr = (immap_t *)CFG_IMMR;
|
||||
#endif
|
||||
uchar tmpdin = 0;
|
||||
uchar tmpdout = 0;
|
||||
int j;
|
||||
|
|
|
|||
|
|
@ -186,6 +186,7 @@ void gpio_set_chip_configuration(void)
|
|||
out32(GPIO0_TCR, reg);
|
||||
}
|
||||
|
||||
#ifdef GPIO1
|
||||
if (gpio_core == GPIO1) {
|
||||
/*
|
||||
* Setup output value
|
||||
|
|
@ -203,6 +204,7 @@ void gpio_set_chip_configuration(void)
|
|||
reg = in32(GPIO1_TCR) | (0x80000000 >> (i));
|
||||
out32(GPIO1_TCR, reg);
|
||||
}
|
||||
#endif /* GPIO1 */
|
||||
|
||||
reg = in32(GPIO_OS(core_add+offs))
|
||||
& ~(GPIO_MASK >> (j*2));
|
||||
|
|
|
|||
|
|
@ -209,8 +209,17 @@ void sdram_init(void)
|
|||
|
||||
if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
|
||||
/*
|
||||
* OK, size detected -> all done
|
||||
* OK, size detected. Enable second bank if
|
||||
* defined (assumes same type as bank 0)
|
||||
*/
|
||||
#ifdef CONFIG_SDRAM_BANK1
|
||||
u32 b1cr = mb0cf[i].size | mb0cf[i].reg;
|
||||
|
||||
mtsdram0(mem_mcopt1, 0x00000000);
|
||||
mtsdram0(mem_mb1cf, b1cr); /* SDRAM0_B1CR */
|
||||
mtsdram0(mem_mcopt1, 0x80800000);
|
||||
udelay(10000);
|
||||
#endif
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1869,6 +1869,11 @@ ppc405ep_init:
|
|||
ori r3,r3,CFG_EBC_PB4CR@l
|
||||
mtdcr ebccfgd,r3
|
||||
#endif
|
||||
#ifdef CONFIG_TAIHU
|
||||
mfdcr r4, CPC0_BOOT
|
||||
andi. r5, r4, CPC0_BOOT_SEP@l
|
||||
bne strap_0 /* serial eeprom present */
|
||||
#endif
|
||||
|
||||
#ifndef CFG_CPC0_PCI
|
||||
li r3,CPC0_PCI_HOST_CFG_EN
|
||||
|
|
@ -1886,12 +1891,16 @@ ppc405ep_init:
|
|||
beq ..pci_cfg_set /* if not set, then bypass reg write*/
|
||||
#endif
|
||||
ori r3,r3,CPC0_PCI_ARBIT_EN
|
||||
#ifdef CONFIG_TAIHU
|
||||
ori r3,r3,CPC0_PCI_SPE
|
||||
#endif
|
||||
#else /* CFG_CPC0_PCI */
|
||||
li r3,CFG_CPC0_PCI
|
||||
#endif /* CFG_CPC0_PCI */
|
||||
..pci_cfg_set:
|
||||
mtdcr CPC0_PCI, r3 /* Enable internal arbiter*/
|
||||
|
||||
strap_0:
|
||||
/*
|
||||
!-----------------------------------------------------------------------
|
||||
! Check to see if chip is in bypass mode.
|
||||
|
|
@ -1947,11 +1956,35 @@ ppc405ep_init:
|
|||
..no_pllset:
|
||||
#endif /* CONFIG_BUBINGA */
|
||||
|
||||
#ifdef CONFIG_TAIHU
|
||||
mfdcr r4, CPC0_BOOT
|
||||
andi. r5, r4, CPC0_BOOT_SEP@l
|
||||
bne strap_1 /* serial eeprom present */
|
||||
addis r5,0,CPLD_REG0_ADDR@h
|
||||
ori r5,r5,CPLD_REG0_ADDR@l
|
||||
andi. r5, r5, 0x10
|
||||
bne _pci_66mhz
|
||||
#endif /* CONFIG_TAIHU */
|
||||
|
||||
addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
|
||||
ori r3,r3,PLLMR0_DEFAULT@l /* */
|
||||
addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
|
||||
ori r4,r4,PLLMR1_DEFAULT@l /* */
|
||||
|
||||
#ifdef CONFIG_TAIHU
|
||||
b 1f
|
||||
_pci_66mhz:
|
||||
addis r3,0,PLLMR0_DEFAULT_PCI66@h
|
||||
ori r3,r3,PLLMR0_DEFAULT_PCI66@l
|
||||
addis r4,0,PLLMR1_DEFAULT_PCI66@h
|
||||
ori r4,r4,PLLMR1_DEFAULT_PCI66@l
|
||||
b 1f
|
||||
strap_1:
|
||||
mfdcr r3, CPC0_PLLMR0
|
||||
mfdcr r4, CPC0_PLLMR1
|
||||
1:
|
||||
#endif /* CONFIG_TAIHU */
|
||||
|
||||
b pll_write /* Write the CPC0_PLLMR with new value */
|
||||
|
||||
pll_done:
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@ include $(TOPDIR)/config.mk
|
|||
|
||||
LIB = $(obj)libdtt.a
|
||||
|
||||
COBJS = lm75.o ds1621.o adm1021.o lm81.o
|
||||
COBJS = lm75.o ds1621.o adm1021.o lm81.o ds1775.o
|
||||
|
||||
SRCS := $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
|
|
|||
|
|
@ -0,0 +1,156 @@
|
|||
/*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* Dallas Semiconductor's DS1775 Digital Thermometer and Thermostat
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#ifdef CONFIG_DTT_DS1775
|
||||
#include <i2c.h>
|
||||
#include <dtt.h>
|
||||
|
||||
#define DTT_I2C_DEV_CODE 0x49 /* Dallas Semi's DS1775 device code */
|
||||
|
||||
int dtt_read(int sensor, int reg)
|
||||
{
|
||||
int dlen;
|
||||
uchar data[2];
|
||||
|
||||
/*
|
||||
* Calculate sensor address and command
|
||||
*/
|
||||
sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); /* Calculate addr of ds1775 */
|
||||
|
||||
/*
|
||||
* Prepare to handle 2 byte result
|
||||
*/
|
||||
if ((reg == DTT_READ_TEMP) ||
|
||||
(reg == DTT_TEMP_OS) || (reg == DTT_TEMP_HYST))
|
||||
dlen = 2;
|
||||
else
|
||||
dlen = 1;
|
||||
|
||||
/*
|
||||
* Now try to read the register
|
||||
*/
|
||||
if (i2c_read(sensor, reg, 1, data, dlen) != 0)
|
||||
return 1;
|
||||
|
||||
/*
|
||||
* Handle 2 byte result
|
||||
*/
|
||||
if (dlen == 2)
|
||||
return ((int)((short)data[1] + (((short)data[0]) << 8)));
|
||||
|
||||
return (int) data[0];
|
||||
}
|
||||
|
||||
|
||||
int dtt_write(int sensor, int reg, int val)
|
||||
{
|
||||
int dlen;
|
||||
uchar data[2];
|
||||
|
||||
/*
|
||||
* Calculate sensor address and register
|
||||
*/
|
||||
sensor = DTT_I2C_DEV_CODE + (sensor & 0x07);
|
||||
|
||||
/*
|
||||
* Handle various data sizes
|
||||
*/
|
||||
if ((reg == DTT_READ_TEMP) ||
|
||||
(reg == DTT_TEMP_OS) || (reg == DTT_TEMP_HYST)) {
|
||||
dlen = 2;
|
||||
data[0] = (char)((val >> 8) & 0xff); /* MSB first */
|
||||
data[1] = (char)(val & 0xff);
|
||||
} else {
|
||||
dlen = 1;
|
||||
data[0] = (char)(val & 0xff);
|
||||
}
|
||||
|
||||
/*
|
||||
* Write value to device
|
||||
*/
|
||||
if (i2c_write(sensor, reg, 1, data, dlen) != 0)
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static int _dtt_init(int sensor)
|
||||
{
|
||||
int val;
|
||||
|
||||
/*
|
||||
* Setup High Temp
|
||||
*/
|
||||
val = ((CFG_DTT_MAX_TEMP * 2) << 7) & 0xff80;
|
||||
if (dtt_write(sensor, DTT_TEMP_OS, val) != 0)
|
||||
return 1;
|
||||
udelay(50000); /* Max 50ms */
|
||||
|
||||
/*
|
||||
* Setup Low Temp - hysteresis
|
||||
*/
|
||||
val = (((CFG_DTT_MAX_TEMP - CFG_DTT_HYSTERESIS) * 2) << 7) & 0xff80;
|
||||
if (dtt_write(sensor, DTT_TEMP_HYST, val) != 0)
|
||||
return 1;
|
||||
udelay(50000); /* Max 50ms */
|
||||
|
||||
/*
|
||||
* Setup configuraton register
|
||||
*
|
||||
* Fault Tolerance limits 4, Thermometer resolution bits is 9,
|
||||
* Polarity = Active Low,continuous conversion mode, Thermostat
|
||||
* mode is interrupt mode
|
||||
*/
|
||||
val = 0xa;
|
||||
if (dtt_write(sensor, DTT_CONFIG, val) != 0)
|
||||
return 1;
|
||||
udelay(50000); /* Max 50ms */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int dtt_init (void)
|
||||
{
|
||||
int i;
|
||||
unsigned char sensors[] = CONFIG_DTT_SENSORS;
|
||||
|
||||
for (i = 0; i < sizeof(sensors); i++) {
|
||||
if (_dtt_init(sensors[i]) != 0)
|
||||
printf("DTT%d: FAILED\n", i+1);
|
||||
else
|
||||
printf("DTT%d: %i C\n", i+1, dtt_get_temp(sensors[i]));
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
int dtt_get_temp(int sensor)
|
||||
{
|
||||
return (dtt_read(sensor, DTT_READ_TEMP) / 256);
|
||||
}
|
||||
|
||||
|
||||
#endif /* CONFIG_DTT_DS1775 */
|
||||
|
|
@ -0,0 +1,473 @@
|
|||
/*
|
||||
* (C) Copyright 2000-2005
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* (C) Copyright 2005-2007
|
||||
* Beijing UD Technology Co., Ltd., taihusupport@amcc.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
|
||||
#define CONFIG_405EP 1 /* this is a PPC405 CPU */
|
||||
#define CONFIG_4xx 1 /* member of PPC4xx family */
|
||||
#define CONFIG_TAIHU 1 /* on a taihu board */
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f */
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
|
||||
|
||||
#define CONFIG_NO_SERIAL_EEPROM
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
#ifdef CONFIG_NO_SERIAL_EEPROM
|
||||
|
||||
/*
|
||||
!-------------------------------------------------------------------------------
|
||||
! PLL settings for 333MHz CPU, 111MHz PLB/SDRAM, 55MHz EBC, 33MHz PCI,
|
||||
! assuming a 33MHz input clock to the 405EP from the C9531.
|
||||
!-------------------------------------------------------------------------------
|
||||
*/
|
||||
#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
|
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_3)
|
||||
#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \
|
||||
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
|
||||
#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
|
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_1)
|
||||
#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \
|
||||
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
|
||||
|
||||
#define PLLMR0_DEFAULT PLLMR0_333_111_55_37
|
||||
#define PLLMR1_DEFAULT PLLMR1_333_111_55_37
|
||||
#define PLLMR0_DEFAULT_PCI66 PLLMR0_333_111_55_111
|
||||
#define PLLMR1_DEFAULT_PCI66 PLLMR1_333_111_55_111
|
||||
|
||||
#endif
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE 1
|
||||
#define CONFIG_PREBOOT "echo;" \
|
||||
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
|
||||
"echo"
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"bootfile=/tftpboot/taihu/uImage\0" \
|
||||
"rootpath=/opt/eldk/ppc_4xx\0" \
|
||||
"netdev=eth0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
|
||||
"flash_nfs=run nfsargs addip addtty;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"flash_self=run ramargs addip addtty;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
||||
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
|
||||
"bootm\0" \
|
||||
"kernel_addr=FC000000\0" \
|
||||
"ramdisk_addr=FC180000\0" \
|
||||
"load=tftp 200000 /tftpboot/taihu/u-boot.bin\0" \
|
||||
"update=protect off FFFC0000 FFFFFFFF;era FFFC0000 FFFFFFFF;" \
|
||||
"cp.b 200000 FFFC0000 40000\0" \
|
||||
"upd=run load;run update\0" \
|
||||
""
|
||||
#define CONFIG_BOOTCOMMAND "run flash_self"
|
||||
|
||||
#if 0
|
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
|
||||
#else
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
#endif
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_PHY_ADDR 0x14 /* PHY address */
|
||||
#define CONFIG_HAS_ETH1
|
||||
#define CONFIG_PHY1_ADDR 0x10 /* EMAC1 PHY address */
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
|
||||
#define CONFIG_PHY_RESET 1
|
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
|
||||
CFG_CMD_ASKENV | \
|
||||
CFG_CMD_CACHE | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_SPI | \
|
||||
CFG_CMD_IRQ | \
|
||||
CFG_CMD_MII | \
|
||||
CFG_CMD_NET | \
|
||||
CFG_CMD_PCI | \
|
||||
CFG_CMD_PING | \
|
||||
CFG_CMD_REGINFO | \
|
||||
CFG_CMD_SDRAM )
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
#undef CONFIG_SPD_EEPROM /* use SPD EEPROM for setup */
|
||||
#define CFG_SDRAM_SIZE_PER_BANK 0x04000000 /* 64MB */
|
||||
#define CFG_SDRAM_BANKS 2
|
||||
|
||||
/*
|
||||
* SDRAM configuration (please see cpu/ppc/sdram.[ch])
|
||||
*/
|
||||
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
|
||||
#define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */
|
||||
|
||||
/* SDRAM timings used in datasheet */
|
||||
#define CFG_SDRAM_CL 3 /* CAS latency */
|
||||
#define CFG_SDRAM_tRP 20 /* PRECHARGE command period */
|
||||
#define CFG_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
|
||||
#define CFG_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
|
||||
#define CFG_SDRAM_tRFC 66 /* Auto refresh period */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
|
||||
|
||||
/*
|
||||
* If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
|
||||
* If CFG_405_UART_ERRATA_59, then UART divisor is 31.
|
||||
* Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
|
||||
* The Linux BASE_BAUD define should match this configuration.
|
||||
* baseBaud = cpuClock/(uartDivisor*16)
|
||||
* If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
|
||||
* set Linux BASE_BAUD to 403200.
|
||||
*/
|
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO
|
||||
#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
|
||||
#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
|
||||
#define CFG_BASE_BAUD 691200
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CONFIG_UART1_CONSOLE 1
|
||||
|
||||
|
||||
/* The following table includes the supported baudrates */
|
||||
#define CFG_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
|
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */
|
||||
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
|
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
|
||||
#define CONFIG_LOOPW 1 /* enable loopw command */
|
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
|
||||
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
|
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CFG_I2C_SLAVE 0x7F
|
||||
|
||||
#define CFG_I2C_NOPROBES { 0x69 } /* avoid iprobe hangup (why?) */
|
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_EEPROM)
|
||||
#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
|
||||
#endif
|
||||
|
||||
|
||||
#define CONFIG_SOFT_SPI
|
||||
#define SPI_SCL spi_scl
|
||||
#define SPI_SDA spi_sda
|
||||
#define SPI_READ spi_read()
|
||||
#define SPI_DELAY udelay(2)
|
||||
#ifndef __ASSEMBLY__
|
||||
void spi_scl(int);
|
||||
void spi_sda(int);
|
||||
unsigned char spi_read(void);
|
||||
#endif
|
||||
|
||||
/* standard dtt sensor configuration */
|
||||
#define CONFIG_DTT_DS1775 1
|
||||
#define CONFIG_DTT_SENSORS { 0 }
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
|
||||
#define PCI_HOST_FORCE 1 /* configure as pci host */
|
||||
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
|
||||
|
||||
#define CONFIG_PCI /* include pci support */
|
||||
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
/* resource configuration */
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
|
||||
#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
|
||||
#define CFG_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */
|
||||
#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
|
||||
#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
|
||||
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
|
||||
#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
|
||||
#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
|
||||
#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
|
||||
#define CONFIG_EEPRO100 1
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CFG_SDRAM_BASE 0x00000000
|
||||
#define CFG_FLASH_BASE 0xFFE00000
|
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
|
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
|
||||
#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
|
||||
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
|
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CFG_FLASH_ADDR0 0x555
|
||||
#define CFG_FLASH_ADDR1 0x2aa
|
||||
#define CFG_FLASH_WORD_SIZE unsigned short
|
||||
|
||||
#ifdef CFG_ENV_IS_IN_FLASH
|
||||
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
|
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
|
||||
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
|
||||
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
|
||||
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
|
||||
#endif /* CFG_ENV_IS_IN_FLASH */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* NVRAM organization
|
||||
*/
|
||||
#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
|
||||
#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */
|
||||
|
||||
#ifdef CFG_ENV_IS_IN_NVRAM
|
||||
#define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
|
||||
#define CFG_ENV_ADDR \
|
||||
(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env*/
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PPC405 GPIO Configuration
|
||||
*/
|
||||
#define CFG_440_GPIO_TABLE { /* GPIO Alternate1 */ \
|
||||
{ \
|
||||
/* GPIO Core 0 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast SPI CS */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO5 TS3 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 SPI SCLK */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 SPI DI */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 SPI DO */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 PCI INTA */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 PCI INTB */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 PCI INTC */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 PCI INTD */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 USB */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 EBC */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 unused */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD UART1 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx UART0 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 User LED1 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 User LED2 */ \
|
||||
} \
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CFG_DCACHE_SIZE 16384 /* For IBM 405EP CPU */
|
||||
#define CFG_CACHELINE_SIZE 32
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Init Memory Controller:
|
||||
*
|
||||
* BR0/1 and OR0/1 (FLASH)
|
||||
*/
|
||||
|
||||
#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
|
||||
#define FLASH_BASE1_PRELIM 0xFC000000 /* FLASH bank #1 */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in data cache)
|
||||
*/
|
||||
/* use on chip memory (OCM) for temperary stack until sdram is tested */
|
||||
#define CFG_TEMP_STACK_OCM 1
|
||||
|
||||
/* On Chip Memory location */
|
||||
#define CFG_OCM_DATA_ADDR 0xF8000000
|
||||
#define CFG_OCM_DATA_SIZE 0x1000
|
||||
#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
|
||||
#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
|
||||
|
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* External Bus Controller (EBC) Setup
|
||||
*/
|
||||
|
||||
/* Memory Bank 0 (Flash/SRAM) initialization */
|
||||
#define CFG_EBC_PB0AP 0x03815600
|
||||
#define CFG_EBC_PB0CR 0xFFE3A000 /* BAS=0xFFE,BS=2MB,BU=R/W,BW=16bit */
|
||||
|
||||
/* Memory Bank 1 (NVRAM/RTC) initialization */
|
||||
#define CFG_EBC_PB1AP 0x05815600
|
||||
#define CFG_EBC_PB1CR 0xFC0BA000 /* BAS=0xFc0,BS=32MB,BU=R/W,BW=16bit */
|
||||
|
||||
/* Memory Bank 2 (USB device) initialization */
|
||||
#define CFG_EBC_PB2AP 0x03016600
|
||||
#define CFG_EBC_PB2CR 0x50018000 /* BAS=0x500,BS=1MB,BU=R/W,BW=8bit */
|
||||
|
||||
/* Memory Bank 3 (LCM and D-flip-flop) initialization */
|
||||
#define CFG_EBC_PB3AP 0x158FF600
|
||||
#define CFG_EBC_PB3CR 0x50118000 /* BAS=0x501,BS=1MB,BU=R/W,BW=8bit */
|
||||
|
||||
/* Memory Bank 4 (not install) initialization */
|
||||
#define CFG_EBC_PB4AP 0x158FF600
|
||||
#define CFG_EBC_PB4CR 0x5021A000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for GPIO setup (PPC405EP specific)
|
||||
*
|
||||
* GPIO0[0] - External Bus Controller BLAST output
|
||||
* GPIO0[1-9] - Instruction trace outputs
|
||||
* GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
|
||||
* GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
|
||||
* GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
|
||||
* GPIO0[24-27] - UART0 control signal inputs/outputs
|
||||
* GPIO0[28-29] - UART1 data signal input/output
|
||||
* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
|
||||
*/
|
||||
#define CFG_GPIO0_OSRH 0x15555550 /* output select high/low */
|
||||
#define CFG_GPIO0_OSRL 0x00000110
|
||||
#define CFG_GPIO0_ISR1H 0x00000001 /* input select high/low */
|
||||
#define CFG_GPIO0_ISR1L 0x15545440
|
||||
#define CFG_GPIO0_TSRH 0x00000000 /* three-state select high/low */
|
||||
#define CFG_GPIO0_TSRL 0x00000000
|
||||
#define CFG_GPIO0_TCR 0xFFFE8117 /* three-state control */
|
||||
#define CFG_GPIO0_ODR 0x00000000 /* open drain */
|
||||
|
||||
#define GPIO0 0 /* GPIO controller 0 */
|
||||
|
||||
/* the GPIO macros in include/ppc405.h for High/Low registers are backwards */
|
||||
|
||||
#define GPIOx_OSL (GPIO0_OSRH-GPIO_BASE)
|
||||
#define GPIOx_TSL (GPIO0_TSRH-GPIO_BASE)
|
||||
#define GPIOx_IS1L (GPIO0_ISR1H-GPIO_BASE)
|
||||
#define GPIOx_IS2L (GPIO0_ISR1H-GPIO_BASE)
|
||||
#define GPIOx_IS3L (GPIO0_ISR1H-GPIO_BASE)
|
||||
|
||||
#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO output select */
|
||||
#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO three-state select */
|
||||
#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO input select */
|
||||
#define GPIO_IS2(x) (x+GPIOx_IS1L)
|
||||
#define GPIO_IS3(x) (x+GPIOx_IS1L)
|
||||
|
||||
#define CPLD_REG0_ADDR 0x50100000
|
||||
#define CPLD_REG1_ADDR 0x50100001
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -29,6 +29,7 @@
|
|||
|
||||
#if defined(CONFIG_DTT_LM75) || \
|
||||
defined(CONFIG_DTT_DS1621) || \
|
||||
defined(CONFIG_DTT_DS1775) || \
|
||||
defined(CONFIG_DTT_LM81) || \
|
||||
defined(CONFIG_DTT_ADM1021)
|
||||
|
||||
|
|
@ -78,6 +79,13 @@ extern int dtt_get_temp(int sensor);
|
|||
#define DTT_CONFIG 0xAC
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_DTT_DS1775)
|
||||
#define DTT_READ_TEMP 0x0
|
||||
#define DTT_CONFIG 0x1
|
||||
#define DTT_TEMP_HYST 0x2
|
||||
#define DTT_TEMP_OS 0x3
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_DTT_ADM1021)
|
||||
#define DTT_READ_LOC_VALUE 0x00
|
||||
#define DTT_READ_REM_VALUE 0x01
|
||||
|
|
|
|||
Loading…
Reference in New Issue