Merge branch 'master' into next

.gitignore

@@ -47,6 +47,9 @@ patches-*
 patches
 series
 
+# gdb files
+.gdb_history
+
 # cscope files
 cscope.*
 

MAINTAINERS

@@ -412,6 +412,10 @@ Rune Torgersen <runet@innovsys.com>
 
 	MPC8266ADS	MPC8266
 
+Peter Tyser <ptyser@xes-inc.com>
+
+	XPEDITE5200	MPC8548
+	XPEDITE5370	MPC8572
 
 David Updegraff <dave@cray.com>
 
@@ -705,7 +709,6 @@ Yasushi Shoji <yashi@atmark-techno.com>
 Michal Simek <monstr@monstr.eu>
 
 	ML401		MicroBlaze
-	XUPV2P		MicroBlaze
 
 #########################################################################
 # Coldfire Systems:							#

MAKEALL

@@ -1,6 +1,15 @@
 #!/bin/sh
 
-: ${JOBS:=}
+# Determine number of CPU cores if no default was set
+: ${BUILD_NCPUS:="`getconf _NPROCESSORS_ONLN`"}
+
+if [ "$BUILD_NCPUS" -gt 1 ]
+then
+	JOBS=-j`expr "$BUILD_NCPUS" + 1`
+else
+	JOBS=""
+fi
+
 
 if [ "${CROSS_COMPILE}" ] ; then
 	MAKE="make CROSS_COMPILE=${CROSS_COMPILE}"
@@ -377,6 +386,8 @@ LIST_85xx="		\
 	TQM8548		\
 	TQM8555		\
 	TQM8560		\
+	XPEDITE5200	\
+	XPEDITE5370	\
 "
 
 #########################################################################
@@ -690,7 +701,6 @@ LIST_nios2="		\
 LIST_microblaze="	\
 	ml401		\
 	suzaku		\
-	xupv2p		\
 "
 
 #########################################################################

Makefile

@@ -21,8 +21,8 @@
 # MA 02111-1307 USA
 #
 
-VERSION = 2008
+VERSION = 2009
-PATCHLEVEL = 10
+PATCHLEVEL = 01
 SUBLEVEL =
 EXTRAVERSION =
 ifneq "$(SUBLEVEL)" ""
@@ -30,6 +30,7 @@ U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 else
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL)$(EXTRAVERSION)
 endif
+TIMESTAMP_FILE = $(obj)include/timestamp_autogenerated.h
 VERSION_FILE = $(obj)include/version_autogenerated.h
 
 HOSTARCH := $(shell uname -m | \
@@ -44,7 +45,12 @@ HOSTARCH := $(shell uname -m | \
 HOSTOS := $(shell uname -s | tr '[:upper:]' '[:lower:]' | \
 	    sed -e 's/\(cygwin\).*/cygwin/')
 
-export	HOSTARCH HOSTOS
+# Set shell to bash if possible, otherwise fall back to sh
+SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \
+	else if [ -x /bin/bash ]; then echo /bin/bash; \
+	else echo sh; fi; fi)
+
+export	HOSTARCH HOSTOS SHELL
 
 # Deal with colliding definitions from tcsh etc.
 VENDOR=
@@ -221,6 +227,8 @@ LIBS += disk/libdisk.a
 LIBS += drivers/bios_emulator/libatibiosemu.a
 LIBS += drivers/block/libblock.a
 LIBS += drivers/dma/libdma.a
+LIBS += drivers/fpga/libfpga.a
+LIBS += drivers/gpio/libgpio.a
 LIBS += drivers/hwmon/libhwmon.a
 LIBS += drivers/i2c/libi2c.a
 LIBS += drivers/input/libinput.a
@@ -230,6 +238,7 @@ LIBS += drivers/mtd/libmtd.a
 LIBS += drivers/mtd/nand/libnand.a
 LIBS += drivers/mtd/nand_legacy/libnand_legacy.a
 LIBS += drivers/mtd/onenand/libonenand.a
+LIBS += drivers/mtd/ubi/libubi.a
 LIBS += drivers/mtd/spi/libspi_flash.a
 LIBS += drivers/net/libnet.a
 LIBS += drivers/net/phy/libphy.a
@@ -259,7 +268,7 @@ LIBS += api/libapi.a
 LIBS += post/libpost.a
 
 LIBS := $(addprefix $(obj),$(LIBS))
-.PHONY : $(LIBS) $(VERSION_FILE)
+.PHONY : $(LIBS) $(TIMESTAMP_FILE) $(VERSION_FILE)
 
 LIBBOARD = board/$(BOARDDIR)/lib$(BOARD).a
 LIBBOARD := $(addprefix $(obj),$(LIBBOARD))
@@ -339,7 +348,7 @@ $(obj)u-boot:		depend $(SUBDIRS) $(OBJS) $(LIBBOARD) $(LIBS) $(LDSCRIPT)
 $(OBJS):	depend $(obj)include/autoconf.mk
 		$(MAKE) -C cpu/$(CPU) $(if $(REMOTE_BUILD),$@,$(notdir $@))
 
-$(LIBS):	depend $(obj)include/autoconf.mk
+$(LIBS):	depend $(obj)include/autoconf.mk $(SUBDIRS)
 		$(MAKE) -C $(dir $(subst $(obj),,$@))
 
 $(LIBBOARD):	depend $(LIBS) $(obj)include/autoconf.mk
@@ -351,13 +360,13 @@ $(SUBDIRS):	depend $(obj)include/autoconf.mk
 $(LDSCRIPT):	depend $(obj)include/autoconf.mk
 		$(MAKE) -C $(dir $@) $(notdir $@)
 
-$(NAND_SPL):	$(VERSION_FILE)	$(obj)include/autoconf.mk
+$(NAND_SPL):	$(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk
 		$(MAKE) -C nand_spl/board/$(BOARDDIR) all
 
 $(U_BOOT_NAND):	$(NAND_SPL) $(obj)u-boot.bin $(obj)include/autoconf.mk
 		cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin
 
-$(ONENAND_IPL):	$(VERSION_FILE)	$(obj)include/autoconf.mk
+$(ONENAND_IPL):	$(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk
 		$(MAKE) -C onenand_ipl/board/$(BOARDDIR) all
 
 $(U_BOOT_ONENAND):	$(ONENAND_IPL) $(obj)u-boot.bin $(obj)include/autoconf.mk
@@ -366,10 +375,13 @@ $(U_BOOT_ONENAND):	$(ONENAND_IPL) $(obj)u-boot.bin $(obj)include/autoconf.mk
 
 $(VERSION_FILE):
 		@( printf '#define U_BOOT_VERSION "U-Boot %s%s"\n' "$(U_BOOT_VERSION)" \
-		 '$(shell $(CONFIG_SHELL) $(TOPDIR)/tools/setlocalversion $(TOPDIR))' \
+		 '$(shell $(TOPDIR)/tools/setlocalversion $(TOPDIR))' ) > $@.tmp
-		 ) > $@.tmp
 		@cmp -s $@ $@.tmp && rm -f $@.tmp || mv -f $@.tmp $@
 
+$(TIMESTAMP_FILE):
+		@date +'#define U_BOOT_DATE "%b %d %C%y"' > $@
+		@date +'#define U_BOOT_TIME "%T"' >> $@
+
 gdbtools:
 		$(MAKE) -C tools/gdb all || exit 1
 
@@ -379,7 +391,7 @@ updater:
 env:
 		$(MAKE) -C tools/env all MTD_VERSION=${MTD_VERSION} || exit 1
 
-depend dep:	$(VERSION_FILE)
+depend dep:	$(TIMESTAMP_FILE) $(VERSION_FILE)
 		for dir in $(SUBDIRS) ; do $(MAKE) -C $$dir _depend ; done
 
 TAG_SUBDIRS += include
@@ -396,6 +408,7 @@ TAG_SUBDIRS += disk
 TAG_SUBDIRS += common
 TAG_SUBDIRS += drivers/bios_emulator
 TAG_SUBDIRS += drivers/block
+TAG_SUBDIRS += drivers/gpio
 TAG_SUBDIRS += drivers/hwmon
 TAG_SUBDIRS += drivers/i2c
 TAG_SUBDIRS += drivers/input
@@ -452,7 +465,8 @@ $(obj)include/autoconf.mk: $(obj)include/config.h
 	set -e ; \
 	: Extract the config macros ; \
 	$(CPP) $(CFLAGS) -DDO_DEPS_ONLY -dM include/common.h | \
-		sed -n -f tools/scripts/define2mk.sed > $@
+		sed -n -f tools/scripts/define2mk.sed > $@.tmp && \
+	mv $@.tmp $@
 
 sinclude $(obj)include/autoconf.mk.dep
 
@@ -460,7 +474,7 @@ sinclude $(obj)include/autoconf.mk.dep
 else	# !config.mk
 all $(obj)u-boot.hex $(obj)u-boot.srec $(obj)u-boot.bin \
 $(obj)u-boot.img $(obj)u-boot.dis $(obj)u-boot \
-$(SUBDIRS) $(VERSION_FILE) gdbtools updater env depend \
+$(SUBDIRS) $(TIMESTAMP_FILE) $(VERSION_FILE) gdbtools updater env depend \
 dep tags ctags etags cscope $(obj)System.map:
 	@echo "System not configured - see README" >&2
 	@ exit 1
@@ -1250,14 +1264,11 @@ CMS700_config:	unconfig
 CPCI2DP_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci2dp esd
 
-CPCI405_config:		unconfig
+CPCI405_config		\
-	@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci405 esd
-
 CPCI4052_config		\
 CPCI405DT_config	\
 CPCI405AB_config:	unconfig
 	@mkdir -p $(obj)board/esd/cpci405
-	@echo "TEXT_BASE = 0xFFFC0000" > $(obj)board/esd/cpci405/config.tmp
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci405 esd
 
 CPCIISER4_config:	unconfig
@@ -2455,6 +2466,12 @@ TQM8560_config:		unconfig
 	echo "#define CONFIG_BOARDNAME \"TQM$${CTYPE}\"">>$(obj)include/config.h;
 	@$(MKCONFIG) -a TQM85xx ppc mpc85xx tqm85xx tqc
 
+XPEDITE5200_config:	unconfig
+	@$(MKCONFIG) $(@:_config=) ppc mpc85xx xpedite5200 xes
+
+XPEDITE5370_config:	unconfig
+	@$(MKCONFIG) $(@:_config=) ppc mpc85xx xpedite5370 xes
+
 #########################################################################
 ## MPC86xx Systems
 #########################################################################
@@ -2584,17 +2601,84 @@ afeb9260_config:	unconfig
 at91cap9adk_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm926ejs at91cap9adk atmel at91
 
+at91sam9260ek_nandflash_config \
+at91sam9260ek_dataflash_cs0_config \
+at91sam9260ek_dataflash_cs1_config \
 at91sam9260ek_config	:	unconfig
-	@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9260ek atmel at91
+	@mkdir -p $(obj)include
+	@if [ "$(findstring _nandflash,$@)" ] ; then \
+		echo "#define CONFIG_SYS_USE_NANDFLASH 1"	>>$(obj)include/config.h ; \
+		$(XECHO) "... with environment variable in NAND FLASH" ; \
+	elif [ "$(findstring dataflash_cs0,$@)" ] ; then \
+		echo "#define CONFIG_SYS_USE_DATAFLASH_CS0 1"	>>$(obj)include/config.h ; \
+		$(XECHO) "... with environment variable in SPI DATAFLASH CS0" ; \
+	else \
+		echo "#define CONFIG_SYS_USE_DATAFLASH_CS1 1"	>>$(obj)include/config.h ; \
+		$(XECHO) "... with environment variable in SPI DATAFLASH CS1" ; \
+	fi;
+	@$(MKCONFIG) -a at91sam9260ek arm arm926ejs at91sam9260ek atmel at91
 
+at91sam9xeek_nandflash_config \
+at91sam9xeek_dataflash_cs0_config \
+at91sam9xeek_dataflash_cs1_config \
+at91sam9xeek_config	:	unconfig
+	@mkdir -p $(obj)include
+	@if [ "$(findstring _nandflash,$@)" ] ; then \
+		echo "#define CONFIG_SYS_USE_NANDFLASH 1"	>>$(obj)include/config.h ; \
+		$(XECHO) "... with environment variable in NAND FLASH" ; \
+	elif [ "$(findstring dataflash_cs0,$@)" ] ; then \
+		echo "#define CONFIG_SYS_USE_DATAFLASH_CS0 1"	>>$(obj)include/config.h ; \
+		$(XECHO) "... with environment variable in SPI DATAFLASH CS0" ; \
+	else \
+		echo "#define CONFIG_SYS_USE_DATAFLASH_CS1 1"	>>$(obj)include/config.h ; \
+		$(XECHO) "... with environment variable in SPI DATAFLASH CS1" ; \
+	fi;
+	@$(MKCONFIG) -n at91sam9xeek -a at91sam9260ek arm arm926ejs at91sam9260ek atmel at91sam9
+
+at91sam9261ek_nandflash_config \
+at91sam9261ek_dataflash_cs0_config \
+at91sam9261ek_dataflash_cs3_config \
 at91sam9261ek_config	:	unconfig
-	@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9261ek atmel at91
+	@mkdir -p $(obj)include
+	@if [ "$(findstring _nandflash,$@)" ] ; then \
+		echo "#define CONFIG_SYS_USE_NANDFLASH 1"	>>$(obj)include/config.h ; \
+		$(XECHO) "... with environment variable in NAND FLASH" ; \
+	elif [ "$(findstring dataflash_cs3,$@)" ] ; then \
+		echo "#define CONFIG_SYS_USE_DATAFLASH_CS3 1"	>>$(obj)include/config.h ; \
+		$(XECHO) "... with environment variable in SPI DATAFLASH CS3" ; \
+	else \
+		echo "#define CONFIG_SYS_USE_DATAFLASH_CS0 1"	>>$(obj)include/config.h ; \
+		$(XECHO) "... with environment variable in SPI DATAFLASH CS0" ; \
+	fi;
+	@$(MKCONFIG) -a at91sam9261ek arm arm926ejs at91sam9261ek atmel at91
 
+at91sam9263ek_nandflash_config \
+at91sam9263ek_dataflash_config \
+at91sam9263ek_dataflash_cs0_config \
 at91sam9263ek_config	:	unconfig
-	@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9263ek atmel at91
+	@mkdir -p $(obj)include
+	@if [ "$(findstring _nandflash,$@)" ] ; then \
+		echo "#define CONFIG_SYS_USE_NANDFLASH 1"	>>$(obj)include/config.h ; \
+		$(XECHO) "... with environment variable in NAND FLASH" ; \
+	else \
+		echo "#define CONFIG_SYS_USE_DATAFLASH 1"	>>$(obj)include/config.h ; \
+		$(XECHO) "... with environment variable in SPI DATAFLASH CS0" ; \
+	fi;
+	@$(MKCONFIG) -a at91sam9263ek arm arm926ejs at91sam9263ek atmel at91
 
+at91sam9rlek_nandflash_config \
+at91sam9rlek_dataflash_config \
+at91sam9rlek_dataflash_cs0_config \
 at91sam9rlek_config	:	unconfig
-	@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9rlek atmel at91
+	@mkdir -p $(obj)include
+	@if [ "$(findstring _nandflash,$@)" ] ; then \
+		echo "#define CONFIG_SYS_USE_NANDFLASH 1"	>>$(obj)include/config.h ; \
+		$(XECHO) "... with environment variable in NAND FLASH" ; \
+	else \
+		echo "#define CONFIG_SYS_USE_DATAFLASH 1"	>>$(obj)include/config.h ; \
+		$(XECHO) "... with environment variable in SPI DATAFLASH CS0" ; \
+	fi;
+	@$(MKCONFIG) -a at91sam9rlek arm arm926ejs at91sam9rlek atmel at91
 
 ########################################################################
 ## ARM Integrator boards - see doc/README-integrator for more info.
@@ -3099,11 +3183,6 @@ suzaku_config:	unconfig
 	@echo "#define CONFIG_SUZAKU 1" > $(obj)include/config.h
 	@$(MKCONFIG) -a $(@:_config=) microblaze microblaze suzaku AtmarkTechno
 
-xupv2p_config:	unconfig
-	@mkdir -p $(obj)include
-	@echo "#define CONFIG_XUPV2P 1" > $(obj)include/config.h
-	@$(MKCONFIG) -a $(@:_config=) microblaze microblaze xupv2p xilinx
-
 #========================================================================
 # Blackfin
 #========================================================================
@@ -3154,9 +3233,9 @@ mimc200_config		:	unconfig
 ## sh2 (Renesas SuperH)
 #########################################################################
 rsk7203_config: unconfig
-	@ >include/config.h
+	@mkdir -p $(obj)include
-	@echo "#define CONFIG_RSK7203 1" >> include/config.h
+	@echo "#define CONFIG_RSK7203 1" > $(obj)/include/config.h
-	@./mkconfig -a $(@:_config=) sh sh2 rsk7203 renesas
+	@$(MKCONFIG) -a $(@:_config=) sh sh2 rsk7203 renesas
 
 #########################################################################
 ## sh3 (Renesas SuperH)
@@ -3179,7 +3258,7 @@ ms7720se_config: unconfig
 MigoR_config :       unconfig
 	@mkdir -p $(obj)include
 	@echo "#define CONFIG_MIGO_R 1" > $(obj)include/config.h
-	@./mkconfig -a $(@:_config=) sh sh4 MigoR renesas
+	@$(MKCONFIG) -a $(@:_config=) sh sh4 MigoR renesas
 
 ms7750se_config: unconfig
 	@mkdir -p $(obj)include
@@ -3275,7 +3354,7 @@ clean:
 	@rm -f $(obj)include/bmp_logo.h
 	@rm -f $(obj)nand_spl/{u-boot-spl,u-boot-spl.map,System.map}
 	@rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl-2k.bin,ipl-4k.bin,ipl.map}
-	@rm -f $(obj)api_examples/demo $(VERSION_FILE)
+	@rm -f $(obj)api_examples/demo $(TIMESTAMP_FILE) $(VERSION_FILE)
 	@find $(OBJTREE) -type f \
 		\( -name 'core' -o -name '*.bak' -o -name '*~' \
 		-o -name '*.o'	-o -name '*.a'	\) -print \

README

@@ -381,6 +381,24 @@ The following options need to be configured:
 		This define fills in the correct boot CPU in the boot
 		param header, the default value is zero if undefined.
 
+- vxWorks boot parameters:
+
+		bootvx constructs a valid bootline using the following
+		environments variables: bootfile, ipaddr, serverip, hostname.
+		It loads the vxWorks image pointed bootfile.
+
+		CONFIG_SYS_VXWORKS_BOOT_DEVICE - The vxworks device name
+		CONFIG_SYS_VXWORKS_MAC_PTR - Ethernet 6 byte MA -address
+		CONFIG_SYS_VXWORKS_SERVERNAME - Name of the server
+		CONFIG_SYS_VXWORKS_BOOT_ADDR - Address of boot parameters
+
+		CONFIG_SYS_VXWORKS_ADD_PARAMS
+
+		Add it at the end of the bootline. E.g "u=username pw=secret"
+
+		Note: If a "bootargs" environment is defined, it will overwride
+		the defaults discussed just above.
+
 - Serial Ports:
 		CONFIG_PL010_SERIAL
 
@@ -603,6 +621,8 @@ The following options need to be configured:
 		CONFIG_CMD_MII		* MII utility commands
 		CONFIG_CMD_NAND		* NAND support
 		CONFIG_CMD_NET		  bootp, tftpboot, rarpboot
+		CONFIG_CMD_PCA953X	* PCA953x I2C gpio commands
+		CONFIG_CMD_PCA953X_INFO	* PCA953x I2C gpio info command
 		CONFIG_CMD_PCI		* pciinfo
 		CONFIG_CMD_PCMCIA		* PCMCIA support
 		CONFIG_CMD_PING		* send ICMP ECHO_REQUEST to network
@@ -680,6 +700,13 @@ The following options need to be configured:
 		Note that if the RTC uses I2C, then the I2C interface
 		must also be configured. See I2C Support, below.
 
+- GPIO Support:
+		CONFIG_PCA953X		- use NXP's PCA953X series I2C GPIO
+		CONFIG_PCA953X_INFO	- enable pca953x info command
+
+		Note that if the GPIO device uses I2C, then the I2C interface
+		must also be configured. See I2C Support, below.
+
 - Timestamp Support:
 
 		When CONFIG_TIMESTAMP is selected, the timestamp
@@ -2157,6 +2184,11 @@ Configuration Settings:
 		This option also enables the building of the cfi_flash driver
 		in the drivers directory
 
+- CONFIG_FLASH_CFI_MTD
+		This option enables the building of the cfi_mtd driver
+		in the drivers directory. The driver exports CFI flash
+		to the MTD layer.
+
 - CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 		Use buffered writes to flash.
 
@@ -3708,7 +3740,7 @@ MPC826x processors), on others (parts of) the data cache can be
 locked as (mis-) used as memory, etc.
 
 	Chris Hallinan posted a good summary of these issues to the
-	u-boot-users mailing list:
+	U-Boot mailing list:
 
 	Subject: RE: [U-Boot-Users] RE: More On Memory Bank x (nothingness)?
 	From: "Chris Hallinan" <clh@net1plus.com>
@@ -3918,7 +3950,7 @@ int main (int argc, char *argv[])
 
 	Download latest U-Boot source;
 
-	Subscribe to u-boot-users mailing list;
+	Subscribe to u-boot mailing list;
 
 	if (clueless) {
 		email ("Hi, I am new to U-Boot, how do I get started?");
@@ -3995,10 +4027,11 @@ Since the number of patches for U-Boot is growing, we need to
 establish some rules. Submissions which do not conform to these rules
 may be rejected, even when they contain important and valuable stuff.
 
-Patches shall be sent to the u-boot-users mailing list.
-
 Please see http://www.denx.de/wiki/U-Boot/Patches for details.
 
+Patches shall be sent to the u-boot mailing list <u-boot@lists.denx.de>;
+see http://lists.denx.de/mailman/listinfo/u-boot
+
 When you send a patch, please include the following information with
 it:
 
@@ -4061,7 +4094,7 @@ Notes:
   disabled must not need more memory than the old code without your
   modification.
 
-* Remember that there is a size limit of 40 kB per message on the
+* Remember that there is a size limit of 100 kB per message on the
-  u-boot-users mailing list. Bigger patches will be moderated. If
+  u-boot mailing list. Bigger patches will be moderated. If they are
-  they are reasonable and not bigger than 100 kB, they will be
+  reasonable and not too big, they will be acknowledged. But patches
-  acknowledged. Even bigger patches should be avoided.
+  bigger than the size limit should be avoided.

board/afeb9260/partition.c

@@ -34,4 +34,3 @@ dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
 	{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
 	{0x00008400, 0x00041FFF, FLAG_PROTECT_CLEAR, 0, "U-Boot"},
 };
-

board/amcc/canyonlands/init.S

@@ -89,7 +89,7 @@ tlbtab:
 #endif
 
 	/* TLB-entry for OCM */
-	tlbentry(CONFIG_SYS_OCM_BASE, SZ_16K, 0x00040000, 4, AC_R|AC_W|AC_X|SA_I)
+	tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
 
 	/* TLB-entry for Local Configuration registers => peripherals */
 	tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS, 4, AC_R|AC_W|AC_X|SA_G|SA_I)

board/amcc/luan/luan.c

@@ -25,6 +25,7 @@
 #include <command.h>
 #include <ppc4xx.h>
 #include <asm/processor.h>
+#include <asm/ppc4xx-isram.h>
 #include <spd_sdram.h>
 #include "epld.h"
 
@@ -255,7 +256,7 @@ static int on_off( const char *s )
  ************************************************************************/
 static void l2cache_disable(void)
 {
-	mtdcr( l2_cache_cfg, 0 );
+	mtdcr( L2_CACHE_CFG, 0 );
 }
 
 
@@ -265,24 +266,24 @@ static void l2cache_disable(void)
  ************************************************************************/
 static void l2cache_enable(void)	/* see p258 7.4.1 Enabling L2 Cache */
 {
-	mtdcr( l2_cache_cfg, 0x80000000 );	/* enable L2_MODE L2_CFG[L2M] */
+	mtdcr( L2_CACHE_CFG, 0x80000000 );	/* enable L2_MODE L2_CFG[L2M] */
 
-	mtdcr( l2_cache_addr, 0 );		/* set L2_ADDR with all zeros */
+	mtdcr( L2_CACHE_ADDR, 0 );		/* set L2_ADDR with all zeros */
 
-	mtdcr( l2_cache_cmd, 0x80000000 );	/* issue HCLEAR command via L2_CMD */
+	mtdcr( L2_CACHE_CMD, 0x80000000 );	/* issue HCLEAR command via L2_CMD */
 
-	while (!(mfdcr( l2_cache_stat ) & 0x80000000 ))  ;; /* poll L2_SR for completion */
+	while (!(mfdcr( L2_CACHE_STAT ) & 0x80000000 ))  ;; /* poll L2_SR for completion */
 
-	mtdcr( l2_cache_cmd, 0x10000000 );	/* clear cache errors L2_CMD[CCP] */
+	mtdcr( L2_CACHE_CMD, 0x10000000 );	/* clear cache errors L2_CMD[CCP] */
 
-	mtdcr( l2_cache_cmd, 0x08000000 );	/* clear tag errors L2_CMD[CTE] */
+	mtdcr( L2_CACHE_CMD, 0x08000000 );	/* clear tag errors L2_CMD[CTE] */
 
-	mtdcr( l2_cache_snp0, 0 );		/* snoop registers */
+	mtdcr( L2_CACHE_SNP0, 0 );		/* snoop registers */
-	mtdcr( l2_cache_snp1, 0 );
+	mtdcr( L2_CACHE_SNP1, 0 );
 
 	__asm__ volatile ("sync");		/* msync */
 
-	mtdcr( l2_cache_cfg, 0xe0000000 );	/* inst and data use L2 */
+	mtdcr( L2_CACHE_CFG, 0xe0000000 );	/* inst and data use L2 */
 
 	__asm__ volatile ("sync");
 }
@@ -294,7 +295,7 @@ static void l2cache_enable(void)	/* see p258 7.4.1 Enabling L2 Cache */
  ************************************************************************/
 static int l2cache_status(void)
 {
-	return  (mfdcr( l2_cache_cfg ) & 0x60000000) != 0;
+	return  (mfdcr( L2_CACHE_CFG ) & 0x60000000) != 0;
 }
 
 

board/apollon/Makefile

@@ -25,9 +25,10 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= apollon.o mem.o sys_info.o
+COBJS-y	:= apollon.o mem.o sys_info.o
 SOBJS	:= lowlevel_init.o
 
+COBJS	:= $(COBJS-y)
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))

board/atmel/at91cap9adk/at91cap9adk.c

@@ -342,7 +342,7 @@ void lcd_show_board_info(void)
 	lcd_printf ("at91support@atmel.com\n");
 	lcd_printf ("%s CPU at %s MHz\n",
 		AT91_CPU_NAME,
-		strmhz(temp, AT91_MAIN_CLOCK));
+		strmhz(temp, AT91_CPU_CLOCK));
 
 	dram_size = 0;
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)

board/atmel/at91sam9261ek/at91sam9261ek.c

@@ -225,7 +225,7 @@ void lcd_show_board_info(void)
 	lcd_printf ("at91support@atmel.com\n");
 	lcd_printf ("%s CPU at %s MHz\n",
 		AT91_CPU_NAME,
-		strmhz(temp, AT91_MAIN_CLOCK));
+		strmhz(temp, AT91_CPU_CLOCK));
 
 	dram_size = 0;
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)

board/atmel/at91sam9263ek/at91sam9263ek.c

@@ -276,7 +276,7 @@ void lcd_show_board_info(void)
 	lcd_printf ("at91support@atmel.com\n");
 	lcd_printf ("%s CPU at %s MHz\n",
 		AT91_CPU_NAME,
-		strmhz(temp, AT91_MAIN_CLOCK));
+		strmhz(temp, AT91_CPU_CLOCK));
 
 	dram_size = 0;
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)

board/atmel/at91sam9rlek/at91sam9rlek.c

@@ -197,7 +197,7 @@ void lcd_show_board_info(void)
 	lcd_printf ("at91support@atmel.com\n");
 	lcd_printf ("%s CPU at %s MHz\n",
 		AT91_CPU_NAME,
-		strmhz(temp, AT91_MAIN_CLOCK));
+		strmhz(temp, AT91_CPU_CLOCK));
 
 	dram_size = 0;
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)

board/atum8548/atum8548.c

@@ -37,10 +37,6 @@
 #include <libfdt.h>
 #include <fdt_support.h>
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
 long int fixed_sdram(void);
 
 int board_early_init_f (void)
@@ -117,12 +113,6 @@ initdram(int board_type)
 	dram_size = fixed_sdram ();
 #endif
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-	/*
-	 * Initialize and enable DDR ECC.
-	 */
-	ddr_enable_ecc(dram_size);
-#endif
 	puts("    DDR: ");
 	return dram_size;
 }

board/bf533-ezkit/Makefile

@@ -35,12 +35,11 @@ SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS) u-boot.lds
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds
 	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
 
-u-boot.lds: u-boot.lds.S
+$(obj)u-boot.lds: u-boot.lds.S
-	$(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P -Ubfin $^ > $@.tmp
+	$(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@
-	mv -f $@.tmp $@
 
 clean:
 	rm -f $(SOBJS) $(OBJS)

board/bf533-ezkit/config.mk

@@ -1,4 +1,6 @@
 #
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
 # (C) Copyright 2001
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
@@ -23,3 +25,9 @@
 
 # This is not actually used for Blackfin boards so do not change it
 #TEXT_BASE = do-not-use-me
+
+LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))

board/bf533-ezkit/u-boot.lds.S

@@ -28,6 +28,8 @@
 #include <config.h>
 #include <asm/blackfin.h>
 #undef ALIGN
+#undef ENTRY
+#undef bfin
 
 /* If we don't actually load anything into L1 data, this will avoid
  * a syntax error.  If we do actually load something into L1 data,
@@ -50,11 +52,12 @@ MEMORY
 	l1_data : ORIGIN = L1_DATA_B_SRAM,   LENGTH = L1_DATA_B_SRAM_SIZE
 }
 
+ENTRY(_start)
 SECTIONS
 {
 	.text :
 	{
-		cpu/blackfin/start.o (.text)
+		cpu/blackfin/start.o (.text .text.*)
 
 #ifdef ENV_IS_EMBEDDED
 		/* WARNING - the following is hand-optimized to fit within
@@ -63,20 +66,20 @@ SECTIONS
 		 * it linked after the configuration sector.
 		 */
 
-		cpu/blackfin/traps.o		(.text)
+		cpu/blackfin/traps.o		(.text .text.*)
-		cpu/blackfin/interrupt.o	(.text)
+		cpu/blackfin/interrupt.o	(.text .text.*)
-		cpu/blackfin/serial.o		(.text)
+		cpu/blackfin/serial.o		(.text .text.*)
-		common/dlmalloc.o		(.text)
+		common/dlmalloc.o		(.text .text.*)
-		lib_generic/crc32.o		(.text)
+		lib_generic/crc32.o		(.text .text.*)
-		lib_generic/zlib.o		(.text)
+		lib_generic/zlib.o		(.text .text.*)
-		board/bf533-ezkit/bf533-ezkit.o		(.text)
+		board/bf533-ezkit/bf533-ezkit.o		(.text .text.*)
 
 		. = DEFINED(env_offset) ? env_offset : .;
-		common/env_embedded.o	(.text)
+		common/env_embedded.o	(.text .text.*)
 #endif
 
 		__initcode_start = .;
-		cpu/blackfin/initcode.o (.text)
+		cpu/blackfin/initcode.o (.text .text.*)
 		__initcode_end = .;
 
 		*(.text .text.*)

board/bf533-stamp/Makefile

@@ -35,12 +35,11 @@ SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS) u-boot.lds
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds
 	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
 
-u-boot.lds: u-boot.lds.S
+$(obj)u-boot.lds: u-boot.lds.S
-	$(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P -Ubfin $^ > $@.tmp
+	$(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@
-	mv -f $@.tmp $@
 
 clean:
 	rm -f $(SOBJS) $(OBJS)

board/bf533-stamp/config.mk

@@ -1,4 +1,6 @@
 #
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
 # (C) Copyright 2001
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
@@ -23,3 +25,9 @@
 
 # This is not actually used for Blackfin boards so do not change it
 #TEXT_BASE = do-not-use-me
+
+LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))

board/bf533-stamp/u-boot.lds.S

@@ -28,6 +28,8 @@
 #include <config.h>
 #include <asm/blackfin.h>
 #undef ALIGN
+#undef ENTRY
+#undef bfin
 
 /* If we don't actually load anything into L1 data, this will avoid
  * a syntax error.  If we do actually load something into L1 data,
@@ -50,11 +52,12 @@ MEMORY
 	l1_data : ORIGIN = L1_DATA_B_SRAM,   LENGTH = L1_DATA_B_SRAM_SIZE
 }
 
+ENTRY(_start)
 SECTIONS
 {
 	.text :
 	{
-		cpu/blackfin/start.o (.text)
+		cpu/blackfin/start.o (.text .text.*)
 
 #ifdef ENV_IS_EMBEDDED
 		/* WARNING - the following is hand-optimized to fit within
@@ -63,18 +66,18 @@ SECTIONS
 		 * it linked after the configuration sector.
 		 */
 
-		cpu/blackfin/traps.o		(.text)
+		cpu/blackfin/traps.o		(.text .text.*)
-		cpu/blackfin/interrupt.o	(.text)
+		cpu/blackfin/interrupt.o	(.text .text.*)
-		cpu/blackfin/serial.o		(.text)
+		cpu/blackfin/serial.o		(.text .text.*)
-		common/dlmalloc.o		(.text)
+		common/dlmalloc.o		(.text .text.*)
-		lib_generic/crc32.o		(.text)
+		lib_generic/crc32.o		(.text .text.*)
 
 		. = DEFINED(env_offset) ? env_offset : .;
-		common/env_embedded.o	(.text)
+		common/env_embedded.o	(.text .text.*)
 #endif
 
 		__initcode_start = .;
-		cpu/blackfin/initcode.o (.text)
+		cpu/blackfin/initcode.o (.text .text.*)
 		__initcode_end = .;
 
 		*(.text .text.*)

board/bf537-stamp/Makefile

@@ -35,12 +35,11 @@ SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS) u-boot.lds
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds
 	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
 
-u-boot.lds: u-boot.lds.S
+$(obj)u-boot.lds: u-boot.lds.S
-	$(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P -Ubfin $^ > $@.tmp
+	$(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@
-	mv -f $@.tmp $@
 
 clean:
 	rm -f $(SOBJS) $(OBJS)

board/bf537-stamp/config.mk

@@ -1,4 +1,6 @@
 #
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
 # (C) Copyright 2001
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
@@ -24,6 +26,9 @@
 # This is not actually used for Blackfin boards so do not change it
 #TEXT_BASE = do-not-use-me
 
+LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds
+
 # Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_UART       := --port g --gpio 6
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
+LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6
 LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))

board/bf537-stamp/nand.c

@@ -87,7 +87,7 @@ int bfin_device_ready(struct mtd_info *mtd)
  * Members with a "?" were not set in the merged testing-NAND branch,
  * so they are not set here either.
  */
-void board_nand_init(struct nand_chip *nand)
+int board_nand_init(struct nand_chip *nand)
 {
 	*PORT(CONFIG_NAND_GPIO_PORT, _FER) &= ~BFIN_NAND_READY;
 	*PORT(CONFIG_NAND_GPIO_PORT, IO_DIR) &= ~BFIN_NAND_READY;
@@ -97,5 +97,7 @@ void board_nand_init(struct nand_chip *nand)
 	nand->ecc.mode = NAND_ECC_SOFT;
 	nand->dev_ready = bfin_device_ready;
 	nand->chip_delay = 30;
+
+	return 0;
 }
 #endif

board/bf537-stamp/u-boot.lds.S

@@ -28,6 +28,8 @@
 #include <config.h>
 #include <asm/blackfin.h>
 #undef ALIGN
+#undef ENTRY
+#undef bfin
 
 /* If we don't actually load anything into L1 data, this will avoid
  * a syntax error.  If we do actually load something into L1 data,
@@ -50,11 +52,12 @@ MEMORY
 	l1_data : ORIGIN = L1_DATA_B_SRAM,   LENGTH = L1_DATA_B_SRAM_SIZE
 }
 
+ENTRY(_start)
 SECTIONS
 {
 	.text :
 	{
-		cpu/blackfin/start.o (.text)
+		cpu/blackfin/start.o (.text .text.*)
 
 #ifdef ENV_IS_EMBEDDED
 		/* WARNING - the following is hand-optimized to fit within
@@ -63,18 +66,18 @@ SECTIONS
 		 * it linked after the configuration sector.
 		 */
 
-		cpu/blackfin/traps.o		(.text)
+		cpu/blackfin/traps.o		(.text .text.*)
-		cpu/blackfin/interrupt.o	(.text)
+		cpu/blackfin/interrupt.o	(.text .text.*)
-		cpu/blackfin/serial.o		(.text)
+		cpu/blackfin/serial.o		(.text .text.*)
-		common/dlmalloc.o		(.text)
+		common/dlmalloc.o		(.text .text.*)
-		lib_generic/crc32.o		(.text)
+		lib_generic/crc32.o		(.text .text.*)
 
 		. = DEFINED(env_offset) ? env_offset : .;
-		common/env_embedded.o	(.text)
+		common/env_embedded.o	(.text .text.*)
 #endif
 
 		__initcode_start = .;
-		cpu/blackfin/initcode.o (.text)
+		cpu/blackfin/initcode.o (.text .text.*)
 		__initcode_end = .;
 
 		*(.text .text.*)

board/bf561-ezkit/Makefile

@@ -35,12 +35,11 @@ SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS) u-boot.lds
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds
 	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
 
-u-boot.lds: u-boot.lds.S
+$(obj)u-boot.lds: u-boot.lds.S
-	$(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P -Ubfin $^ > $@.tmp
+	$(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@
-	mv -f $@.tmp $@
 
 clean:
 	rm -f $(SOBJS) $(OBJS)

board/bf561-ezkit/config.mk

@@ -1,4 +1,6 @@
 #
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
 # (C) Copyright 2001
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
@@ -23,3 +25,9 @@
 
 # This is not actually used for Blackfin boards so do not change it
 #TEXT_BASE = do-not-use-me
+
+LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))

board/bf561-ezkit/u-boot.lds.S

@@ -28,6 +28,8 @@
 #include <config.h>
 #include <asm/blackfin.h>
 #undef ALIGN
+#undef ENTRY
+#undef bfin
 
 /* If we don't actually load anything into L1 data, this will avoid
  * a syntax error.  If we do actually load something into L1 data,
@@ -50,11 +52,12 @@ MEMORY
 	l1_data : ORIGIN = L1_DATA_B_SRAM,   LENGTH = L1_DATA_B_SRAM_SIZE
 }
 
+ENTRY(_start)
 SECTIONS
 {
 	.text :
 	{
-		cpu/blackfin/start.o (.text)
+		cpu/blackfin/start.o (.text .text.*)
 
 #ifdef ENV_IS_EMBEDDED
 		/* WARNING - the following is hand-optimized to fit within
@@ -63,20 +66,20 @@ SECTIONS
 		 * it linked after the configuration sector.
 		 */
 
-		cpu/blackfin/traps.o		(.text)
+		cpu/blackfin/traps.o		(.text .text.*)
-		cpu/blackfin/interrupt.o	(.text)
+		cpu/blackfin/interrupt.o	(.text .text.*)
-		cpu/blackfin/serial.o		(.text)
+		cpu/blackfin/serial.o		(.text .text.*)
-		common/dlmalloc.o		(.text)
+		common/dlmalloc.o		(.text .text.*)
-		lib_generic/crc32.o		(.text)
+		lib_generic/crc32.o		(.text .text.*)
-		lib_generic/zlib.o		(.text)
+		lib_generic/zlib.o		(.text .text.*)
-		board/bf561-ezkit/bf561-ezkit.o		(.text)
+		board/bf561-ezkit/bf561-ezkit.o		(.text .text.*)
 
 		. = DEFINED(env_offset) ? env_offset : .;
-		common/env_embedded.o	(.text)
+		common/env_embedded.o	(.text .text.*)
 #endif
 
 		__initcode_start = .;
-		cpu/blackfin/initcode.o (.text)
+		cpu/blackfin/initcode.o (.text .text.*)
 		__initcode_end = .;
 
 		*(.text .text.*)

board/bmw/bmw.c

@@ -28,7 +28,7 @@
 #include <malloc.h>
 #include <devices.h>
 #include <net.h>
-#include <version.h>
+#include <timestamp.h>
 #include <dtt.h>
 #include <mpc824x.h>
 #include <asm/processor.h>
@@ -45,7 +45,7 @@ int checkboard(void)
     char  buf[32];
 
     puts ("Board: BMW MPC8245/KAHLUA2 - CHRP (MAP B)\n");
-    printf("Built: %s at %s\n", __DATE__ , __TIME__ );
+    printf("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME);
     /* printf("MPLD:  Revision %d\n", SYS_REVID_GET()); */
     printf("Local Bus at %s MHz\n", strmhz(buf, busfreq));
     return 0;

board/eXalion/eXalion.c

@@ -31,6 +31,7 @@
 #include <pci.h>
 #include <ide.h>
 #include <netdev.h>
+#include <timestamp.h>
 #include "piix_pci.h"
 #include "eXalion.h"
 
@@ -40,7 +41,7 @@ int checkboard (void)
 	char buf[32];
 
 	printf ("Board: eXalion MPC824x - CHRP (MAP B)\n");
-	printf ("Built: %s at %s\n", __DATE__, __TIME__);
+	printf ("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME);
 	printf ("Local Bus:  %s MHz\n", strmhz (buf, busfreq));
 
 	return 0;

board/esd/cpci405/Makefile

@@ -29,6 +29,7 @@ endif
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	= $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o
+COBJS	+= ../common/cmd_loadpci.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))

board/esd/cpci405/config.mk

@@ -21,8 +21,4 @@
 # MA 02111-1307 USA
 #
 
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+TEXT_BASE = 0xFFFC0000
-
-ifndef TEXT_BASE
-TEXT_BASE = 0xFFFD0000
-endif

board/esd/cpci405/cpci405.c

@@ -20,8 +20,9 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
-
 #include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
 #include <asm/processor.h>
 #include <asm/io.h>
 #include <command.h>
@@ -31,16 +32,16 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);	/*cmd_boot.c*/
+extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
-#if 0
+extern void __ft_board_setup(void *blob, bd_t *bd);
-#define FPGA_DEBUG
+
-#endif
+#undef FPGA_DEBUG
 
 /* fpga configuration data - generated by bin2cc */
 const unsigned char fpgadata[] =
 {
-#ifdef CONFIG_CPCI405_VER2
+#if defined(CONFIG_CPCI405_VER2)
-# ifdef CONFIG_CPCI405AB
+# if defined(CONFIG_CPCI405AB)
 #  include "fpgadata_cpci405ab.c"
 # else
 #  include "fpgadata_cpci4052.c"
@@ -56,7 +57,7 @@ const unsigned char fpgadata[] =
 #include "../common/fpga.c"
 #include "../common/auto_update.h"
 
-#ifdef CONFIG_CPCI405AB
+#if defined(CONFIG_CPCI405AB)
 au_image_t au_image[] = {
 	{"cpci405ab/preinst.img", 0, -1, AU_SCRIPT},
 	{"cpci405ab/pImage", 0xffc00000, 0x000c0000, AU_NOR},
@@ -65,7 +66,7 @@ au_image_t au_image[] = {
 	{"cpci405ab/postinst.img", 0, 0, AU_SCRIPT},
 };
 #else
-#ifdef CONFIG_CPCI405_VER2
+#if defined(CONFIG_CPCI405_VER2)
 au_image_t au_image[] = {
 	{"cpci4052/preinst.img", 0, -1, AU_SCRIPT},
 	{"cpci4052/pImage", 0xffc00000, 0x000c0000, AU_NOR},
@@ -91,7 +92,7 @@ int cpci405_version(void);
 int gunzip(void *, int, unsigned char *, unsigned long *);
 void lxt971_no_sleep(void);
 
-int board_early_init_f (void)
+int board_early_init_f(void)
 {
 #ifndef CONFIG_CPCI405_VER2
 	int index, len, i;
@@ -100,18 +101,19 @@ int board_early_init_f (void)
 
 #ifdef FPGA_DEBUG
 	/* set up serial port with default baudrate */
-	(void) get_clocks ();
+	(void)get_clocks();
 	gd->baudrate = CONFIG_BAUDRATE;
-	serial_init ();
+	serial_init();
 	console_init_f();
 #endif
 
 	/*
-	 * First pull fpga-prg pin low, to disable fpga logic (on version 2 board)
+	 * First pull fpga-prg pin low,
+	 * to disable fpga logic (on version 2 board)
 	 */
 	out32(GPIO0_ODR, 0x00000000);	     /* no open drain pins	*/
-	out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG);      /* setup for output	*/
+	out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output	*/
-	out32(GPIO0_OR,  CONFIG_SYS_FPGA_PRG);      /* set output pins to high */
+	out32(GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
 	out32(GPIO0_OR, 0);		     /* pull prg low		*/
 
 	/*
@@ -124,39 +126,42 @@ int board_early_init_f (void)
 			/* booting FPGA failed */
 #ifndef FPGA_DEBUG
 			/* set up serial port with default baudrate */
-			(void) get_clocks ();
+			(void)get_clocks();
 			gd->baudrate = CONFIG_BAUDRATE;
-			serial_init ();
+			serial_init();
 			console_init_f();
 #endif
 			printf("\nFPGA: Booting failed ");
 			switch (status) {
 			case ERROR_FPGA_PRG_INIT_LOW:
-				printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+				printf("(Timeout: INIT not low after "
+				       "asserting PROGRAM*)\n ");
 				break;
 			case ERROR_FPGA_PRG_INIT_HIGH:
-				printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+				printf("(Timeout: INIT not high after "
+				       "deasserting PROGRAM*)\n ");
 				break;
 			case ERROR_FPGA_PRG_DONE:
-				printf("(Timeout: DONE not high after programming FPGA)\n ");
+				printf("(Timeout: DONE not high after "
+				       "programming FPGA)\n ");
 				break;
 			}
 
 			/* display infos on fpgaimage */
 			index = 15;
-			for (i=0; i<4; i++) {
+			for (i = 0; i < 4; i++) {
 				len = fpgadata[index];
-				printf("FPGA: %s\n", &(fpgadata[index+1]));
+				printf("FPGA: %s\n", &(fpgadata[index + 1]));
-				index += len+3;
+				index += len + 3;
 			}
-			putc ('\n');
+			putc('\n');
 			/* delayed reboot */
-			for (i=20; i>0; i--) {
+			for (i = 20; i > 0; i--) {
 				printf("Rebooting in %2d seconds \r",i);
-				for (index=0;index<1000;index++)
+				for (index = 0; index < 1000; index++)
 					udelay(1000);
 			}
-			putc ('\n');
+			putc('\n');
 			do_reset(NULL, 0, 0, NULL);
 		}
 	}
@@ -167,7 +172,7 @@ int board_early_init_f (void)
 	 * IRQ 16    405GP internally generated; active low; level sensitive
 	 * IRQ 17-24 RESERVED
 	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
-	 * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052) ; active low; level sensitive
+	 * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052); active low; level sens.
 	 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
 	 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
 	 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
@@ -177,7 +182,7 @@ int board_early_init_f (void)
 	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
 	mtdcr(uicer, 0x00000000);	/* disable all ints */
 	mtdcr(uiccr, 0x00000000);	/* set all to be non-critical*/
-#ifdef CONFIG_CPCI405_6U
+#if defined(CONFIG_CPCI405_6U)
 	if (cpci405_version() == 3) {
 		mtdcr(uicpr, 0xFFFFFF99);	/* set int polarities */
 	} else {
@@ -187,21 +192,20 @@ int board_early_init_f (void)
 	mtdcr(uicpr, 0xFFFFFF81);	/* set int polarities */
 #endif
 	mtdcr(uictr, 0x10000000);	/* set int trigger levels */
-	mtdcr(uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority*/
+	mtdcr(uicvcr, 0x00000001);	/* set vect base=0,
+					 * INT0 highest priority */
 	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
 
 	return 0;
 }
 
-/* ------------------------------------------------------------------------- */
-
 int ctermm2(void)
 {
-#ifdef CONFIG_CPCI405_VER2
+#if defined(CONFIG_CPCI405_VER2)
 	return 0;			/* no, board is cpci405 */
 #else
-	if ((*(unsigned char *)0xf0000400 == 0x00) &&
+	if ((in_8((void*)0xf0000400) == 0x00) &&
-	    (*(unsigned char *)0xf0000401 == 0x01))
+	    (in_8((void*)0xf0000401) == 0x01))
 		return 0;		/* no, board is cpci405 */
 	else
 		return -1;		/* yes, board is cterm-m2 */
@@ -228,8 +232,8 @@ int cpci405_version(void)
 	mtdcr(cntrl0, cntrl0Reg | 0x03000000);
 	out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000);
 	out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000);
-	udelay(1000);			/* wait some time before reading input */
+	udelay(1000); /* wait some time before reading input */
-	value = in_be32((void*)GPIO0_IR) & 0x00180000;	     /* get config bits */
+	value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */
 
 	/*
 	 * Restore GPIO settings
@@ -263,7 +267,7 @@ int misc_init_r (void)
 	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 	gd->bd->bi_flashoffset = 0;
 
-#ifdef CONFIG_CPCI405_VER2
+#if defined(CONFIG_CPCI405_VER2)
 	{
 	unsigned char *dst;
 	ulong len = sizeof(fpgadata);
@@ -283,9 +287,10 @@ int misc_init_r (void)
 		mtdcr(cntrl0, cntrl0Reg | 0x00300000);
 
 		dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
-		if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+		if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
-			printf ("GUNZIP ERROR - must RESET board to recover\n");
+			   (uchar *)fpgadata, &len) != 0) {
-			do_reset (NULL, 0, 0, NULL);
+			printf("GUNZIP ERROR - must RESET board to recover\n");
+			do_reset(NULL, 0, 0, NULL);
 		}
 
 		status = fpga_boot(dst, len);
@@ -293,31 +298,34 @@ int misc_init_r (void)
 			printf("\nFPGA: Booting failed ");
 			switch (status) {
 			case ERROR_FPGA_PRG_INIT_LOW:
-				printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+				printf("(Timeout: INIT not low after "
+				       "asserting PROGRAM*)\n ");
 				break;
 			case ERROR_FPGA_PRG_INIT_HIGH:
-				printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+				printf("(Timeout: INIT not high after "
+				       "deasserting PROGRAM*)\n ");
 				break;
 			case ERROR_FPGA_PRG_DONE:
-				printf("(Timeout: DONE not high after programming FPGA)\n ");
+				printf("(Timeout: DONE not high after "
+				       "programming FPGA)\n ");
 				break;
 			}
 
 			/* display infos on fpgaimage */
 			index = 15;
-			for (i=0; i<4; i++) {
+			for (i = 0; i < 4; i++) {
 				len = dst[index];
-				printf("FPGA: %s\n", &(dst[index+1]));
+				printf("FPGA: %s\n", &(dst[index + 1]));
-				index += len+3;
+				index += len + 3;
 			}
-			putc ('\n');
+			putc('\n');
 			/* delayed reboot */
-			for (i=20; i>0; i--) {
+			for (i = 20; i > 0; i--) {
-				printf("Rebooting in %2d seconds \r",i);
+				printf("Rebooting in %2d seconds \r", i);
-				for (index=0;index<1000;index++)
+				for (index = 0; index < 1000; index++)
 					udelay(1000);
 			}
-			putc ('\n');
+			putc('\n');
 			do_reset(NULL, 0, 0, NULL);
 		}
 
@@ -328,12 +336,12 @@ int misc_init_r (void)
 
 		/* display infos on fpgaimage */
 		index = 15;
-		for (i=0; i<4; i++) {
+		for (i = 0; i < 4; i++) {
 			len = dst[index];
-			printf("%s ", &(dst[index+1]));
+			printf("%s ", &(dst[index + 1]));
-			index += len+3;
+			index += len + 3;
 		}
-		putc ('\n');
+		putc('\n');
 
 		free(dst);
 
@@ -345,68 +353,48 @@ int misc_init_r (void)
 		SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
 		udelay(1000); /* wait 1ms */
 
-#ifdef CONFIG_CPCI405_6U
+#if defined(CONFIG_CPCI405_6U)
+#error HIER GETH ES WEITER MIT IO ACCESSORS
 		if (cpci405_version() == 3) {
-			volatile unsigned short *fpga_mode = (unsigned short *)CONFIG_SYS_FPGA_BASE_ADDR;
-			volatile unsigned char *leds = (unsigned char *)CONFIG_SYS_LED_ADDR;
-
 			/*
 			 * Enable outputs in fpga on version 3 board
 			 */
-			*fpga_mode |= CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT;
+			out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
+				 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
+				 CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT);
 
 			/*
 			 * Set outputs to 0
 			 */
-			*leds = 0x00;
+			out_8((void*)CONFIG_SYS_LED_ADDR, 0x00);
 
 			/*
 			 * Reset external DUART
 			 */
-			*fpga_mode |= CONFIG_SYS_FPGA_MODE_DUART_RESET;
+			out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
+				 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
+				 CONFIG_SYS_FPGA_MODE_DUART_RESET);
 			udelay(100);
-			*fpga_mode &= ~(CONFIG_SYS_FPGA_MODE_DUART_RESET);
+			out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
+				 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) &
+				 ~CONFIG_SYS_FPGA_MODE_DUART_RESET);
 		}
 #endif
 	}
 	else {
 		puts("\n*** U-Boot Version does not match Board Version!\n");
 		puts("*** CPCI-405 Version 1.x detected!\n");
-		puts("*** Please use correct U-Boot version (CPCI405 instead of CPCI4052)!\n\n");
+		puts("*** Please use correct U-Boot version "
+		     "(CPCI405 instead of CPCI4052)!\n\n");
 	}
 	}
-
 #else /* CONFIG_CPCI405_VER2 */
-
-#if 0 /* test-only: code-plug now not relavant for ip-address any more */
-	/*
-	 * Generate last byte of ip-addr from code-plug @ 0xf0000400
-	 */
-	if (ctermm2()) {
-		char str[32];
-		unsigned char ipbyte = *(unsigned char *)0xf0000400;
-
-		/*
-		 * Only overwrite ip-addr with allowed values
-		 */
-		if ((ipbyte != 0x00) && (ipbyte != 0xff)) {
-			bd->bi_ip_addr = (bd->bi_ip_addr & 0xffffff00) | ipbyte;
-			sprintf(str, "%ld.%ld.%ld.%ld",
-				(bd->bi_ip_addr & 0xff000000) >> 24,
-				(bd->bi_ip_addr & 0x00ff0000) >> 16,
-				(bd->bi_ip_addr & 0x0000ff00) >> 8,
-				(bd->bi_ip_addr & 0x000000ff));
-			setenv("ipaddr", str);
-		}
-	}
-#endif
-
 	if (cpci405_version() >= 2) {
 		puts("\n*** U-Boot Version does not match Board Version!\n");
 		puts("*** CPCI-405 Board Version 2.x detected!\n");
-		puts("*** Please use correct U-Boot version (CPCI4052 instead of CPCI405)!\n\n");
+		puts("*** Please use correct U-Boot version "
+		     "(CPCI4052 instead of CPCI405)!\n\n");
 	}
-
 #endif /* CONFIG_CPCI405_VER2 */
 
 	/*
@@ -415,46 +403,33 @@ int misc_init_r (void)
 	cntrl0Reg = mfdcr(cntrl0);
 	mtdcr(cntrl0, cntrl0Reg | 0x00001000);
 
-	return (0);
+	return 0;
 }
 
 /*
  * Check Board Identity:
  */
 
-int checkboard (void)
+int checkboard(void)
 {
 #ifndef CONFIG_CPCI405_VER2
 	int index;
 	int len;
 #endif
 	char str[64];
-	int i = getenv_r ("serial#", str, sizeof(str));
+	int i = getenv_r("serial#", str, sizeof(str));
 	unsigned short ver;
 
-	puts ("Board: ");
+	puts("Board: ");
 
-	if (i == -1) {
+	if (i == -1)
-		puts ("### No HW ID - assuming CPCI405");
+		puts("### No HW ID - assuming CPCI405");
-	} else {
+	else
 		puts(str);
-	}
 
 	ver = cpci405_version();
 	printf(" (Ver %d.x, ", ver);
 
-#if 0 /* test-only */
-	if (ver >= 2) {
-		volatile u16 *fpga_status = (u16 *)CONFIG_SYS_FPGA_BASE_ADDR + 1;
-
-		if (*fpga_status & CONFIG_SYS_FPGA_STATUS_FLASH) {
-			puts ("FLASH Bank B, ");
-		} else {
-			puts ("FLASH Bank A, ");
-		}
-	}
-#endif
-
 	if (ctermm2()) {
 		char str[4];
 
@@ -465,32 +440,31 @@ int checkboard (void)
 		setenv("boardid", str);
 		printf("CTERM-M2 - Id=%s)", str);
 	} else {
-		if (cpci405_host()) {
+		if (cpci405_host())
-			puts ("PCI Host Version)");
+			puts("PCI Host Version)");
-		} else {
+		else
-			puts ("PCI Adapter Version)");
+			puts("PCI Adapter Version)");
-		}
 	}
 
 #ifndef CONFIG_CPCI405_VER2
-	puts ("\nFPGA:	");
+	puts("\nFPGA:	");
 
 	/* display infos on fpgaimage */
 	index = 15;
-	for (i=0; i<4; i++) {
+	for (i = 0; i < 4; i++) {
 		len = fpgadata[index];
-		printf("%s ", &(fpgadata[index+1]));
+		printf("%s ", &(fpgadata[index + 1]));
-		index += len+3;
+		index += len + 3;
 	}
 #endif
 
-	putc ('\n');
+	putc('\n');
 	return 0;
 }
 
 void reset_phy(void)
 {
-#ifdef CONFIG_LXT971_NO_SLEEP
+#if defined(CONFIG_LXT971_NO_SLEEP)
 
 	/*
 	 * Disable sleep mode in LXT971
@@ -499,25 +473,24 @@ void reset_phy(void)
 #endif
 }
 
-#ifdef CONFIG_CPCI405_VER2
+#if defined(CONFIG_CPCI405_VER2) && defined (CONFIG_IDE_RESET)
-#ifdef CONFIG_IDE_RESET
-
 void ide_set_reset(int on)
 {
-	volatile unsigned short *fpga_mode = (unsigned short *)CONFIG_SYS_FPGA_BASE_ADDR;
-
 	/*
 	 * Assert or deassert CompactFlash Reset Pin
 	 */
-	if (on) {		/* assert RESET */
+	if (on) {	/* assert RESET */
-		*fpga_mode &= ~(CONFIG_SYS_FPGA_MODE_CF_RESET);
+		out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
-	} else {		/* release RESET */
+			 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) &
-		*fpga_mode |= CONFIG_SYS_FPGA_MODE_CF_RESET;
+			 ~CONFIG_SYS_FPGA_MODE_CF_RESET);
+	} else {	/* release RESET */
+		out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
+			 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
+			 CONFIG_SYS_FPGA_MODE_CF_RESET);
 	}
 }
 
-#endif /* CONFIG_IDE_RESET */
+#endif /* CONFIG_IDE_RESET && CONFIG_CPCI405_VER2 */
-#endif /* CONFIG_CPCI405_VER2 */
 
 #if defined(CONFIG_PCI)
 void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
@@ -552,15 +525,44 @@ int pci_pre_init(struct pci_controller *hose)
 }
 #endif /* defined(CONFIG_PCI) */
 
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	int rc;
 
-#ifdef CONFIG_CPCI405AB
+	__ft_board_setup(blob, bd);
 
-#define ONE_WIRE_CLEAR	 (*(volatile unsigned short *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_MODE) \
+	/*
-			  |= CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
+	 * Disable PCI in adapter mode.
-#define ONE_WIRE_SET	 (*(volatile unsigned short *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_MODE) \
+	 */
-			  &= ~CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
+	if (!cpci405_host()) {
-#define ONE_WIRE_GET	 (*(volatile unsigned short *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_STATUS) \
+		rc = fdt_find_and_setprop(blob, "/plb/pci@ec000000", "status",
-			  & CONFIG_SYS_FPGA_MODE_1WIRE)
+					  "disabled", sizeof("disabled"), 1);
+		if (rc) {
+			printf("Unable to update property status in PCI node, "
+			       "err=%s\n",
+			       fdt_strerror(rc));
+		}
+	}
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+#if defined(CONFIG_CPCI405AB)
+#define ONE_WIRE_CLEAR	 out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +	\
+					  CONFIG_SYS_FPGA_MODE),	\
+				  in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
+						  CONFIG_SYS_FPGA_MODE)) | \
+					  CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
+
+#define ONE_WIRE_SET	 out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +	\
+					  CONFIG_SYS_FPGA_MODE),	\
+				  in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
+						  CONFIG_SYS_FPGA_MODE)) & \
+					  ~CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
+
+#define ONE_WIRE_GET	 (in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
+					  CONFIG_SYS_FPGA_STATUS)) &  \
+			  CONFIG_SYS_FPGA_MODE_1WIRE)
 
 /*
  * Generate a 1-wire reset, return 1 if no presence detect was found,
@@ -630,7 +632,7 @@ void OWWriteByte(int data)
 {
 	int loop;
 
-	for (loop=0; loop<8; loop++) {
+	for (loop = 0; loop < 8; loop++) {
 		OWWriteBit(data & 0x01);
 		data >>= 1;
 	}
@@ -640,11 +642,10 @@ int OWReadByte(void)
 {
 	int loop, result = 0;
 
-	for (loop=0; loop<8; loop++) {
+	for (loop = 0; loop < 8; loop++) {
 		result >>= 1;
-		if (OWReadBit()) {
+		if (OWReadBit())
 			result |= 0x80;
-		}
 	}
 
 	return result;
@@ -652,7 +653,7 @@ int OWReadByte(void)
 
 int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-	volatile unsigned short val;
+	unsigned short val;
 	int result;
 	int i;
 	unsigned char ow_id[6];
@@ -662,23 +663,25 @@ int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	/*
 	 * Clear 1-wire bit (open drain with pull-up)
 	 */
-	val = *(volatile unsigned short *)0xf0400000;
+	val = in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +
-	val &= ~0x1000; /* clear 1-wire bit */
+			      CONFIG_SYS_FPGA_MODE));
-	*(volatile unsigned short *)0xf0400000 = val;
+	val &= ~CONFIG_SYS_FPGA_MODE_1WIRE; /* clear 1-wire bit */
+	out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +
+			 CONFIG_SYS_FPGA_MODE), val);
 
 	result = OWTouchReset();
-	if (result != 0) {
+	if (result != 0)
 		puts("No 1-wire device detected!\n");
-	}
 
 	OWWriteByte(0x33); /* send read rom command */
 	OWReadByte(); /* skip family code ( == 0x01) */
-	for (i=0; i<6; i++) {
+	for (i = 0; i < 6; i++)
 		ow_id[i] = OWReadByte();
-	}
 	ow_crc = OWReadByte(); /* read crc */
 
-	sprintf(str, "%08X%04X", *(unsigned int *)&ow_id[0], *(unsigned short *)&ow_id[4]);
+	sprintf(str, "%08X%04X",
+		*(unsigned int *)&ow_id[0],
+		*(unsigned short *)&ow_id[4]);
 	printf("Setting environment variable 'ow_id' to %s\n", str);
 	setenv("ow_id", str);
 
@@ -690,8 +693,8 @@ U_BOOT_CMD(
 	NULL
 	);
 
-#define CONFIG_SYS_I2C_EEPROM_ADDR_2	0x51	/* EEPROM CAT28WC32		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT24WC32 */
-#define CONFIG_ENV_SIZE_2	0x800	/* 2048 bytes may be used for env vars*/
+#define CONFIG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars */
 
 /*
  * Write backplane ip-address...
@@ -706,12 +709,14 @@ int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	IPaddr_t ipaddr;
 
 	buf = malloc(CONFIG_ENV_SIZE_2);
-	if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CONFIG_ENV_SIZE_2)) {
+	if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0,
+			(uchar *)buf, CONFIG_ENV_SIZE_2))
 		puts("\nError reading backplane EEPROM!\n");
-	} else {
+	else {
-		crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2-4);
+		crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4);
 		if (crc != *(ulong *)buf) {
-			printf("ERROR: crc mismatch %08lx %08lx\n", crc, *(ulong *)buf);
+			printf("ERROR: crc mismatch %08lx %08lx\n",
+			       crc, *(ulong *)buf);
 			return -1;
 		}
 
@@ -768,12 +773,12 @@ int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	memset(buf, 0, CONFIG_ENV_SIZE_2);
 	sprintf(str, "bp_ip=%s", argv[1]);
 	strcpy(buf+4, str);
-	crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2-4);
+	crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4);
 	*(ulong *)buf = crc;
 
-	if (eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CONFIG_ENV_SIZE_2)) {
+	if (eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR_2,
+			 0, (uchar *)buf, CONFIG_ENV_SIZE_2))
 		puts("\nError writing backplane EEPROM!\n");
-	}
 
 	free(buf);
 

board/esd/pci405/cmd_pci405.c

@@ -32,13 +32,9 @@
 
 #include "pci405.h"
 
-
 #if defined(CONFIG_CMD_BSP)
 
 extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
-extern int do_bootvx (cmd_tbl_t *, int, int, char *[]);
-unsigned long get_dcr(unsigned short);
-
 
 /*
  * Command loadpci: wait for signal from host and boot image.
@@ -97,33 +93,6 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	} else {
 		sprintf(addr, "%08x", *ptr);
 
-#if 0
-		/*
-		 * Boot image
-		 */
-		if (*ptr & 0x00000001) {
-			/*
-			 * Boot VxWorks image via bootvx
-			 */
-			addr[strlen(addr)-1] = '0';
-			printf("\nBooting VxWorks-Image at addr 0x%s ...\n", addr);
-			setenv("loadaddr", addr);
-
-			local_args[0] = argv[0];
-			local_args[1] = NULL;
-			status = do_bootvx (cmdtp, 0, 1, local_args);
-		} else {
-			/*
-			 * Boot image via bootm (normally Linux)
-			 */
-			printf("\nBooting Image at addr 0x%s ...\n", addr);
-			setenv("loadaddr", addr);
-
-			local_args[0] = argv[0];
-			local_args[1] = NULL;
-			status = do_bootm (cmdtp, 0, 1, local_args);
-		}
-#else
 		/*
 		 * Boot image via bootm
 		 */
@@ -133,7 +102,6 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		local_args[0] = argv[0];
 		local_args[1] = NULL;
 		status = do_bootm (cmdtp, 0, 1, local_args);
-#endif
 	}
 
 	return 0;
@@ -143,843 +111,4 @@ U_BOOT_CMD(
 	"loadpci - Wait for pci-image and boot it\n",
 	NULL
 );
-
-#endif
-
-#if 1 /* test-only */
-int do_getpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
-	unsigned int val;
-	int i;
-
-	printf("\nPCI Configuration Regs for PPC405GP:");
-	for (i=0; i<0x64; i+=4) {
-		pci_read_config_dword(PCIDEVID_405GP, i, &val);
-		if (!(i % 0x10)) {
-			printf("\n%02x: ", i);
-		}
-		printf("%08x ", val);
-	}
-	printf("\n");
-
-	return 0;
-}
-U_BOOT_CMD(
-	getpci,	1,	1,	do_getpci,
-	"getpci  - Print own pci configuration registers\n",
-	NULL
-);
-
-int do_setpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
-	unsigned int addr;
-	unsigned int val;
-
-	addr = simple_strtol (argv[1], NULL, 16);
-	val = simple_strtol (argv[2], NULL, 16);
-
-	printf("\nWriting %08x to PCI reg %08x.\n", val, addr);
-	pci_write_config_dword(PCIDEVID_405GP, addr, val);
-
-	return 0;
-}
-U_BOOT_CMD(
-	setpci,	3,	1,	do_setpci,
-	"setpci  - Set one pci configuration lword\n",
-	"<addr> <val>\n"
-	"        - Write pci configuration lword <val> to <addr>.\n"
-);
-
-int do_dumpdcr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
-	int i;
-
-	printf("\nDevice Configuration Registers (DCR's) for PPC405GP:");
-	for (i=0; i<=0x1e0; i++) {
-		if (!(i % 0x8)) {
-			printf("\n%04x ", i);
-		}
-		printf("%08lx ", get_dcr(i));
-	}
-	printf("\n");
-
-	return 0;
-}
-U_BOOT_CMD(
-	dumpdcr,	1,	1,	do_dumpdcr,
-	"dumpdcr - Dump all DCR registers\n",
-	NULL
-);
-
-
-int do_dumpspr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
-	printf("\nSpecial Purpose Registers (SPR's) for PPC405GP:");
-	printf("\n%04x %08x ", 947, mfspr(947));
-	printf("\n%04x %08x ", 9, mfspr(9));
-	printf("\n%04x %08x ", 1014, mfspr(1014));
-	printf("\n%04x %08x ", 1015, mfspr(1015));
-	printf("\n%04x %08x ", 1010, mfspr(1010));
-	printf("\n%04x %08x ", 957, mfspr(957));
-	printf("\n%04x %08x ", 1008, mfspr(1008));
-	printf("\n%04x %08x ", 1018, mfspr(1018));
-	printf("\n%04x %08x ", 954, mfspr(954));
-	printf("\n%04x %08x ", 950, mfspr(950));
-	printf("\n%04x %08x ", 951, mfspr(951));
-	printf("\n%04x %08x ", 981, mfspr(981));
-	printf("\n%04x %08x ", 980, mfspr(980));
-	printf("\n%04x %08x ", 982, mfspr(982));
-	printf("\n%04x %08x ", 1012, mfspr(1012));
-	printf("\n%04x %08x ", 1013, mfspr(1013));
-	printf("\n%04x %08x ", 948, mfspr(948));
-	printf("\n%04x %08x ", 949, mfspr(949));
-	printf("\n%04x %08x ", 1019, mfspr(1019));
-	printf("\n%04x %08x ", 979, mfspr(979));
-	printf("\n%04x %08x ", 8, mfspr(8));
-	printf("\n%04x %08x ", 945, mfspr(945));
-	printf("\n%04x %08x ", 987, mfspr(987));
-	printf("\n%04x %08x ", 287, mfspr(287));
-	printf("\n%04x %08x ", 953, mfspr(953));
-	printf("\n%04x %08x ", 955, mfspr(955));
-	printf("\n%04x %08x ", 272, mfspr(272));
-	printf("\n%04x %08x ", 273, mfspr(273));
-	printf("\n%04x %08x ", 274, mfspr(274));
-	printf("\n%04x %08x ", 275, mfspr(275));
-	printf("\n%04x %08x ", 260, mfspr(260));
-	printf("\n%04x %08x ", 276, mfspr(276));
-	printf("\n%04x %08x ", 261, mfspr(261));
-	printf("\n%04x %08x ", 277, mfspr(277));
-	printf("\n%04x %08x ", 262, mfspr(262));
-	printf("\n%04x %08x ", 278, mfspr(278));
-	printf("\n%04x %08x ", 263, mfspr(263));
-	printf("\n%04x %08x ", 279, mfspr(279));
-	printf("\n%04x %08x ", 26, mfspr(26));
-	printf("\n%04x %08x ", 27, mfspr(27));
-	printf("\n%04x %08x ", 990, mfspr(990));
-	printf("\n%04x %08x ", 991, mfspr(991));
-	printf("\n%04x %08x ", 956, mfspr(956));
-	printf("\n%04x %08x ", 284, mfspr(284));
-	printf("\n%04x %08x ", 285, mfspr(285));
-	printf("\n%04x %08x ", 986, mfspr(986));
-	printf("\n%04x %08x ", 984, mfspr(984));
-	printf("\n%04x %08x ", 256, mfspr(256));
-	printf("\n%04x %08x ", 1, mfspr(1));
-	printf("\n%04x %08x ", 944, mfspr(944));
-	printf("\n");
-
-	return 0;
-}
-U_BOOT_CMD(
-	dumpspr,	1,	1,	do_dumpspr,
-	"dumpspr - Dump all SPR registers\n",
-	NULL
-);
-
-
-#define PCI0_BRDGOPT1 0x4a
-#define plb0_acr      0x87
-
-int do_getplb(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
-	unsigned short val;
-
-	printf("PLB0_ACR=%08lx\n", get_dcr(0x87));
-	pci_read_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, &val);
-	printf("PCI0_BRDGOPT1=%04x\n", val);
-	printf("CCR0=%08x\n", mfspr(ccr0));
-
-	return 0;
-}
-U_BOOT_CMD(
-	getplb,	1,	1,	do_getplb,
-	"getplb  - Dump all plb arbiter registers\n",
-	NULL
-);
-
-int do_setplb(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
-	unsigned int my_acr;
-	unsigned int my_brdgopt1;
-	unsigned int my_ccr0;
-
-	my_acr = simple_strtol (argv[1], NULL, 16);
-	my_brdgopt1 = simple_strtol (argv[2], NULL, 16);
-	my_ccr0 = simple_strtol (argv[3], NULL, 16);
-
-	mtdcr(plb0_acr, my_acr);
-	pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, my_brdgopt1);
-	mtspr(ccr0, my_ccr0);
-
-	return 0;
-}
-U_BOOT_CMD(
-	setplb,	4,	1,	do_setplb,
-	"setplb  - Set all plb arbiter registers\n",
-	"PLB0_ACR PCI0_BRDGOPT1 CCR0\n"
-	"        - Set all plb arbiter registers\n"
-);
-
-
-/***********************************************************************
- *
- * The following code is only for test purposes!!!!
- * Please ignore this ugly stuff!!!!!!!!!!!!!!!!!!!
- *
- ***********************************************************************/
-
-#define PCI_ADDR 0xc0000000
-
-int do_writepci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
-	unsigned int addr;
-	unsigned int size;
-	unsigned int countmax;
-	int i;
-	int max;
-	volatile unsigned long *ptr;
-	volatile unsigned long val;
-	int loopcount = 0;
-	int test_pci_read = 0;
-	int test_pci_cfg_write = 0;
-	int test_sync = 0;
-	int test_pci_pre_read = 0;
-
-	addr = simple_strtol (argv[1], NULL, 16);
-	size = simple_strtol (argv[2], NULL, 16);
-	countmax = simple_strtol (argv[3], NULL, 16);
-	if (countmax == 0)
-		countmax = 1000;
-
-	do_getplb(NULL, 0, 0, NULL);
-
-#if 0
-	out32r(PMM0LA, 0);
-	out32r(PMM0PCILA, 0);
-	out32r(PMM0PCIHA, 0);
-	out32r(PMM0MA, 0);
-	out32r(PMM1LA, PCI_ADDR);
-	out32r(PMM1PCILA, addr & 0xff000000);
-	out32r(PMM1PCIHA, 0x00000000);
-	out32r(PMM1MA, 0xff000001);
-#endif
-
-	printf("PMM1LA    =%08lx\n", in32r(PMM1LA));
-	printf("PMM1MA    =%08lx\n", in32r(PMM1MA));
-	printf("PMM1PCILA =%08lx\n", in32r(PMM1PCILA));
-	printf("PMM1PCIHA =%08lx\n", in32r(PMM1PCIHA));
-
-	addr = PCI_ADDR | (addr & 0x00ffffff);
-	printf("\nWriting at addr %08x, size %08x (countmax=%x)\n", addr, size, countmax);
-
-	max = size >> 2;
-
-	pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */
-
-	val = *(ulong *)0x00000000;
-	if (val & 0x00000008) {
-		test_pci_pre_read = 1;
-		printf("Running test with pre pci-memory-read access!\n");
-	}
-	if (val & 0x00000004) {
-		test_sync = 1;
-		printf("Running test with sync instruction!\n");
-	}
-	if (val & 0x00000001) {
-		test_pci_read = 1;
-		printf("Running test with pci-memory-read access!\n");
-	}
-	if (val & 0x00000002) {
-		test_pci_cfg_write = 1;
-		printf("Running test with pci-config-write access!\n");
-	}
-
-	while (1) {
-
-		if (test_pci_pre_read) {
-			/*
-			 * Read one value back
-			 */
-			ptr = (volatile unsigned long *)addr;
-			val = *ptr;
-		}
-
-		/*
-		 * Write some values to host via pci busmastering
-		 */
-		ptr = (volatile unsigned long *)addr;
-		for (i=0; i<max; i++) {
-			*ptr++ = i;
-		}
-
-		if (test_sync) {
-			/*
-			 * Sync previous writes
-			 */
-			ppcSync();
-		}
-
-		if (test_pci_read) {
-			/*
-			 * Read one value back
-			 */
-			ptr = (volatile unsigned long *)addr;
-			val = *ptr;
-		}
-
-		if (test_pci_cfg_write) {
-			/*
-			 * Generate IRQ to host via config regs
-			 */
-			pci_write_config_byte(PCIDEVID_405GP, 0x44, 0x00);
-		}
-
-		if (loopcount++ > countmax) {
-			/* Abort if ctrl-c was pressed */
-			if (ctrlc()) {
-				puts("\nAbort\n");
-				return 0;
-			}
-
-			putc('.');
-
-			loopcount = 0;
-		}
-	}
-
-	return 0;
-}
-U_BOOT_CMD(
-	writepci,	4,	1,	do_writepci,
-	"writepci - Write some data to pcibus\n",
-	"<addr> <size>\n"
-	"        - Write some data to pcibus.\n"
-);
-
-#define PCI_CFGADDR        0xeec00000
-#define PCI_CFGDATA        0xeec00004
-
-int ibmPciConfigWrite
-(
-	int offset,     /* offset into the configuration space */
-	int width,      /* data width                          */
-	unsigned int data       /* data to be written                  */
-	)
-{
-	/*
-	 * Write config register address to the PCI config address register
-	 * bit 31 must be 1 and bits 1:0 must be 0 (note LE bit notation)
-	 */
-	out32r(PCI_CFGADDR, 0x80000000 | (offset & 0xFFFFFFFC));
-
-#if 0 /* test-only */
-	ppcSync();
-#endif
-
-	/*
-	 * Write value to be written to the PCI config data register
-	 */
-	switch ( width ) {
-	case 1: out32r(PCI_CFGDATA | (offset & 0x3), (unsigned char)(data & 0xFF));
-		break;
-	case 2: out32r(PCI_CFGDATA | (offset & 0x3), (unsigned short)(data & 0xFFFF));
-		break;
-	case 4:	out32r(PCI_CFGDATA | (offset & 0x3), data);
-		break;
-	}
-
-	return (0);
-}
-
-int do_writepci2(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
-	unsigned int addr;
-	unsigned int size;
-	unsigned int countmax;
-	int max;
-	volatile unsigned long *ptr;
-	volatile unsigned long val;
-	int loopcount = 0;
-
-	addr = simple_strtol (argv[1], NULL, 16);
-	size = simple_strtol (argv[2], NULL, 16);
-	countmax = simple_strtol (argv[3], NULL, 16);
-	if (countmax == 0)
-		countmax = 1000;
-
-	do_getplb(NULL, 0, 0, NULL);
-
-#if 0
-	out32r(PMM0LA, 0);
-	out32r(PMM0PCILA, 0);
-	out32r(PMM0PCIHA, 0);
-	out32r(PMM0MA, 0);
-	out32r(PMM1LA, PCI_ADDR);
-	out32r(PMM1PCILA, addr & 0xff000000);
-	out32r(PMM1PCIHA, 0x00000000);
-	out32r(PMM1MA, 0xff000001);
-#endif
-
-	printf("PMM1LA    =%08lx\n", in32r(PMM1LA));
-	printf("PMM1MA    =%08lx\n", in32r(PMM1MA));
-	printf("PMM1PCILA =%08lx\n", in32r(PMM1PCILA));
-	printf("PMM1PCIHA =%08lx\n", in32r(PMM1PCIHA));
-
-	addr = PCI_ADDR | (addr & 0x00ffffff);
-	printf("\nWriting at addr %08x, size %08x (countmax=%x)\n", addr, size, countmax);
-
-	max = size >> 2;
-
-	pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */
-
-	while (1) {
-
-		/*
-		 * Write one values to host via pci busmastering
-		 */
-		ptr = (volatile unsigned long *)addr;
-		*ptr = 0x01234567;
-
-		/*
-		 * Read one value back
-		 */
-		ptr = (volatile unsigned long *)addr;
-		val = *ptr;
-
-		/*
-		 * One pci config write
-		 */
-/*		pci_write_config_byte(PCIDEVID_405GP, 0x44, 0x00); */
-/*		ibmPciConfigWrite(0x44, 1, 0x00); */
-		ibmPciConfigWrite(0x2e, 2, 0x1234); /* subsystem id */
-
-		if (loopcount++ > countmax) {
-			/* Abort if ctrl-c was pressed */
-			if (ctrlc()) {
-				puts("\nAbort\n");
-				return 0;
-			}
-
-			putc('.');
-
-			loopcount = 0;
-		}
-	}
-
-	return 0;
-}
-U_BOOT_CMD(
-	writepci2,	4,	1,	do_writepci2,
-	"writepci2- Write some data to pcibus\n",
-	"<addr> <size>\n"
-	"        - Write some data to pcibus.\n"
-);
-
-int do_writepci22(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
-	unsigned int addr;
-	unsigned int size;
-	unsigned int countmax = 0;
-	volatile unsigned long *ptr;
-	volatile unsigned long val;
-
-	addr = simple_strtol (argv[1], NULL, 16);
-	size = simple_strtol (argv[2], NULL, 16);
-
-	addr = PCI_ADDR | (addr & 0x00ffffff);
-	printf("\nWriting at addr %08x, size %08x (countmax=%x)\n", addr, size, countmax);
-	pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */
-
-	while (1) {
-
-		/*
-		 * Write one values to host via pci busmastering
-		 */
-		ptr = (volatile unsigned long *)addr;
-		*ptr = 0x01234567;
-
-		/*
-		 * Read one value back
-		 */
-		ptr = (volatile unsigned long *)addr;
-		val = *ptr;
-
-		/*
-		 * One pci config write
-		 */
-		ibmPciConfigWrite(0x2e, 2, 0x1234); /* subsystem id */
-	}
-
-	return 0;
-}
-U_BOOT_CMD(
-	writepci22,	4,	1,	do_writepci22,
-	"writepci22- Write some data to pcibus\n",
-	"<addr> <size>\n"
-	"        - Write some data to pcibus.\n"
-);
-
-int ibmPciConfigWrite3
-(
-	int offset,     /* offset into the configuration space */
-	int width,      /* data width                          */
-	unsigned int data       /* data to be written                  */
-	)
-{
-	/*
-	 * Write config register address to the PCI config address register
-	 * bit 31 must be 1 and bits 1:0 must be 0 (note LE bit notation)
-	 */
-	out32r(PCI_CFGADDR, 0x80000000 | (offset & 0xFFFFFFFC));
-
-#if 1 /* test-only */
-	ppcSync();
-#endif
-
-	/*
-	 * Write value to be written to the PCI config data register
-	 */
-	switch ( width ) {
-	case 1: out32r(PCI_CFGDATA | (offset & 0x3), (unsigned char)(data & 0xFF));
-		break;
-	case 2: out32r(PCI_CFGDATA | (offset & 0x3), (unsigned short)(data & 0xFFFF));
-		break;
-	case 4:	out32r(PCI_CFGDATA | (offset & 0x3), data);
-		break;
-	}
-
-	return (0);
-}
-
-int do_writepci3(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
-	unsigned int addr;
-	unsigned int size;
-	unsigned int countmax;
-	int max;
-	volatile unsigned long *ptr;
-	volatile unsigned long val;
-	int loopcount = 0;
-
-	addr = simple_strtol (argv[1], NULL, 16);
-	size = simple_strtol (argv[2], NULL, 16);
-	countmax = simple_strtol (argv[3], NULL, 16);
-	if (countmax == 0)
-		countmax = 1000;
-
-	do_getplb(NULL, 0, 0, NULL);
-
-#if 0
-	out32r(PMM0LA, 0);
-	out32r(PMM0PCILA, 0);
-	out32r(PMM0PCIHA, 0);
-	out32r(PMM0MA, 0);
-	out32r(PMM1LA, PCI_ADDR);
-	out32r(PMM1PCILA, addr & 0xff000000);
-	out32r(PMM1PCIHA, 0x00000000);
-	out32r(PMM1MA, 0xff000001);
-#endif
-
-	printf("PMM1LA    =%08lx\n", in32r(PMM1LA));
-	printf("PMM1MA    =%08lx\n", in32r(PMM1MA));
-	printf("PMM1PCILA =%08lx\n", in32r(PMM1PCILA));
-	printf("PMM1PCIHA =%08lx\n", in32r(PMM1PCIHA));
-
-	addr = PCI_ADDR | (addr & 0x00ffffff);
-	printf("\nWriting at addr %08x, size %08x (countmax=%x)\n", addr, size, countmax);
-
-	max = size >> 2;
-
-	pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */
-
-	while (1) {
-
-		/*
-		 * Write one values to host via pci busmastering
-		 */
-		ptr = (volatile unsigned long *)addr;
-		*ptr = 0x01234567;
-
-		/*
-		 * Read one value back
-		 */
-		ptr = (volatile unsigned long *)addr;
-		val = *ptr;
-
-		/*
-		 * One pci config write
-		 */
-/*		pci_write_config_byte(PCIDEVID_405GP, 0x44, 0x00); */
-/*		ibmPciConfigWrite(0x44, 1, 0x00); */
-		ibmPciConfigWrite3(0x2e, 2, 0x1234); /* subsystem id */
-
-		if (loopcount++ > countmax) {
-			/* Abort if ctrl-c was pressed */
-			if (ctrlc()) {
-				puts("\nAbort\n");
-				return 0;
-			}
-
-			putc('.');
-
-			loopcount = 0;
-		}
-	}
-
-	return 0;
-}
-U_BOOT_CMD(
-	writepci3,	4,	1,	do_writepci3,
-	"writepci3- Write some data to pcibus\n",
-	"<addr> <size>\n"
-	"        - Write some data to pcibus.\n"
-);
-
-
-#define SECTOR_SIZE	32		/* 32 byte cache line */
-#define SECTOR_MASK	0x1F
-
-void my_flush_dcache(ulong lcl_addr, ulong count)
-{
-  unsigned int lcl_target;
-
-  /* promote to nearest cache sector */
-  lcl_target =  (lcl_addr + count + SECTOR_SIZE - 1) & ~SECTOR_MASK;
-  lcl_addr &= ~SECTOR_MASK;
-  while (lcl_addr != lcl_target)
-    {
-      /*      ppcDcbf((void *)lcl_addr);*/
-      __asm__("dcbf 0,%0": :"r" (lcl_addr));
-      lcl_addr += SECTOR_SIZE;
-    }
-  __asm__("sync");		/* Always flush prefetch queue in any case */
-}
-
-int do_writepci_cache(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
-	unsigned int addr;
-	unsigned int size;
-	unsigned int countmax;
-	int i;
-	volatile unsigned long *ptr;
-	volatile unsigned long val;
-	int loopcount = 0;
-
-	addr = simple_strtol (argv[1], NULL, 16);
-	size = simple_strtol (argv[2], NULL, 16);
-	countmax = simple_strtol (argv[3], NULL, 16);
-	if (countmax == 0)
-		countmax = 1000;
-
-	do_getplb(NULL, 0, 0, NULL);
-
-#if 0
-	out32r(PMM0LA, 0);
-	out32r(PMM0PCILA, 0);
-	out32r(PMM0PCIHA, 0);
-	out32r(PMM0MA, 0);
-	out32r(PMM1LA, PCI_ADDR);
-	out32r(PMM1PCILA, addr & 0xff000000);
-	out32r(PMM1PCIHA, 0x00000000);
-	out32r(PMM1MA, 0xff000001);
-#endif
-
-	printf("PMM1LA    =%08lx\n", in32r(PMM1LA));
-	printf("PMM1MA    =%08lx\n", in32r(PMM1MA));
-	printf("PMM1PCILA =%08lx\n", in32r(PMM1PCILA));
-	printf("PMM1PCIHA =%08lx\n", in32r(PMM1PCIHA));
-
-	addr = PCI_ADDR | (addr & 0x00ffffff);
-	printf("\nWriting at addr %08x, size %08x (countmax=%x)\n", addr, size, countmax);
-
-	pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */
-
-	i = 0;
-
-	/*
-	 * Set pci region as cachable
-	 */
-	ppcSync();
-	__asm__ volatile ("	addis	4,0,0x0000 ");
-	__asm__ volatile ("	addi	4,4,0x0080 ");
-	__asm__ volatile ("	mtdccr	4 ");
-	ppcSync();
-
-	while (1) {
-
-		/*
-		 * Write one values to host via pci busmastering
-		 */
-		ptr = (volatile unsigned long *)addr;
-		printf("A\n"); /* test-only */
-		*ptr++ = i++;
-		*ptr++ = i++;
-		*ptr++ = i++;
-		*ptr++ = i++;
-		*ptr++ = i++;
-		*ptr++ = i++;
-		*ptr++ = i++;
-		*ptr++ = i++;
-		printf("B\n"); /* test-only */
-		my_flush_dcache(addr, 32);
-		printf("C\n"); /* test-only */
-
-		/*
-		 * Read one value back
-		 */
-		ptr = (volatile unsigned long *)addr;
-		val = *ptr;
-		printf("D\n"); /* test-only */
-
-		/*
-		 * One pci config write
-		 */
-/*		pci_write_config_byte(PCIDEVID_405GP, 0x44, 0x00); */
-/*		ibmPciConfigWrite(0x44, 1, 0x00); */
-		ibmPciConfigWrite3(0x2e, 2, 0x1234); /* subsystem id */
-		printf("E\n"); /* test-only */
-
-		if (loopcount++ > countmax) {
-			/* Abort if ctrl-c was pressed */
-			if (ctrlc()) {
-				puts("\nAbort\n");
-				return 0;
-			}
-
-			putc('.');
-
-			loopcount = 0;
-		}
-	}
-
-	return 0;
-}
-U_BOOT_CMD(
-	writepci_cache,	4,	1,	do_writepci_cache,
-	"writepci_cache - Write some data to pcibus\n",
-	"<addr> <size>\n"
-	"        - Write some data to pcibus.\n"
-);
-
-int do_savepci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
-	unsigned int *ptr;
-	int i;
-
-	/*
-	 * Save own pci configuration in PRAM
-	 */
-	memset((char *)PCI_REGS_ADDR, 0, PCI_REGS_LEN);
-	ptr = (unsigned int *)PCI_REGS_ADDR + 1;
-	for (i=0; i<0x40; i+=4) {
-		pci_read_config_dword(PCIDEVID_405GP, i, ptr++);
-	}
-	ptr = (unsigned int *)PCI_REGS_ADDR;
-	*ptr = crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4);
-
-	printf("\nStoring PCI Configuration Regs...\n");
-
-	return 0;
-}
-U_BOOT_CMD(
-	savepci,	4,	1,	do_savepci,
-	"savepci  - Save all pci regs\n",
-	"<addr> <size>\n"
-	"        - Write some data to pcibus.\n"
-);
-
-int do_restorepci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
-	unsigned int *ptr;
-	int i;
-
-	/*
-	 * Rewrite pci config regs (only after soft-reset with magic set)
-	 */
-	ptr = (unsigned int *)PCI_REGS_ADDR;
-	if (crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) {
-		puts("Restoring PCI Configurations Regs!\n");
-		ptr = (unsigned int *)PCI_REGS_ADDR + 1;
-		for (i=0; i<0x40; i+=4) {
-			pci_write_config_dword(PCIDEVID_405GP, i, *ptr++);
-		}
-	}
-	mtdcr(uicsr, 0xFFFFFFFF);        /* clear all ints */
-
-	return 0;
-}
-U_BOOT_CMD(
-	restorepci,	4,	1,	do_restorepci,
-	"restorepci  - Restore all pci regs\n",
-	"<addr> <size>\n"
-	"        - Write some data to pcibus.\n"
-);
-
-
-extern void write_without_sync(void);
-extern void write_with_sync(void);
-extern void write_with_less_sync(void);
-extern void write_with_more_sync(void);
-
-/*
- * code from IBM-PPCSUPP
- */
-int do_writeibm1(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
-	pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */
-
-	write_without_sync();
-
-	return 0;
-}
-U_BOOT_CMD(
-	writeibm1,	4,	1,	do_writeibm1,
-	"writeibm1- Write some data to pcibus (without sync)\n",
-	"<addr> <size>\n"
-	"        - Write some data to pcibus.\n"
-);
-
-int do_writeibm2(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
-	pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */
-
-	write_with_sync();
-
-	return 0;
-}
-U_BOOT_CMD(
-	writeibm2,	4,	1,	do_writeibm2,
-	"writeibm2- Write some data to pcibus (with sync)\n",
-	"<addr> <size>\n"
-	"        - Write some data to pcibus.\n"
-);
-
-int do_writeibm22(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
-	pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */
-
-	write_with_less_sync();
-
-	return 0;
-}
-U_BOOT_CMD(
-	writeibm22,	4,	1,	do_writeibm22,
-	"writeibm22- Write some data to pcibus (with less sync)\n",
-	"<addr> <size>\n"
-	"        - Write some data to pcibus.\n"
-);
-
-int do_writeibm3(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
-	pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */
-
-	write_with_more_sync();
-
-	return 0;
-}
-U_BOOT_CMD(
-	writeibm3,	4,	1,	do_writeibm3,
-	"writeibm3- Write some data to pcibus (with more sync)\n",
-	"<addr> <size>\n"
-	"        - Write some data to pcibus.\n"
-);
 #endif

board/esd/pci405/pci405.c

@@ -27,6 +27,7 @@
 #include <malloc.h>
 #include <pci.h>
 #include <asm/4xx_pci.h>
+#include <asm/io.h>
 
 #include "pci405.h"
 
@@ -34,7 +35,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 /* Prototypes */
 int gunzip(void *, int, unsigned char *, unsigned long *);
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);/*cmd_boot.c*/
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 unsigned long fpga_done_state(void);
 unsigned long fpga_init_state(void);
 
@@ -57,11 +58,11 @@ const unsigned char fpgadata[] =
  */
 #include "../common/fpga.c"
 
-#define FPGA_DONE_STATE_V11 (in32(GPIO0_IR) & CONFIG_SYS_FPGA_DONE)
+#define FPGA_DONE_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE)
-#define FPGA_DONE_STATE_V12 (in32(GPIO0_IR) & CONFIG_SYS_FPGA_DONE_V12)
+#define FPGA_DONE_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE_V12)
 
-#define FPGA_INIT_STATE_V11 (in32(GPIO0_IR) & CONFIG_SYS_FPGA_INIT)
+#define FPGA_INIT_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT)
-#define FPGA_INIT_STATE_V12 (in32(GPIO0_IR) & CONFIG_SYS_FPGA_INIT_V12)
+#define FPGA_INIT_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT_V12)
 
 
 int board_revision(void)
@@ -78,10 +79,10 @@ int board_revision(void)
 	 */
 	cntrl0Reg = mfdcr(cntrl0);
 	mtdcr(cntrl0, cntrl0Reg | 0x03000000);
-	out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00100200);
+	out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00100200);
-	out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00100200);
+	out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00100200);
 	udelay(1000);                   /* wait some time before reading input */
-	value = in32(GPIO0_IR) & 0x00100200;       /* get config bits */
+	value = in_be32((void*)GPIO0_IR) & 0x00100200;       /* get config bits */
 
 	/*
 	 * Restore GPIO settings
@@ -137,10 +138,10 @@ int board_early_init_f (void)
 	/*
 	 * First pull fpga-prg pin low, to disable fpga logic (on version 1.2 board)
 	 */
-	out32(GPIO0_ODR, 0x00000000);        /* no open drain pins      */
+	out_be32((void*)GPIO0_ODR, 0x00000000);        /* no open drain pins      */
-	out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG);      /* setup for output        */
+	out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG);      /* setup for output        */
-	out32(GPIO0_OR,  CONFIG_SYS_FPGA_PRG);      /* set output pins to high */
+	out_be32((void*)GPIO0_OR,  CONFIG_SYS_FPGA_PRG);      /* set output pins to high */
-	out32(GPIO0_OR, 0);                  /* pull prg low            */
+	out_be32((void*)GPIO0_OR, 0);                  /* pull prg low            */
 
 	/*
 	 * IRQ 0-15  405GP internally generated; active high; level sensitive
@@ -181,15 +182,6 @@ int board_early_init_f (void)
 	return 0;
 }
 
-
-/* ------------------------------------------------------------------------- */
-
-int misc_init_f (void)
-{
-	return 0;  /* dummy implementation */
-}
-
-
 int misc_init_r (void)
 {
 	unsigned char *dst;
@@ -284,13 +276,11 @@ int misc_init_r (void)
 		*magic = 0;      /* clear pci reconfig magic again */
 	}
 
-#if 1 /* test-only */
 	/*
 	 * Decrease PLB latency timeout and reduce priority of the PCI bridge master
 	 */
 #define PCI0_BRDGOPT1 0x4a
 	pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f20);
-/*	pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f60);	*/
 
 #define plb0_acr      0x87
 	/*
@@ -298,14 +288,6 @@ int misc_init_r (void)
 	 */
 	mtdcr(plb0_acr, 0x98000000);
 
-#if 0 /* test-only */
-	printf("CCR0=%08x\n", mfspr(ccr0)); /* test-only */
-/*	mtspr(ccr0, (mfspr(ccr0) & 0xff8fffff) | 0x00100000);	*/
-	mtspr(ccr0, (mfspr(ccr0) & 0xff8fffff) | 0x00000000);
-#endif
-/*	printf("CCR0=%08x\n", mfspr(ccr0)); */ /* test-only */
-#endif
-
 	free(dst);
 	return (0);
 }
@@ -314,7 +296,6 @@ int misc_init_r (void)
 /*
  * Check Board Identity:
  */
-
 int checkboard (void)
 {
 	char str[64];
@@ -340,10 +321,10 @@ int checkboard (void)
 		 */
 		cntrl0Reg = mfdcr(cntrl0);
 		mtdcr(cntrl0, cntrl0Reg & ~0x08000000);
-		out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x40000000);
+		out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x40000000);
-		out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x40000000);
+		out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x40000000);
 		udelay(1000);                   /* wait some time before reading input */
-		value = in32(GPIO0_IR) & 0x40000000;       /* get config bits */
+		value = in_be32((void*)GPIO0_IR) & 0x40000000;       /* get config bits */
 		if (value) {
 			puts(", 33 MHz PCI");
 		} else {

board/esd/plu405/plu405.c

@@ -104,6 +104,7 @@ int misc_init_r (void)
 	unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
 	unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
 	unsigned char *dst;
+	unsigned char fctr;
 	ulong len = sizeof(fpgadata);
 	int status;
 	int index;
@@ -203,6 +204,15 @@ int misc_init_r (void)
 	out_8(duart0_mcr, 0x08);
 	out_8(duart1_mcr, 0x08);
 
+	/*
+	 * Enable auto RS485 mode in 2nd external uart
+	 */
+	out_8((void *)DUART1_BA + 3, 0xbf); /* write LCR */
+	fctr = in_8((void *)DUART1_BA + 1); /* read FCTR */
+	fctr |= 0x08;                       /* enable RS485 mode */
+	out_8((void *)DUART1_BA + 1, fctr); /* write FCTR */
+	out_8((void *)DUART1_BA + 3, 0);    /* write LCR */
+
 	return (0);
 }
 

board/esd/pmc440/cmd_pmc440.c

@@ -364,7 +364,7 @@ int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD;
 #endif
 	/*
-	 * gd->bd->bi_memsize == physical ram size - CFG_MEM_TOP_HIDE
+	 * gd->bd->bi_memsize == physical ram size - CONFIG_SYS_MEM_TOP_HIDE
 	 */
 	param = base - (pram << 10);
 	printf("PARAM: @%08x\n", param);

board/esd/pmc440/pmc440.c

@@ -107,7 +107,7 @@ int board_early_init_f(void)
 	 * Setup the GPIO pins
 	 * TODO: setup GPIOs via CONFIG_SYS_4xx_GPIO_TABLE in board's config file
 	 */
-	out32(GPIO0_OR,    0x40000002);
+	out32(GPIO0_OR,    0x40000102);
 	out32(GPIO0_TCR,   0x4c90011f);
 	out32(GPIO0_OSRL,  0x28051400);
 	out32(GPIO0_OSRH,  0x55005000);
@@ -755,17 +755,31 @@ int post_hotkeys_pressed(void)
 #ifdef CONFIG_RESET_PHY_R
 void reset_phy(void)
 {
+	char *s;
+	unsigned short val_method, val_behavior;
+
+	/* special LED setup for NGCC/CANDES */
+	if ((s = getenv("bd_type")) &&
+	    ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes")))) {
+		val_method   = 0x0e0a;
+		val_behavior = 0x0cf2;
+	} else {
+		/* PMC440 standard type */
+		val_method   = 0x0e10;
+		val_behavior = 0x0cf0;
+	}
+
 	if (miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0001) == 0) {
 		miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0010);
-		miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0df0);
+		miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, val_behavior);
-		miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, 0x0e10);
+		miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, val_method);
 		miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0000);
 	}
 
 	if (miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0001) == 0) {
 		miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0010);
-		miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0df0);
+		miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, val_behavior);
-		miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x10, 0x0e10);
+		miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x10, val_method);
 		miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0000);
 	}
 }

board/evb64260/zuma_pbb.c

@@ -149,8 +149,10 @@ void zuma_init_pbb (void)
 
 	pci_read_config_dword (dev, PCI_BASE_ADDRESS_0, &iobase);
 
-	zuma_pbb_reg =
+	iobase &= PCI_BASE_ADDRESS_MEM_MASK;
-			(PBB_DMA_REG_MAP *) (iobase & PCI_BASE_ADDRESS_MEM_MASK);
+
+	zuma_pbb_reg = (PBB_DMA_REG_MAP *)iobase;
+
 
 	if (!zuma_pbb_reg) {
 		printf ("zuma pbb bar none! (hah hah, get it?)\n");

board/evb64260/zuma_pbb_mbox.c

@@ -165,7 +165,9 @@ int zuma_mbox_init(void)
 
   pci_read_config_dword(zuma_mbox_dev.dev, PCI_BASE_ADDRESS_0, &iobase);
 
-  zuma_mbox_dev.sip = (PBB_DMA_REG_MAP *) (iobase & PCI_BASE_ADDRESS_MEM_MASK);
+  iobase &= PCI_BASE_ADDRESS_MEM_MASK;
+
+  zuma_mbox_dev.sip = (PBB_DMA_REG_MAP *)iobase;
 
   zuma_mbox_dev.sip->int_mask.word=0;
 

board/freescale/mpc8536ds/mpc8536ds.c

@@ -41,10 +41,6 @@
 #include "../common/pixis.h"
 #include "../common/sgmii_riser.h"
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
 phys_size_t fixed_sdram(void);
 
 int checkboard (void)
@@ -65,20 +61,12 @@ initdram(int board_type)
 
 #ifdef CONFIG_SPD_EEPROM
 	dram_size = fsl_ddr_sdram();
-
-	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-
-	dram_size *= 0x100000;
 #else
 	dram_size = fixed_sdram();
 #endif
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-	/*
-	 * Initialize and enable DDR ECC.
-	 */
-	ddr_enable_ecc(dram_size);
-#endif
 	puts("    DDR: ");
 	return dram_size;
 }

board/freescale/mpc8540ads/mpc8540ads.c

@@ -133,7 +133,7 @@ local_bus_init(void)
 	 */
 
 	get_sys_info(&sysinfo);
-	clkdiv = lbc->lcrr & 0x0f;
+	clkdiv = lbc->lcrr & LCRR_CLKDIV;
 	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
 	if (lbc_hz < 66) {

board/freescale/mpc8541cds/mpc8541cds.c

@@ -308,7 +308,7 @@ local_bus_init(void)
 	 */
 
 	get_sys_info(&sysinfo);
-	clkdiv = lbc->lcrr & 0x0f;
+	clkdiv = lbc->lcrr & LCRR_CLKDIV;
 	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
 	if (lbc_hz < 66) {

board/freescale/mpc8544ds/mpc8544ds.c

@@ -38,10 +38,6 @@
 #include "../common/pixis.h"
 #include "../common/sgmii_riser.h"
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
 int checkboard (void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@@ -77,12 +73,6 @@ initdram(int board_type)
 
 	dram_size *= 0x100000;
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-	/*
-	 * Initialize and enable DDR ECC.
-	 */
-	ddr_enable_ecc(dram_size);
-#endif
 	puts("    DDR: ");
 	return dram_size;
 }
@@ -131,7 +121,7 @@ pci_init_board(void)
 	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
 	struct pci_controller *hose = &pcie3_hose;
 	int pcie_ep = (host_agent == 1);
-	int pcie_configured  = io_sel >= 1;
+	int pcie_configured  = io_sel >= 6;
 	struct pci_region *r = hose->regions;
 
 	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
@@ -198,7 +188,7 @@ pci_init_board(void)
 	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
 	struct pci_controller *hose = &pcie1_hose;
 	int pcie_ep = (host_agent == 5);
-	int pcie_configured  = io_sel & 6;
+	int pcie_configured  = io_sel >= 2;
 	struct pci_region *r = hose->regions;
 
 	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
@@ -261,7 +251,7 @@ pci_init_board(void)
 	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
 	struct pci_controller *hose = &pcie2_hose;
 	int pcie_ep = (host_agent == 3);
-	int pcie_configured  = io_sel & 4;
+	int pcie_configured  = io_sel >= 4;
 	struct pci_region *r = hose->regions;
 
 	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){

board/freescale/mpc8548cds/mpc8548cds.c

@@ -38,10 +38,6 @@
 #include "../common/eeprom.h"
 #include "../common/via.h"
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
 DECLARE_GLOBAL_DATA_PTR;
 
 void local_bus_init(void);
@@ -56,7 +52,6 @@ int checkboard (void)
 	uint pci_slot = get_pci_slot ();
 
 	uint cpu_board_rev = get_cpu_board_revision ();
-	uint svr;
 
 	printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
 		get_board_version (), pci_slot);
@@ -69,17 +64,6 @@ int checkboard (void)
 	 */
 	local_bus_init ();
 
-	svr = get_svr();
-
-	/*
-	 * Fix CPU2 errata: A core hang possible while executing a
-	 * msync instruction and a snoopable transaction from an I/O
-	 * master tagged to make quick forward progress is present.
-	 * Fixed in Silicon Rev.2.1
-	 */
-	if (!(SVR_MAJ(svr) >= 2 && SVR_MIN(svr) >= 1))
-		ecm->eebpcr |= (1 << 16);
-
 	/*
 	 * Hack TSEC 3 and 4 IO voltages.
 	 */
@@ -118,13 +102,6 @@ initdram(int board_type)
 	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 	dram_size *= 0x100000;
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-	/*
-	 * Initialize and enable DDR ECC.
-	 */
-	ddr_enable_ecc(dram_size);
-#endif
-
 	/*
 	 * SDRAM Initialization
 	 */
@@ -148,7 +125,7 @@ local_bus_init(void)
 	sys_info_t sysinfo;
 
 	get_sys_info(&sysinfo);
-	clkdiv = (lbc->lcrr & 0x0f) * 2;
+	clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
 	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
 	gur->lbiuiplldcr1 = 0x00078080;
@@ -355,7 +332,7 @@ pci_init_board(void)
 		first_free_busno=hose->last_busno+1;
 		printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
 #ifdef CONFIG_PCIX_CHECK
-		if (!(gur->pordevsr & PORDEVSR_PCI)) {
+		if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
 			/* PCI-X init */
 			if (CONFIG_SYS_CLK_FREQ < 66000000)
 				printf("PCI-X will only work at 66 MHz\n");

board/freescale/mpc8555cds/mpc8555cds.c

@@ -308,7 +308,7 @@ local_bus_init(void)
 	 */
 
 	get_sys_info(&sysinfo);
-	clkdiv = lbc->lcrr & 0x0f;
+	clkdiv = lbc->lcrr & LCRR_CLKDIV;
 	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
 	if (lbc_hz < 66) {

board/freescale/mpc8560ads/mpc8560ads.c

@@ -337,7 +337,7 @@ local_bus_init(void)
 	 */
 
 	get_sys_info(&sysinfo);
-	clkdiv = lbc->lcrr & 0x0f;
+	clkdiv = lbc->lcrr & LCRR_CLKDIV;
 	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
 	if (lbc_hz < 66) {

board/freescale/mpc8568mds/mpc8568mds.c

@@ -99,11 +99,6 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
 	{0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
 };
 
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
 void local_bus_init(void);
 void sdram_init(void);
 
@@ -170,13 +165,6 @@ initdram(int board_type)
 	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 	dram_size *= 0x100000;
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-	/*
-	 * Initialize and enable DDR ECC.
-	 */
-	ddr_enable_ecc(dram_size);
-#endif
-
 	/*
 	 * SDRAM Initialization
 	 */
@@ -200,7 +188,7 @@ local_bus_init(void)
 	sys_info_t sysinfo;
 
 	get_sys_info(&sysinfo);
-	clkdiv = (lbc->lcrr & 0x0f) * 2;
+	clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
 	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
 	gur->lbiuiplldcr1 = 0x00078080;

board/freescale/mpc8572ds/mpc8572ds.c

@@ -38,10 +38,6 @@
 #include "../common/pixis.h"
 #include "../common/sgmii_riser.h"
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
 long int fixed_sdram(void);
 
 int checkboard (void)
@@ -61,20 +57,12 @@ phys_size_t initdram(int board_type)
 
 #ifdef CONFIG_SPD_EEPROM
 	dram_size = fsl_ddr_sdram();
-
-	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-
-	dram_size *= 0x100000;
 #else
 	dram_size = fixed_sdram();
 #endif
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-	/*
-	 * Initialize and enable DDR ECC.
-	 */
-	ddr_enable_ecc(dram_size);
-#endif
 	puts("    DDR: ");
 	return dram_size;
 }
@@ -178,11 +166,11 @@ void pci_init_board(void)
 		struct pci_controller *hose = &pcie3_hose;
 		int pcie_ep = (host_agent == 0) || (host_agent == 3) ||
 			(host_agent == 5) || (host_agent == 6);
-		int pcie_configured  = io_sel >= 1;
+		int pcie_configured  = (io_sel == 0x7);
 		struct pci_region *r = hose->regions;
 		u32 temp32;
 
-		if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
+		if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
 			printf ("\n    PCIE3 connected to ULI as %s (base address %x)",
 					pcie_ep ? "End Point" : "Root Complex",
 					(uint)pci);
@@ -246,10 +234,10 @@ void pci_init_board(void)
 		struct pci_controller *hose = &pcie2_hose;
 		int pcie_ep = (host_agent == 2) || (host_agent == 4) ||
 			(host_agent == 6) || (host_agent == 0);
-		int pcie_configured  = io_sel & 4;
+		int pcie_configured  = (io_sel == 0x3) || (io_sel == 0x7);
 		struct pci_region *r = hose->regions;
 
-		if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
+		if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
 			printf ("\n    PCIE2 connected to Slot 1 as %s (base address %x)",
 					pcie_ep ? "End Point" : "Root Complex",
 					(uint)pci);
@@ -299,7 +287,9 @@ void pci_init_board(void)
 		struct pci_controller *hose = &pcie1_hose;
 		int pcie_ep = (host_agent <= 1) || (host_agent == 4) ||
 			(host_agent == 5);
-		int pcie_configured  = io_sel & 6;
+		int pcie_configured  = (io_sel == 0x2) || (io_sel == 0x3) ||
+					(io_sel == 0x7) || (io_sel == 0xb) ||
+					(io_sel == 0xc) || (io_sel == 0xf);
 		struct pci_region *r = hose->regions;
 
 		if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){

board/freescale/mpc8572ds/tlb.c

@@ -41,10 +41,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 
-	SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-
 	/* TLB 1 */
 	/* *I*** - Covers boot page */
 	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
@@ -86,6 +82,9 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 7, BOOKE_PAGESZ_1M, 1),
 
+	SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 8, BOOKE_PAGESZ_4K, 1),
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);

board/freescale/mpc8610hpcd/law.c

@@ -31,8 +31,8 @@ struct law_entry law_table[] = {
 #if !defined(CONFIG_SPD_EEPROM)
 	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR_1),
 #endif
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1),
+	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE2_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
+	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
 	SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1),
 	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2),

board/freescale/mpc8610hpcd/mpc8610hpcd.c

@@ -266,14 +266,14 @@ void pci_init_board(void)
 
 		/* outbound memory */
 		pci_set_region(r++,
-			 CONFIG_SYS_PCIE1_MEM_BASE,
+			 CONFIG_SYS_PCIE1_MEM_BUS,
 			 CONFIG_SYS_PCIE1_MEM_PHYS,
 			 CONFIG_SYS_PCIE1_MEM_SIZE,
 			 PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(r++,
-			 CONFIG_SYS_PCIE1_IO_BASE,
+			 CONFIG_SYS_PCIE1_IO_BUS,
 			 CONFIG_SYS_PCIE1_IO_PHYS,
 			 CONFIG_SYS_PCIE1_IO_SIZE,
 			 PCI_REGION_IO);
@@ -321,14 +321,14 @@ void pci_init_board(void)
 
 		/* outbound memory */
 		pci_set_region(r++,
-			 CONFIG_SYS_PCIE2_MEM_BASE,
+			 CONFIG_SYS_PCIE2_MEM_BUS,
 			 CONFIG_SYS_PCIE2_MEM_PHYS,
 			 CONFIG_SYS_PCIE2_MEM_SIZE,
 			 PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(r++,
-			 CONFIG_SYS_PCIE2_IO_BASE,
+			 CONFIG_SYS_PCIE2_IO_BUS,
 			 CONFIG_SYS_PCIE2_IO_PHYS,
 			 CONFIG_SYS_PCIE2_IO_SIZE,
 			 PCI_REGION_IO);
@@ -370,14 +370,14 @@ void pci_init_board(void)
 
 		/* outbound memory */
 		pci_set_region(r++,
-			 CONFIG_SYS_PCI1_MEM_BASE,
+			 CONFIG_SYS_PCI1_MEM_BUS,
 			 CONFIG_SYS_PCI1_MEM_PHYS,
 			 CONFIG_SYS_PCI1_MEM_SIZE,
 			 PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(r++,
-			 CONFIG_SYS_PCI1_IO_BASE,
+			 CONFIG_SYS_PCI1_IO_BUS,
 			 CONFIG_SYS_PCI1_IO_PHYS,
 			 CONFIG_SYS_PCI1_IO_SIZE,
 			 PCI_REGION_IO);

board/keymile/common/keymile_hdlc_enet.c

@@ -0,0 +1,620 @@
+/*
+ * (C) Copyright 2008
+ * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
+ *
+ * Based in part on cpu/mpc8260/ether_scc.c.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <net.h>
+
+#ifdef CONFIG_KEYMILE_HDLC_ENET
+#ifdef TEST_IT
+#include <command.h>
+#endif
+
+#include "keymile_hdlc_enet.h"
+
+extern char keymile_slot;	/* our slot number in the backplane */
+
+/* Allow up to about 50 ms for sending */
+#define TOUT_LOOP	50000
+
+/*
+ * Since, except during initialization, ethact is always HDLC ETHERNET
+ * while we're in the driver, just use serial_printf() everywhere for
+ * output.  This avoids possible conflicts when netconsole is being
+ * used.
+ */
+#define dprintf(fmt, args...)	serial_printf(fmt, ##args)
+
+/* Cannot use the storage from net.c because we allocate larger buffers */
+static volatile uchar MyPktBuf[HDLC_PKTBUFSRX * PKT_MAXBLR_SIZE + PKTALIGN];
+static volatile uchar *MyRxPackets[HDLC_PKTBUFSRX]; /* Receive packet */
+
+static unsigned int keymile_rxIdx;	/* index of the current RX buffer */
+
+static IPaddr_t cachedNumbers[CACHEDNUMBERS]; /* 4 bytes per entry */
+void initCachedNumbers(int);
+
+/*
+  * SCC Ethernet Tx and Rx buffer descriptors allocated at the
+  *  immr->udata_bd address on Dual-Port RAM
+  * Provide for Double Buffering
+  */
+typedef volatile struct CommonBufferDescriptor {
+    cbd_t txbd;			/* Tx BD */
+    cbd_t rxbd[HDLC_PKTBUFSRX];	/* Rx BD */
+} RTXBD;
+
+/*
+ * This must be extern because it is allocated in DPRAM using CPM-sepcific
+ * code.
+ */
+static RTXBD *rtx;
+
+static int keymile_hdlc_enet_send(struct eth_device *, volatile void *, int);
+static int keymile_hdlc_enet_recv(struct eth_device *);
+void keymile_hdlc_enet_init_bds(RTXBD *);
+extern int keymile_hdlc_enet_init(struct eth_device *, bd_t *);
+extern void keymile_hdlc_enet_halt(struct eth_device *);
+
+/* flags in the buffer descriptor not defined anywhere else */
+#define BD_SC_CT	BD_SC_CD
+#define BD_SC_CR	0x04
+#define BD_SC_DE	0x80
+#ifndef BD_SC_TC
+#define BD_SC_TC	((ushort)0x0400)	/* Transmit CRC */
+#endif
+#define BD_SC_FIRST	BD_SC_TC
+#define BD_SC_STATS (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_CR | BD_SC_CD \
+		| BD_SC_OV | BD_SC_DE)
+
+#if defined(TEST_RX) || defined(TEST_TX) || defined(TEST_IT)
+static void hexdump(unsigned char *buf, int len)
+{
+	int i;
+	const int bytesPerLine = 32;
+
+	if (len > 4 * bytesPerLine)
+		len = 4 * bytesPerLine;
+	dprintf("\t address: %08x\n", (unsigned int)buf);
+	for (i = 0; i < len; i++) {
+		if (i % bytesPerLine == 0)
+			dprintf("%04x: ", (unsigned short)i);
+		dprintf("%02x ", buf[i]);
+		if ((i + 1) % bytesPerLine == 0) {
+			dprintf("\n");
+			continue;
+		}
+		if ((i + 1) % 8 == 0)
+			printf(" ");
+	}
+	if (len % bytesPerLine)
+		dprintf("\n");
+}
+#endif
+
+int keymile_hdlc_enet_initialize(bd_t *bis)
+{
+	struct eth_device *dev;
+
+	dev = (struct eth_device *) malloc(sizeof *dev);
+	memset(dev, 0, sizeof *dev);
+#ifdef TEST_IT
+	seth = dev;
+#endif
+
+	sprintf(dev->name, "HDLC ETHERNET");
+	dev->init   = keymile_hdlc_enet_init;
+	dev->halt   = keymile_hdlc_enet_halt;
+	dev->send   = keymile_hdlc_enet_send;
+	dev->recv   = keymile_hdlc_enet_recv;
+
+	eth_register(dev);
+
+	return 1;
+}
+
+/*
+ * This is called from the board-specific driver after rtx is allocated.
+ */
+void keymile_hdlc_enet_init_bds(RTXBD *board_rtx)
+{
+	volatile cbd_t *bdp;
+	int i;
+
+	rtx = board_rtx;
+	keymile_rxIdx = 0;
+	/*
+	 * Initialize the buffer descriptors.
+	 */
+	bdp = &rtx->txbd;
+	bdp->cbd_sc = 0;
+	bdp->cbd_bufaddr = 0;
+	bdp->cbd_sc = BD_SC_WRAP;
+
+	/*
+	 *	Setup RX packet buffers, aligned correctly.
+	 *	Borrowed from net/net.c.
+	 */
+	MyRxPackets[0] = &MyPktBuf[0] + (PKTALIGN - 1);
+	MyRxPackets[0] -= (ulong)MyRxPackets[0] % PKTALIGN;
+	for (i = 1; i < HDLC_PKTBUFSRX; i++)
+		MyRxPackets[i] = MyRxPackets[0] + i * PKT_MAXBLR_SIZE;
+
+	bdp = &rtx->rxbd[0];
+	for (i = 0; i < HDLC_PKTBUFSRX; i++) {
+		bdp->cbd_sc = BD_SC_EMPTY;
+		/* Leave space at the start for INET header. */
+		bdp->cbd_bufaddr = (unsigned int)(MyRxPackets[i] +
+			INET_HDR_ALIGN);
+		bdp++;
+	}
+	bdp--;
+	bdp->cbd_sc |= BD_SC_WRAP;
+}
+
+/*
+ * This returns the current port number for NETCONSOLE.  If nc_port
+ * in netconsole.c weren't declared static we wouldn't need this.
+ */
+static short get_netcons_port(void)
+{
+	char *p;
+	short nc_port;
+
+	nc_port = 6666; /* default */
+
+	p = getenv("ncip");
+	if (p != NULL) {
+		p = strchr(p, ':');
+		if (p != NULL)
+			nc_port = simple_strtoul(p + 1, NULL, 10);
+	}
+
+	return htons(nc_port);
+}
+
+/*
+ * Read the port numbers from the variables
+ */
+void initCachedNumbers(int verbose)
+{
+	char *str;
+	ushort port;
+
+	/* already in network order */
+	cachedNumbers[IP_ADDR] = getenv_IPaddr("ipaddr");
+	/* already in network order */
+	cachedNumbers[IP_SERVER] = getenv_IPaddr("serverip");
+	str = getenv("tftpsrcp");
+	if (str != NULL) {
+		/* avoid doing htons() again and again */
+		port = htons((ushort)simple_strtol(str, NULL, 10));
+		cachedNumbers[TFTP_SRC_PORT] = port;
+	} else
+		/* this can never be a valid port number */
+		cachedNumbers[TFTP_SRC_PORT] = (ulong)-1;
+	str = getenv("tftpdstp");
+	if (str != NULL) {
+		/* avoid doing htons() again and again */
+		port = htons((ushort)simple_strtol(str, NULL, 10));
+		cachedNumbers[TFTP_DST_PORT] = port;
+	} else
+		/* this is the default value */
+		cachedNumbers[TFTP_DST_PORT] = htons(WELL_KNOWN_PORT);
+	/* already in network order */
+	cachedNumbers[NETCONS_PORT] = get_netcons_port();
+	if (verbose) {
+		dprintf("\nIP Number Initialization:\n");
+		dprintf(" ip address          %08lx\n", cachedNumbers[IP_ADDR]);
+		dprintf(" server ip address   %08lx\n",
+			cachedNumbers[IP_SERVER]);
+		dprintf(" tftp client port    %ld\n",
+			cachedNumbers[TFTP_SRC_PORT]);
+		dprintf(" tftp server port    %ld\n",
+			cachedNumbers[TFTP_DST_PORT]);
+		dprintf(" netcons port        %ld\n",
+			cachedNumbers[NETCONS_PORT]);
+		dprintf(" slot number (hex)   %02x\n", keymile_slot);
+	}
+}
+
+static void keymile_hdlc_enet_doarp(volatile void *packet, int len)
+{
+	ARP_t *arp;
+	IPaddr_t src_ip; /* U-Boot's IP */
+	IPaddr_t dest_ip; /* the mgcoge's IP */
+	unsigned char *packet_copy = malloc(len);
+
+	/*
+	 * Handling an ARP request means that a new transfer has started.
+	 * Update our cached parameters now.
+	 */
+	initCachedNumbers(0); /* may reinit port numbers */
+
+	/* special handling required for ARP */
+	arp = (ARP_t *)(packet + ETHER_HDR_SIZE);
+	/*
+	 *	XXXX
+	 * This is pretty dirty!  NetReceive only uses
+	 * a few fields when handling an ARP reply, so
+	 * we only modify those here.  This could
+	 * result in catastrophic failure at a later
+	 * time if the handler is modified!
+	 */
+	arp->ar_op = htons(ARPOP_REPLY);
+	/* save his/our IP */
+	src_ip = NetReadIP(&arp->ar_data[6]);
+	dest_ip = NetReadIP(&arp->ar_data[16]);
+	/* copy target IP to source IP */
+	NetCopyIP(&arp->ar_data[6], &dest_ip);
+	/* copy our IP to the right place */
+	NetCopyIP(&arp->ar_data[16], &src_ip);
+	/* always use 0x7f as the MAC for the coge */
+	arp->ar_data[0] = HDLC_UACUA;
+	/*
+	 * copy the packet
+	 * if NetReceive wants to write to stdout, it may overwrite packet
+	 * especially if stdout is set to nc!
+	 *
+	 * However, if the malloc() above fails then we can still try the
+	 * original packet, rather than causing the transfer to fail.
+	 */
+	if (packet_copy != NULL) {
+		memcpy(packet_copy, (char *)packet, len);
+		NetReceive(packet_copy, len);
+		free(packet_copy);
+	} else
+		NetReceive(packet, len);
+}
+
+/*
+ * NOTE all callers ignore the returned value!
+ * At the moment this only handles ARP Requests, TFTP and NETCONSOLE.
+ */
+static int keymile_hdlc_enet_send(struct eth_device *dev, volatile void *packet,
+	int len)
+{
+	int j;
+	uint data_addr;
+	int data_len;
+	struct icn_hdr header;
+	struct icn_frame *frame;
+	Ethernet_t *et;
+	ARP_t *arp;
+	IP_t *ip;
+
+	if (len > (MAX_FRAME_LENGTH - sizeof(header)))
+		return -1;
+
+	frame = NULL;
+	et = NULL;
+	arp = NULL;
+	ip = NULL;
+
+	j = 0;
+	while ((rtx->txbd.cbd_sc & BD_SC_READY) && (j < TOUT_LOOP)) {
+		/* will also trigger Wd if needed, but maybe too often  */
+		udelay(1);
+		j++;
+	}
+	if (j >= TOUT_LOOP) {
+		dprintf("TX not ready sc %x\n", rtx->txbd.cbd_sc);
+		return -1;
+	}
+
+	/*
+	 * First check for an ARP Request since this requires special handling.
+	 */
+	if (len >= (ARP_HDR_SIZE + ETHER_HDR_SIZE)) {
+		et = (Ethernet_t *)packet;
+		arp = (ARP_t *)(((char *)et) + ETHER_HDR_SIZE);
+		/* ARP and REQUEST? */
+		if (et->et_protlen == PROT_ARP &&
+			arp->ar_op == htons(ARPOP_REQUEST)) {
+			/* just short-circuit the request on the U-Boot side */
+			keymile_hdlc_enet_doarp(packet, len);
+			return 0;
+		}
+	}
+
+	/*
+	 * GJ - I suppose the assumption here that len will always be
+	 * > INET_HDR_SIZE is alright as long as the network stack
+	 * isn't changed.
+	 * Do not send INET header.
+	 */
+	data_len = len + sizeof(header) - INET_HDR_SIZE;
+	frame = (struct icn_frame *) (((char *)packet) + INET_HDR_SIZE -
+		sizeof(header));
+
+#ifdef TEST_TX
+	printf("frame: %08x, ", frame);
+	hexdump((unsigned char *)packet, data_len + INET_HDR_SIZE);
+#endif
+
+	data_addr = (uint)frame;
+	if (len >= (IP_HDR_SIZE + ETHER_HDR_SIZE))
+		ip = (IP_t *)(packet + ETHER_HDR_SIZE);
+	/* Is it TFTP? TFTP always uses UDP and the cached dport */
+	if (ip != NULL && ip->ip_p == IPPROTO_UDP && ip->udp_dst ==
+			(ushort)cachedNumbers[TFTP_DST_PORT]) {
+		/* just in case the port wasn't set in the environment */
+		if (cachedNumbers[TFTP_SRC_PORT] == (ulong)-1)
+			cachedNumbers[TFTP_SRC_PORT] = ip->udp_src;
+		frame->hdr.application = MGS_TFTP;
+	}
+	/*
+	 * Is it NETCONSOLE?  NETCONSOLE always uses UDP.
+	 */
+	else if (ip != NULL && ip->ip_p == IPPROTO_UDP
+		&& ip->udp_dst == (ushort)cachedNumbers[NETCONS_PORT]) {
+			frame->hdr.application = MGS_NETCONS;
+	} else {
+		/* reject unknown packets */
+		/* may do some check on frame->hdr.application */
+		dprintf("Unknown packet type in %s, rejected\n",
+			__func__);
+		return -1;
+	}
+	/*
+	 * Could extract the target's slot ID from its MAC here,
+	 * but u-boot only wants to talk to the active server.
+	 *
+	 * avoid setting new source address when moving to another slot
+	 */
+	frame->hdr.src_addr = keymile_slot;
+	frame->hdr.dest_addr = HDLC_UACUA;
+#ifdef TEST_TX
+	{
+		dprintf("TX: ");
+		hexdump((unsigned char *)data_addr, data_len);
+	}
+#endif
+
+	flush_cache(data_addr, data_len);
+	rtx->txbd.cbd_bufaddr = data_addr;
+	rtx->txbd.cbd_datlen = data_len;
+	rtx->txbd.cbd_sc |= (BD_SC_READY | BD_SC_TC | BD_SC_LAST | BD_SC_WRAP);
+
+	while ((rtx->txbd.cbd_sc & BD_SC_READY) && (j < TOUT_LOOP)) {
+		/* will also trigger Wd if needed, but maybe too often  */
+		udelay(1);
+		j++;
+	}
+	if (j >= TOUT_LOOP)
+		dprintf("TX timeout\n");
+#ifdef ET_DEBUG
+	dprintf("cycles: %d    status: %x\n", j, rtx->txbd.cbd_sc);
+#endif
+	j = (rtx->txbd.cbd_sc & BD_SC_STATS); /* return only status bits */
+	return j;
+}
+
+/*
+ * During a receive, the RxIdx points to the current incoming buffer.
+ * When we update through the ring, if the next incoming buffer has
+ * not been given to the system, we just set the empty indicator,
+ * effectively tossing the packet.
+ */
+static int keymile_hdlc_enet_recv(struct eth_device *dev)
+{
+	int length;
+	unsigned char app;
+	struct icn_frame *fp;
+	Ethernet_t *ep;
+	IP_t *ip;
+
+	for (;;) {
+		if (rtx->rxbd[keymile_rxIdx].cbd_sc & BD_SC_EMPTY) {
+			length = -1;
+			break;	/* nothing received - leave for() loop */
+		}
+
+		length = rtx->rxbd[keymile_rxIdx].cbd_datlen;
+#ifdef TEST_RX
+		dprintf("packet %d bytes long\n", length);
+#endif
+
+		/*
+		 * BD_SC_BR -> LG bit
+		 * BD_SC_FR -> NO bit
+		 * BD_SC_PR -> AB bit
+		 * BD_SC_NAK -> CR bit
+		 * 0x80 -> DE bit
+		 */
+		if (rtx->rxbd[keymile_rxIdx].cbd_sc & BD_SC_STATS) {
+#ifdef ET_DEBUG
+			dprintf("err: %x\n", rtx->rxbd[keymile_rxIdx].cbd_sc);
+#endif
+		} else if (length > MAX_FRAME_LENGTH) { /* can't happen */
+#ifdef ET_DEBUG
+			dprintf("err: packet too big\n");
+#endif
+		} else {
+			fp = (struct icn_frame *)(MyRxPackets[keymile_rxIdx] +
+				INET_HDR_ALIGN - INET_HDR_SIZE);
+#ifdef TEST_RX
+			dprintf("RX %d: ", keymile_rxIdx);
+			hexdump((unsigned char *)MyRxPackets[keymile_rxIdx],
+				INET_HDR_ALIGN + INET_HDR_SIZE + 4);
+#endif
+			/* copy icn header to the beginning */
+			memcpy(fp, ((char *)fp + INET_HDR_SIZE),
+				sizeof(struct icn_hdr));
+			app = fp->hdr.application;
+			if (app == MGS_NETCONS || app == MGS_TFTP) {
+				struct icn_hdr *ih = &fp->hdr;
+				unsigned char icn_src_addr = ih->src_addr;
+				unsigned char icn_dest_addr = ih->dest_addr;
+
+				/*
+				 * expand header by INET_HDR_SIZE
+				 */
+				length += INET_HDR_SIZE;
+				/* initalize header */
+				memset((char *)fp->data, 0x00, INET_HDR_SIZE);
+				ep = (Ethernet_t *)fp->data;
+				/* set MACs */
+				ep->et_dest[0] = icn_dest_addr;
+				ep->et_src[0] = icn_src_addr;
+				ep->et_protlen = htons(PROT_IP);
+				/* set ip stuff */
+				ip = (IP_t *)(fp->data + ETHER_HDR_SIZE);
+				/* set ip addresses */
+				ip->ip_src = cachedNumbers[IP_SERVER];
+				ip->ip_dst = cachedNumbers[IP_ADDR];
+				/* ip length */
+				ip->ip_len = htons(length - ETHER_HDR_SIZE -
+					REMOVE);
+				/* ip proto */
+				ip->ip_p = IPPROTO_UDP;
+				switch (app) {
+				case MGS_TFTP:
+					/* swap src/dst port numbers */
+					ip->udp_src = (ushort)
+						cachedNumbers[TFTP_DST_PORT];
+					ip->udp_dst = (ushort)
+						cachedNumbers[TFTP_SRC_PORT];
+					ip->udp_len = ip->ip_len -
+						IP_HDR_SIZE_NO_UDP;
+					ip->udp_xsum = 0;
+					break;
+				case MGS_NETCONS:
+					ip->udp_src = (ushort)
+						cachedNumbers[NETCONS_PORT];
+					/*
+					 * in drivers/net/netconsole.c src port
+					 * equals dest port
+					 */
+					ip->udp_dst = ip->udp_src;
+					ip->udp_len = ip->ip_len -
+						IP_HDR_SIZE_NO_UDP;
+					ip->udp_xsum = 0;
+					break;
+				}
+				/* ip version */
+				ip->ip_hl_v = (0x40) | (0x0f &
+					(IP_HDR_SIZE_NO_UDP / 4));
+				ip->ip_tos = 0;
+				ip->ip_id = 0;
+				/* flags, fragment offset */
+				ip->ip_off = htons(0x4000);
+				ip->ip_ttl = 255; /* time to live */
+				/* have to fixup the checksum */
+				ip->ip_sum = ~NetCksum((uchar *)ip,
+					IP_HDR_SIZE_NO_UDP / 2);
+				/*
+				 * Pass the packet up to the protocol layers
+				 * but remove dest_addr, src_addr, application
+				 * and the CRC.
+				 */
+#ifdef TEST_RX
+				hexdump((unsigned char *)fp->data,
+					INET_HDR_SIZE + 4);
+#endif
+				NetReceive(fp->data, length - REMOVE);
+			} else {
+				/*
+				 * the other application types are not yet
+				 * supported by u-boot.
+				 */
+				/* normally drop it */
+#ifdef TEST_NO
+				/* send it anyway */
+				fp = (struct icn_frame *)
+					(MyRxPackets[keymile_rxIdx] +
+						INET_HDR_ALIGN);
+				NetReceive(fp->data, length - REMOVE);
+#endif
+			}
+		}
+
+		/* Give the buffer back to the SCC. */
+		rtx->rxbd[keymile_rxIdx].cbd_datlen = 0;
+
+		/* wrap around buffer index when necessary */
+		if ((keymile_rxIdx + 1) >= HDLC_PKTBUFSRX) {
+			rtx->rxbd[HDLC_PKTBUFSRX - 1].cbd_sc =
+				(BD_SC_WRAP | BD_SC_EMPTY);
+			keymile_rxIdx = 0;
+		} else {
+			rtx->rxbd[keymile_rxIdx].cbd_sc = BD_SC_EMPTY;
+			keymile_rxIdx++;
+		}
+	}
+	return length;
+}
+
+#ifdef TEST_IT
+/* simple send test routine */
+int hdlc_enet_stest(struct cmd_tbl_s *a, int b, int c, char **d)
+{
+	unsigned char pkt[2];
+	int ret;
+
+	dprintf("enter stest\n");
+	/* may have to initialize things */
+	if (seth->state != ETH_STATE_ACTIVE) {
+		/* the bd_t* is not used */
+		if (seth->init(seth, NULL) >= 0)
+			seth->state = ETH_STATE_ACTIVE;
+	}
+	pkt[0] = 0xea;
+	pkt[1] = 0xae;
+	ret = keymile_hdlc_enet_send(seth, pkt, 2);
+	dprintf("return from send %x\n", ret);
+	dprintf("exit stest\n");
+	return ret;
+}
+U_BOOT_CMD(
+	stest, 1, 1, hdlc_enet_stest,
+	"stest	- simple send test for hdlc_enet\n",
+	"no arguments\n"
+);
+/* simple receive test routine */
+int hdlc_enet_rtest(struct cmd_tbl_s *a, int b, int c, char **d)
+{
+	int ret;
+
+	dprintf("enter rtest\n");
+	/* may have to initialize things */
+	if (seth->state != ETH_STATE_ACTIVE) {
+		/* the bd_t* is not used */
+		if (seth->init(seth, NULL) >= 0)
+			seth->state = ETH_STATE_ACTIVE;
+	}
+	ret = keymile_hdlc_enet_recv(seth);
+	dprintf("return from recv %x\n", ret);
+	dprintf("exit rtest\n");
+	return ret;
+}
+U_BOOT_CMD(
+	rtest, 1, 1, hdlc_enet_rtest,
+	"rtest	- simple receive test for hdlc_enet\n",
+	"no arguments\n"
+);
+#endif
+
+#endif /* CONFIG_KEYMILE_HDLC_ENET */

board/keymile/common/keymile_hdlc_enet.h

@@ -0,0 +1,129 @@
+/*
+ * (C) Copyright 2008
+ * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _KEYMILE_HDLC_ENET_H_
+#define _KEYMILE_HDLC_ENET_H_
+
+/* Unfortuantely, we have do this to get the flag defines in the cbd_t */
+#ifdef CONFIG_MGSUVD
+#include <commproc.h>
+#endif
+#ifdef CONFIG_MGCOGE
+#include <mpc8260.h>
+#include <asm/cpm_8260.h>
+#endif
+
+/*
+ * Defines for the ICN protocol used for communication over HDLC
+ * on the backplane between MGSUVDs and MGCOGEs.
+ */
+
+/*
+ * MAC which is reserved for communication (0x00 - 0xff in the last byte,
+ * which is the slot number)
+ */
+
+/*
+ * A DLL frame looks like this:
+ *  8 bit  |  8 bit     |  8 bit |  8 bit     | n * 8 bit| 16 bit|  8 bit
+ *  opening| destination| source | application|  data    |  FCS  | closing
+ *   flag  |  address   | address|            |          |       |  flag
+ *  (HW)      (APP)       (APP)      (APP)       (APP)      (HW)   (HW)
+ */
+
+/*
+ * The opening flag, the FCS and the closing flag are set by the hardware so
+ * they are not reflected in this struct.
+ */
+struct icn_hdr {
+	unsigned char dest_addr;
+	unsigned char src_addr;
+	unsigned char application;
+} __attribute__((packed));
+
+#define ICNHDR_LEN	(sizeof(struct icn_hdr))
+#define CRC_LEN		(sizeof(short))
+/* bytes to remove from packet before sending it upstream */
+#define REMOVE		(ICNHDR_LEN + CRC_LEN)
+
+struct icn_frame {
+	struct icn_hdr hdr;
+	unsigned char data[0];	/* a place holder */
+} __attribute__((packed));
+
+/* Address field */
+#define HDLC_UUA	0x00 /* Unicast Unit Address */
+#define HDLC_UUA_MASK	0x3f /* the last 6 bits contain the slot number */
+#define SET_HDLC_UUA(x) ((HDLC_UUA | ((x) & HDLC_UUA_MASK)))
+#define HDLC_UACUA	0x7f /* Unicast Active Control Unit Address */
+#define HDLC_BCAST	0xff /* broadcast */
+
+/* Application field */
+#define MGS_UUSP	0x00
+#define MGS_UREP	0x01
+#define MGS_IUP		0x02
+#define MGS_UTA		0x03
+#define MGS_MDS		0x04
+#define MGS_ITIME	0x05
+/* added by DENX */
+#define MGS_NETCONS	0x06	/* netconsole */
+#define MGS_TFTP	0x07
+
+/* Useful defines for buffer sizes, etc. */
+#define HDLC_PKTBUFSRX		32
+#define MAX_FRAME_LENGTH	1500 /* ethernet frame size */
+			 /*   14        +    28     */
+#define INET_HDR_SIZE	(ETHER_HDR_SIZE + IP_HDR_SIZE)
+#define INET_HDR_ALIGN	(((INET_HDR_SIZE + PKTALIGN - 1) / PKTALIGN) * PKTALIGN)
+/* INET_HDR_SIZE is stripped off */
+#define PKT_MAXBLR_SIZE	(MAX_FRAME_LENGTH + INET_HDR_ALIGN)
+
+/*
+ * It is too slow to read always the port numbers and IP addresses from the
+ * string variables.
+ * cachedNumbers is meant to cache it.
+ * THIS IS ONLY A SPEED IMPROVEMENT!
+ */
+enum {
+	IP_ADDR = 0,	/* getenv_IPaddr("serverip"); */
+	IP_SERVER,	/* getenv_IPaddr("ipaddr"); */
+	TFTP_SRC_PORT,	/* simple_strtol(getenv("tftpsrcp"), NULL, 10); */
+	TFTP_DST_PORT,	/* simple_strtol(getenv("tftpdstp"), NULL, 10); */
+	NETCONS_PORT,	/* simple_strtol(getenv("ncip"), NULL, 10); */
+	CACHEDNUMBERS
+};
+
+#define WELL_KNOWN_PORT 69	/* Well known TFTP port # */
+
+/* define this to create a test commend (htest) */
+#undef TEST_IT
+#ifdef TEST_IT
+/* have to save a copy of the eth_device for the test command's use */
+struct eth_device *seth;
+#endif
+/* define this for outputting of received packets */
+#undef TEST_RX
+/* define this for outputting of packets being sent */
+#undef TEST_TX
+
+#endif /* _KEYMILE_HDLC_ENET_H_ */

board/keymile/mgcoge/Makefile

@@ -28,7 +28,8 @@ endif
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o ../common/common.o
+COBJS	:= $(BOARD).o ../common/common.o ../common/keymile_hdlc_enet.o \
+		mgcoge_hdlc_enet.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))

board/keymile/mgcoge/mgcoge_hdlc_enet.c

@@ -0,0 +1,276 @@
+/*
+ * (C) Copyright 2008
+ * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
+ *
+ * Based in part on cpu/mpc8260/ether_scc.c.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <net.h>
+
+#ifdef CONFIG_KEYMILE_HDLC_ENET
+
+#include "../common/keymile_hdlc_enet.h"
+
+char keymile_slot;	/* our slot number in the backplane */
+
+/*
+ * Since, except during initialization, ethact is always HDLC ETHERNET
+ * while we're in the driver, just use serial_printf() everywhere for
+ * output.  This avoids possible conflicts when netconsole is being
+ * used.
+ */
+#define dprintf(fmt, args...)	serial_printf(fmt, ##args)
+
+static int already_inited;
+
+/*
+  * SCC Ethernet Tx and Rx buffer descriptors allocated at the
+  *  immr->udata_bd address on Dual-Port RAM
+  * Provide for Double Buffering
+  */
+typedef volatile struct CommonBufferDescriptor {
+    cbd_t txbd;			/* Tx BD */
+    cbd_t rxbd[HDLC_PKTBUFSRX];	/* Rx BD */
+} RTXBD;
+
+static RTXBD *rtx;
+
+int keymile_hdlc_enet_init(struct eth_device *, bd_t *);
+void keymile_hdlc_enet_halt(struct eth_device *);
+extern void keymile_hdlc_enet_init_bds(RTXBD *);
+extern void initCachedNumbers(int);
+
+/* Use SCC1 */
+#define CPM_CR_SCC_PAGE		CPM_CR_SCC1_PAGE
+#define CPM_CR_SCC_SBLOCK	CPM_CR_SCC1_SBLOCK
+#define CMXSCR_MASK		(CMXSCR_GR1|CMXSCR_SC1|\
+					CMXSCR_RS1CS_MSK|CMXSCR_TS1CS_MSK)
+#define CMXSCR_VALUE		(CMXSCR_RS1CS_CLK11|CMXSCR_TS1CS_CLK11)
+#define MGC_PROFF_HDLC	PROFF_SCC1
+#define MGC_SCC_HDLC	0	/* Index, not number! */
+
+int keymile_hdlc_enet_init(struct eth_device *dev, bd_t *bis)
+{
+	/* int i; */
+	uint dpr;
+	/* volatile cbd_t *bdp; */
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	volatile cpm8260_t *cp = &(im->im_cpm);
+	volatile scc_t *sccp;
+	volatile scc_hdlc_t *hpr;
+	volatile iop8260_t *iop;
+
+	if (already_inited)
+		return 0;
+
+	hpr = (scc_hdlc_t *)(&im->im_dprambase[MGC_PROFF_HDLC]);
+	sccp = (scc_t *)(&im->im_scc[MGC_SCC_HDLC]);
+	iop = &im->im_ioport;
+
+	/*
+	 * Disable receive and transmit just in case.
+	 */
+	sccp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
+
+	/*
+	 * Avoid exhausting DPRAM, which would cause a panic.
+	 */
+	if (rtx == NULL) {
+		/* dpr is an offset into dpram */
+		dpr = m8260_cpm_dpalloc(sizeof(RTXBD), 8);
+		rtx = (RTXBD *)&im->im_dprambase[dpr];
+	}
+
+	/* We need the slot number for addressing. */
+	keymile_slot = *(char *)(CONFIG_SYS_SLOT_ID_BASE +
+		CONFIG_SYS_SLOT_ID_OFF) & CONFIG_SYS_SLOT_ID_MASK;
+	/*
+	 * Be consistent with the Linux driver and set
+	 * only enetaddr[0].
+	 *
+	 * Always add 1 to the slot number so that
+	 * there are no problems with an ethaddr which
+	 * is all 0s.  This should be acceptable because
+	 * a board should never have a slot number of 255,
+	 * which is the broadcast address.  The HDLC addressing
+	 * uses only the slot number.
+	 */
+	dev->enetaddr[0] = keymile_slot + 1;
+#ifdef TEST_IT
+	dprintf("slot %d\n", keymile_slot);
+#endif
+
+	/* use pd30, pd31 pins for TXD1, RXD1 respectively */
+	iop->iop_ppard |= (0x80000000 >> 30) | (0x80000000 >> 31);
+	iop->iop_pdird |= (0x80000000 >> 30);
+	iop->iop_psord |= (0x80000000 >> 30);
+
+	/* use pc21 as CLK11 */
+	iop->iop_pparc |= (0x80000000 >> 21);
+	iop->iop_pdirc &= ~(0x80000000 >> 21);
+	iop->iop_psorc &= ~(0x80000000 >> 21);
+
+	/* use pc15 as CTS1 */
+	iop->iop_pparc |= (0x80000000 >> 15);
+	iop->iop_pdirc &= ~(0x80000000 >> 15);
+	iop->iop_psorc &= ~(0x80000000 >> 15);
+
+	/*
+	 * SI clock routing
+	 * use CLK11
+	 * this also connects SCC1 to NMSI
+	 */
+	im->im_cpmux.cmx_scr = (im->im_cpmux.cmx_scr & ~CMXSCR_MASK) |
+		CMXSCR_VALUE;
+
+	/* keymile_rxIdx = 0; */
+
+	/*
+	 * Initialize function code registers for big-endian.
+	 */
+	hpr->sh_genscc.scc_rfcr = CPMFCR_EB;
+	hpr->sh_genscc.scc_tfcr = CPMFCR_EB;
+
+	/*
+	 * Set maximum bytes per receive buffer.
+	 */
+	hpr->sh_genscc.scc_mrblr = MAX_FRAME_LENGTH;
+
+	/* Setup CRC generator values for HDLC */
+	hpr->sh_cmask = 0x0000F0B8;
+	hpr->sh_cpres = 0x0000FFFF;
+
+	/* Initialize all error counters to 0 */
+	hpr->sh_disfc = 0;
+	hpr->sh_crcec = 0;
+	hpr->sh_abtsc = 0;
+	hpr->sh_nmarc = 0;
+	hpr->sh_retrc = 0;
+
+	/* Set maximum frame length size */
+	hpr->sh_mflr = MAX_FRAME_LENGTH;
+
+	/* set to 1 for per frame processing change later if needed */
+	hpr->sh_rfthr = 1;
+
+	hpr->sh_hmask = 0xff;
+
+	hpr->sh_haddr2 = SET_HDLC_UUA(keymile_slot);
+	hpr->sh_haddr3 = hpr->sh_haddr2;
+	hpr->sh_haddr4 = hpr->sh_haddr2;
+	/* broadcast */
+	hpr->sh_haddr1 = HDLC_BCAST;
+
+	hpr->sh_genscc.scc_rbase = (unsigned int) &rtx->rxbd[0];
+	hpr->sh_genscc.scc_tbase = (unsigned int) &rtx->txbd;
+
+#if 0
+	/*
+	 * Initialize the buffer descriptors.
+	 */
+	bdp = &rtx->txbd;
+	bdp->cbd_sc = 0;
+	bdp->cbd_bufaddr = 0;
+	bdp->cbd_sc = BD_SC_WRAP;
+
+	/*
+	 *	Setup RX packet buffers, aligned correctly.
+	 *	Borrowed from net/net.c.
+	 */
+	MyRxPackets[0] = &MyPktBuf[0] + (PKTALIGN - 1);
+	MyRxPackets[0] -= (ulong)MyRxPackets[0] % PKTALIGN;
+	for (i = 1; i < HDLC_PKTBUFSRX; i++)
+		MyRxPackets[i] = MyRxPackets[0] + i * PKT_MAXBLR_SIZE;
+
+	bdp = &rtx->rxbd[0];
+	for (i = 0; i < HDLC_PKTBUFSRX; i++) {
+		bdp->cbd_sc = BD_SC_EMPTY;
+		/* Leave space at the start for INET header. */
+		bdp->cbd_bufaddr = (unsigned int)(MyRxPackets[i] +
+			INET_HDR_ALIGN);
+		bdp++;
+	}
+	bdp--;
+	bdp->cbd_sc |= BD_SC_WRAP;
+#else
+	keymile_hdlc_enet_init_bds(rtx);
+#endif
+
+	/* Let's re-initialize the channel now.	 We have to do it later
+	 * than the manual describes because we have just now finished
+	 * the BD initialization.
+	 */
+	cp->cp_cpcr = mk_cr_cmd(CPM_CR_SCC_PAGE, CPM_CR_SCC_SBLOCK,
+					0, CPM_CR_INIT_TRX) | CPM_CR_FLG;
+	while (cp->cp_cpcr & CPM_CR_FLG);
+
+	sccp->scc_gsmrl = SCC_GSMRL_MODE_HDLC;
+	/* CTSS=1 */
+	sccp->scc_gsmrh = SCC_GSMRH_CTSS;
+	/* NOF=0, RTE=1, DRT=0, BUS=1 */
+	sccp->scc_psmr = ((0x8000 >> 6) | (0x8000 >> 10));
+
+/* loopback for local testing */
+#ifdef GJTEST
+	dprintf("LOOPBACK!\n");
+	sccp->scc_gsmrl |= SCC_GSMRL_DIAG_LOOP;
+#endif
+
+	/*
+	 * Disable all interrupts and clear all pending
+	 * events.
+	 */
+	sccp->scc_sccm = 0;
+	sccp->scc_scce = 0xffff;
+
+	/*
+	 * And last, enable the transmit and receive processing.
+	 */
+	sccp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
+
+	dprintf("%s: HDLC ENET Version 0.3 on SCC%d\n", dev->name,
+		MGC_SCC_HDLC + 1);
+
+	/*
+	 * We may not get an ARP packet because ARP was already done on
+	 * a different interface, so initialize the cached values now.
+	 */
+	initCachedNumbers(1);
+
+	already_inited = 1;
+
+	return 0;
+}
+
+void keymile_hdlc_enet_halt(struct eth_device *dev)
+{
+#if 0 /* just return, but keep this for reference */
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+
+	/* maybe should do a graceful stop here? */
+	immr->im_scc[MGC_SCC_HDLC].scc_gsmrl &=
+		~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
+#endif
+}
+
+#endif /* CONFIG_MGCOGE_HDLC_ENET */

board/keymile/mgsuvd/Makefile

@@ -28,7 +28,8 @@ endif
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	= $(BOARD).o ../common/common.o
+COBJS	= $(BOARD).o ../common/common.o ../common/keymile_hdlc_enet.o \
+		mgsuvd_hdlc_enet.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))

board/keymile/mgsuvd/mgsuvd_hdlc_enet.c

@@ -0,0 +1,278 @@
+/*
+ * (C) Copyright 2008
+ * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
+ *
+ * Based in part on cpu/mpc8xx/scc.c.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>	/* commproc.h is included here */
+#include <malloc.h>
+#include <net.h>
+
+#ifdef CONFIG_KEYMILE_HDLC_ENET
+
+#include "../common/keymile_hdlc_enet.h"
+
+char keymile_slot;	/* our slot number in the backplane */
+
+/*
+ * Since, except during initialization, ethact is always HDLC ETHERNET
+ * while we're in the driver, just use serial_printf() everywhere for
+ * output.  This avoids possible conflicts when netconsole is being
+ * used.
+ */
+#define dprintf(fmt, args...)	serial_printf(fmt, ##args)
+
+static int already_inited;
+
+/*
+  * SCC Ethernet Tx and Rx buffer descriptors allocated at the
+  *  immr->udata_bd address on Dual-Port RAM
+  * Provide for Double Buffering
+  */
+typedef volatile struct CommonBufferDescriptor {
+    cbd_t txbd;			/* Tx BD */
+    cbd_t rxbd[HDLC_PKTBUFSRX];	/* Rx BD */
+} RTXBD;
+
+static RTXBD *rtx;
+
+int keymile_hdlc_enet_init(struct eth_device *, bd_t *);
+void keymile_hdlc_enet_halt(struct eth_device *);
+extern void keymile_hdlc_enet_init_bds(RTXBD *);
+extern void initCachedNumbers(int);
+
+/* Use SCC4 */
+#define MGS_CPM_CR_HDLC	CPM_CR_CH_SCC4
+#define MGS_PROFF_HDLC	PROFF_SCC4
+#define MGS_SCC_HDLC	3	/* Index, not number! */
+
+int keymile_hdlc_enet_init(struct eth_device *dev, bd_t *bis)
+{
+	/* int i; */
+	/* volatile cbd_t *bdp; */
+	volatile cpm8xx_t *cp;
+	volatile scc_t *sccp;
+	volatile hdlc_pram_t *hpr;
+	volatile iop8xx_t *iop;
+
+	if (already_inited)
+		return 0;
+
+	cp = (cpm8xx_t *)&(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm);
+	hpr = (hdlc_pram_t *)(&cp->cp_dparam[MGS_PROFF_HDLC]);
+	sccp = (volatile scc_t *)(&cp->cp_scc[MGS_SCC_HDLC]);
+	iop = (iop8xx_t *)&(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport);
+
+	/*
+	 * Disable receive and transmit just in case.
+	 */
+	sccp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
+
+#ifndef CONFIG_SYS_ALLOC_DPRAM
+#error "CONFIG_SYS_ALLOC_DPRAM must be defined"
+#else
+	/*
+	 * Avoid exhausting DPRAM, which would cause a panic.
+	 * Actually this isn't really necessary, but leave it here
+	 * for safety's sake.
+	 */
+	if (rtx == NULL) {
+		rtx = (RTXBD *) (cp->cp_dpmem +
+			 dpram_alloc_align(sizeof(RTXBD), 8));
+		if (rtx == (RTXBD *)CPM_DP_NOSPACE)
+			return -1;
+		memset((void *)rtx, 0, sizeof(RTXBD));
+	}
+#endif /* !CONFIG_SYS_ALLOC_DPRAM */
+
+	/* We need the slot number for addressing. */
+	keymile_slot = *(char *)(CONFIG_SYS_SLOT_ID_BASE +
+		CONFIG_SYS_SLOT_ID_OFF) & CONFIG_SYS_SLOT_ID_MASK;
+	/*
+	 * Be consistent with the Linux driver and set
+	 * only enetaddr[0].
+	 *
+	 * Always add 1 to the slot number so that
+	 * there are no problems with an ethaddr which
+	 * is all 0s.  This should be acceptable because
+	 * a board should never have a slot number of 255,
+	 * which is the broadcast address.  The HDLC addressing
+	 * uses only the slot number.
+	 */
+	dev->enetaddr[0] = keymile_slot + 1;
+
+#ifdef TEST_IT
+	dprintf("slot %d\n", keymile_slot);
+#endif
+
+	/* use pa8, pa9 pins for TXD4, RXD4 respectively */
+	iop->iop_papar |= ((0x8000 >> 8) | (0x8000 >> 9));
+	iop->iop_padir &= ~((0x8000 >> 8) | (0x8000 >> 9));
+	iop->iop_paodr &= ~((0x8000 >> 8) | (0x8000 >> 9));
+
+	/* also use pa0 as CLK8 */
+	iop->iop_papar |= 0x8000;
+	iop->iop_padir &= ~0x8000;
+	iop->iop_paodr &= ~0x8000;
+
+	/* use pc5 as CTS4 */
+	iop->iop_pcpar &= ~(0x8000 >> 5);
+	iop->iop_pcdir &= ~(0x8000 >> 5);
+	iop->iop_pcso  |= (0x8000 >> 5);
+
+	/*
+	 * SI clock routing
+	 * use CLK8
+	 * this also connects SCC4 to NMSI
+	 */
+	cp->cp_sicr = (cp->cp_sicr & ~0xff000000) | 0x3f000000;
+
+	/* keymile_rxIdx = 0; */
+
+	/*
+	 * Initialize function code registers for big-endian.
+	 */
+	hpr->rfcr = SCC_EB;
+	hpr->tfcr = SCC_EB;
+
+	/*
+	 * Set maximum bytes per receive buffer.
+	 */
+	hpr->mrblr = MAX_FRAME_LENGTH;
+
+	/* Setup CRC generator values for HDLC */
+	hpr->c_mask = 0x0000F0B8;
+	hpr->c_pres = 0x0000FFFF;
+
+	/* Initialize all error counters to 0 */
+	hpr->disfc = 0;
+	hpr->crcec = 0;
+	hpr->abtsc = 0;
+	hpr->nmarc = 0;
+	hpr->retrc = 0;
+
+	/* Set maximum frame length size */
+	hpr->mflr = MAX_FRAME_LENGTH;
+
+	/* set to 1 for per frame processing change later if needed */
+	hpr->rfthr = 1;
+
+	hpr->hmask = 0xff;
+
+	hpr->haddr2 = SET_HDLC_UUA(keymile_slot);
+	hpr->haddr3 = hpr->haddr2;
+	hpr->haddr4 = hpr->haddr2;
+	/* broadcast */
+	hpr->haddr1 = HDLC_BCAST;
+
+	hpr->rbase = (unsigned int) &rtx->rxbd[0];
+	hpr->tbase = (unsigned int) &rtx->txbd;
+
+#if 0
+	/*
+	 * Initialize the buffer descriptors.
+	 */
+	bdp = &rtx->txbd;
+	bdp->cbd_sc = 0;
+	bdp->cbd_bufaddr = 0;
+	bdp->cbd_sc = BD_SC_WRAP;
+
+	/*
+	 *	Setup RX packet buffers, aligned correctly.
+	 *	Borrowed from net/net.c.
+	 */
+	MyRxPackets[0] = &MyPktBuf[0] + (PKTALIGN - 1);
+	MyRxPackets[0] -= (ulong)MyRxPackets[0] % PKTALIGN;
+	for (i = 1; i < HDLC_PKTBUFSRX; i++)
+		MyRxPackets[i] = MyRxPackets[0] + i * PKT_MAXBLR_SIZE;
+
+	bdp = &rtx->rxbd[0];
+	for (i = 0; i < HDLC_PKTBUFSRX; i++) {
+		bdp->cbd_sc = BD_SC_EMPTY;
+		/* Leave space at the start for INET header. */
+		bdp->cbd_bufaddr = (unsigned int)(MyRxPackets[i] +
+			INET_HDR_ALIGN);
+		bdp++;
+	}
+	bdp--;
+	bdp->cbd_sc |= BD_SC_WRAP;
+#else
+	keymile_hdlc_enet_init_bds(rtx);
+#endif
+
+	/* Let's re-initialize the channel now.	 We have to do it later
+	 * than the manual describes because we have just now finished
+	 * the BD initialization.
+	 */
+	cp->cp_cpcr = mk_cr_cmd(MGS_CPM_CR_HDLC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
+	while (cp->cp_cpcr & CPM_CR_FLG);
+
+	sccp->scc_gsmrl = SCC_GSMRL_MODE_HDLC;
+	/* CTSS=1 */
+	sccp->scc_gsmrh = SCC_GSMRH_CTSS;
+	/* NOF=0, RTE=1, DRT=0, BUS=1 */
+	sccp->scc_psmr = ((0x8000 >> 6) | (0x8000 >> 10));
+
+/* loopback for local testing */
+#ifdef GJTEST
+	dprintf("LOOPBACK!\n");
+	sccp->scc_gsmrl |= SCC_GSMRL_DIAG_LOOP;
+#endif
+
+	/*
+	 * Disable all interrupts and clear all pending
+	 * events.
+	 */
+	sccp->scc_sccm = 0;
+	sccp->scc_scce = 0xffff;
+
+	/*
+	 * And last, enable the transmit and receive processing.
+	 */
+	sccp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
+
+	dprintf("%s: HDLC ENET Version 0.3 on SCC%d\n", dev->name,
+		MGS_SCC_HDLC + 1);
+
+	/*
+	 * We may not get an ARP packet because ARP was already done on
+	 * a different interface, so initialize the cached values now.
+	 */
+	initCachedNumbers(1);
+
+	already_inited = 1;
+
+	return 0;
+}
+
+void keymile_hdlc_enet_halt(struct eth_device *dev)
+{
+#if 0 /* just return, but keep this for reference */
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+
+	/* maybe should do a graceful stop here? */
+	immr->im_cpm.cp_scc[MGS_SCC_HDLC].scc_gsmrl &=
+		~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
+#endif
+}
+
+#endif /* CONFIG_KEYMILE_HDLC_ENET */

board/lwmon/lwmon.c

@@ -762,19 +762,18 @@ static uchar *key_match (uchar *kbd_data)
 #ifdef CONFIG_LCD_INFO
 #include <lcd.h>
 #include <version.h>
+#include <timestamp.h>
 
 void lcd_show_board_info(void)
 {
 	char temp[32];
 
-	lcd_printf ("%s (%s - %s)\n", U_BOOT_VERSION, __DATE__, __TIME__);
+	lcd_printf ("%s (%s - %s)\n", U_BOOT_VERSION, U_BOOT_DATE, U_BOOT_TIME);
 	lcd_printf ("(C) 2008 DENX Software Engineering GmbH\n");
 	lcd_printf ("    Wolfgang DENK, wd@denx.de\n");
 #ifdef CONFIG_LCD_INFO_BELOW_LOGO
 	lcd_printf ("MPC823 CPU at %s MHz\n",
 		strmhz(temp, gd->cpu_clk));
-	lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT * 3,
-					info, strlen(info));
 	lcd_printf ("  %ld MB RAM, %ld MB Flash\n",
 		gd->ram_size >> 20,
 		gd->bd->bi_flashsize >> 20 );

board/m501sk/Makefile

@@ -27,8 +27,6 @@ LIB	= $(obj)lib$(BOARD).a
 
 COBJS  := m501sk.o eeprom.o
 
-SOBJS  := memsetup.o
-
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))

board/m501sk/memsetup.S

@@ -1,200 +0,0 @@
-/*
- * Memory Setup stuff - taken from blob memsetup.S
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
- *	          Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
- *
- * Modified for the at91rm9200dk board by
- * (C) Copyright 2004
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-
-#ifdef CONFIG_BOOTBINFUNC
-/*
- * some parameters for the board
- *
- * This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in
- * turn is based on the boot.bin code from ATMEL
- *
- */
-
-/* flash */
-#define MC_PUIA 0xFFFFFF10
-#define MC_PUIA_VAL 0x00000000
-#define MC_PUP 0xFFFFFF50
-#define MC_PUP_VAL 0x00000000
-#define MC_PUER 0xFFFFFF54
-#define MC_PUER_VAL 0x00000000
-#define MC_ASR 0xFFFFFF04
-#define MC_ASR_VAL 0x00000000
-#define MC_AASR 0xFFFFFF08
-#define MC_AASR_VAL 0x00000000
-#define EBI_CFGR 0xFFFFFF64
-#define EBI_CFGR_VAL 0x00000000
-#define SMC_CSR0 0xFFFFFF70
-#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
-
-/* clocks */
-#define PLLAR 0xFFFFFC28
-#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
-#define PLLBR 0xFFFFFC2C
-#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
-#define MCKR 0xFFFFFC30
-/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
-#define MCKR_VAL	0x00000202
-
-/* sdram */
-#define PIOC_ASR 0xFFFFF870
-#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as Perip (D16/D31) */
-#define PIOC_BSR 0xFFFFF874
-#define PIOC_BSR_VAL 0x00000000
-#define PIOC_PDR 0xFFFFF804
-#define PIOC_PDR_VAL 0xFFFF0000
-#define EBI_CSA 0xFFFFFF60
-#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
-#define SDRC_CR 0xFFFFFF98
-#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */
-#define SDRAM 0x20000000 /* address of the SDRAM */
-#define SDRAM1 0x20000080 /* address of the SDRAM */
-#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
-#define SDRC_MR 0xFFFFFF90
-#define SDRC_MR_VAL 0x00000002 /* Precharge All */
-#define SDRC_MR_VAL1 0x00000004 /* refresh */
-#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
-#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
-#define SDRC_TR 0xFFFFFF94
-#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
-
-_TEXT_BASE:
-	.word   TEXT_BASE
-
-.globl lowlevelinit
-lowlevelinit:
-	/* memory control configuration */
-	/* this isn't very elegant, but  what the heck */
-	ldr     r0, =SMRDATA
-	ldr     r1, _TEXT_BASE
-	sub     r0, r0, r1
-	add     r2, r0, #80
-0:
-	/* the address */
-	ldr     r1, [r0], #4
-	/* the value */
-	ldr     r3, [r0], #4
-	str     r3, [r1]
-	cmp     r2, r0
-	bne     0b
-	/* delay - this is all done by guess */
-	ldr     r0, =0x00010000
-1:
-	subs    r0, r0, #1
-	bhi     1b
-	ldr     r0, =SMRDATA1
-	ldr     r1, _TEXT_BASE
-	sub     r0, r0, r1
-	add     r2, r0, #176
-2:
-	/* the address */
-	ldr     r1, [r0], #4
-	/* the value */
-	ldr     r3, [r0], #4
-	str     r3, [r1]
-	cmp     r2, r0
-	bne     2b
-
-	/* everything is fine now */
-	mov     pc, lr
-
-	.ltorg
-
-SMRDATA:
-	.word MC_PUIA
-	.word MC_PUIA_VAL
-	.word MC_PUP
-	.word MC_PUP_VAL
-	.word MC_PUER
-	.word MC_PUER_VAL
-	.word MC_ASR
-	.word MC_ASR_VAL
-	.word MC_AASR
-	.word MC_AASR_VAL
-	.word EBI_CFGR
-	.word EBI_CFGR_VAL
-	.word SMC_CSR0
-	.word SMC_CSR0_VAL
-	.word PLLAR
-	.word PLLAR_VAL
-	.word PLLBR
-	.word PLLBR_VAL
-	.word MCKR
-	.word MCKR_VAL
-	/* SMRDATA is 80 bytes long */
-	/* here there's a delay of 100 */
-SMRDATA1:
-	.word PIOC_ASR
-	.word PIOC_ASR_VAL
-	.word PIOC_BSR
-	.word PIOC_BSR_VAL
-	.word PIOC_PDR
-	.word PIOC_PDR_VAL
-	.word EBI_CSA
-	.word EBI_CSA_VAL
-	.word SDRC_CR
-	.word SDRC_CR_VAL
-	.word SDRC_MR
-	.word SDRC_MR_VAL
-	.word SDRAM
-	.word SDRAM_VAL
-	.word SDRC_MR
-	.word SDRC_MR_VAL1
-	.word SDRAM
-	.word SDRAM_VAL
-	.word SDRAM
-	.word SDRAM_VAL
-	.word SDRAM
-	.word SDRAM_VAL
-	.word SDRAM
-	.word SDRAM_VAL
-	.word SDRAM
-	.word SDRAM_VAL
-	.word SDRAM
-	.word SDRAM_VAL
-	.word SDRAM
-	.word SDRAM_VAL
-	.word SDRAM
-	.word SDRAM_VAL
-	.word SDRC_MR
-	.word SDRC_MR_VAL2
-	.word SDRAM1
-	.word SDRAM_VAL
-	.word SDRC_TR
-	.word SDRC_TR_VAL
-	.word SDRAM
-	.word SDRAM_VAL
-	.word SDRC_MR
-	.word SDRC_MR_VAL3
-	.word SDRAM
-	.word SDRAM_VAL
-	/* SMRDATA1 is 176 bytes long */
-#endif /* CONFIG_BOOTBINFUNC */

board/ml2/u-boot.lds

@@ -63,7 +63,6 @@ SECTIONS
     cpu/ppc4xx/4xx_uart.o	(.text)
     cpu/ppc4xx/cpu_init.o	(.text)
     cpu/ppc4xx/speed.o	(.text)
-    drivers/net/4xx_enet.o	(.text)
     common/dlmalloc.o	(.text)
     lib_generic/crc32.o		(.text)
     lib_ppc/extable.o	(.text)

board/mousse/mousse.c

@@ -30,6 +30,7 @@
 #include <mpc824x.h>
 #include <netdev.h>
 #include <asm/processor.h>
+#include <timestamp.h>
 
 #include "mousse.h"
 #include "m48t59y.h"
@@ -42,7 +43,7 @@ int checkboard (void)
 	char buf[32];
 
 	puts ("Board: MOUSSE MPC8240/KAHLUA - CHRP (MAP B)\n");
-	printf ("Built: %s at %s\n", __DATE__, __TIME__);
+	printf ("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME);
 	printf ("MPLD:  Revision %d\n", SYS_REVID_GET ());
 	printf ("Local Bus:  %s MHz\n", strmhz (buf, busfreq));
 

board/mpc8540eval/mpc8540eval.c

@@ -101,7 +101,7 @@ phys_size_t initdram (int board_type)
 #if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */
 	get_sys_info(&sysinfo);
 	/* if localbus freq is less than 66MHz,we use bypass mode,otherwise use DLL */
-	if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f) < 66000000) {
+	if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV) < 66000000) {
 		lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000;
 	} else {
 		lbc->lcrr = CONFIG_SYS_LBC_LCRR & 0x7fffffff;

board/mpr2/lowlevel_init.S

@@ -22,6 +22,7 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
+#include <asm/macro.h>
 
 	.global	lowlevel_init
 
@@ -33,59 +34,35 @@ lowlevel_init:
 /*
  * Set frequency multipliers and dividers in FRQCR.
  */
-	mov.l	WTCSR_A,r1
+	write16	WTCSR_A, WTCSR_D
-	mov.l	WTCSR_D,r0
-	mov.w	r0,@r1
 
-	mov.l	WTCNT_A,r1
+	write16	WTCNT_A, WTCNT_D
-	mov.l	WTCNT_D,r0
-	mov.w	r0,@r1
 
-	mov.l	FRQCR_A,r1
+	write16	FRQCR_A, FRQCR_D
-	mov.l	FRQCR_D,r0
-	mov.w	r0,@r1
 
 /*
  * Setup CS0 (Flash).
  */
-	mov.l	CS0BCR_A, r1
+	write32	CS0BCR_A, CS0BCR_D
-	mov.l	CS0BCR_D, r0
-	mov.l	r0, @r1
 
-	mov.l	CS0WCR_A, r1
+	write32	CS0WCR_A, CS0WCR_D
-	mov.l	CS0WCR_D, r0
-	mov.l	r0, @r1
 
 /*
  * Setup CS3 (SDRAM).
  */
-	mov.l	CS3BCR_A, r1
+	write32	CS3BCR_A, CS3BCR_D
-	mov.l	CS3BCR_D, r0
-	mov.l	r0, @r1
 
-	mov.l	CS3WCR_A, r1
+	write32	CS3WCR_A, CS3WCR_D
-	mov.l	CS3WCR_D, r0
-	mov.l	r0, @r1
 
-	mov.l	SDCR_A, r1
+	write32	SDCR_A, SDCR_D1
-	mov.l	SDCR_D1, r0
-	mov.l	r0, @r1
 
-	mov.l	RTCSR_A, r1
+	write32	RTCSR_A, RTCSR_D
-	mov.l	RTCSR_D, r0
-	mov.l	r0, @r1
 
-	mov.l	RTCNT_A, r1
+	write32	RTCNT_A, RTCNT_D
-	mov.l	RTCNT_D, r0
-	mov.l	r0, @r1
 
-	mov.l	RTCOR_A, r1
+	write32	RTCOR_A, RTCOR_D
-	mov.l	RTCOR_D, r0
-	mov.l	r0, @r1
 
-	mov.l	SDCR_A, r1
+	write32	SDCR_A, SDCR_D2
-	mov.l	SDCR_D2, r0
-	mov.l	r0, @r1
 
 	mov.l	SDMR3_A, r1
 	mov.l	SDMR3_D, r0
@@ -112,21 +89,27 @@ WTCSR_D:	.long	0xA507		/* divide by 4096 */
 /*
  * Spansion S29GL256N11 @ 48 MHz
  */
-CS0BCR_D:	.long	0x12490400  /* 1 idle cycle inserted, normal space, 16 bit */
+/* 1 idle cycle inserted, normal space, 16 bit */
-CS0WCR_D:	.long	0x00000340  /* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */
+CS0BCR_D:	.long	0x12490400
+/* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */
+CS0WCR_D:	.long	0x00000340
 
 /*
  * Samsung K4S511632B-UL75 @ 48 MHz
  * Micron MT48LC32M16A2-75 @ 48 MHz
  */
-CS3BCR_D:	.long	0x10004400  /* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */
+/* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */
-CS3WCR_D:	.long	0x00000091  /* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */
+CS3BCR_D:	.long	0x10004400
-SDCR_D1:	.long	0x00000012  /* no refresh, 13 rows, 10 cols, NO bank active mode */
+/* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */
-SDCR_D2:	.long	0x00000812  /* refresh */
+CS3WCR_D:	.long	0x00000091
-RTCSR_D:	.long	0xA55A0008  /* 1/4, once */
+/* no refresh, 13 rows, 10 cols, NO bank active mode */
-RTCNT_D:	.long	0xA55A005D  /* count 93 */
+SDCR_D1:	.long	0x00000012
-RTCOR_D:	.long	0xa55a005d  /* count 93 */
+SDCR_D2:	.long	0x00000812	/* refresh */
-SDMR3_D:	.long	0x440       /* mode register CL2, burst read and SINGLE WRITE */
+RTCSR_D:	.long	0xA55A0008	/* 1/4, once */
+RTCNT_D:	.long	0xA55A005D	/* count 93 */
+RTCOR_D:	.long	0xa55a005d	/* count 93 */
+/* mode register CL2, burst read and SINGLE WRITE */
+SDMR3_D:	.long	0x440
 
 /*
  * Registers

board/ms7722se/lowlevel_init.S

@@ -27,13 +27,14 @@
 #include <version.h>
 
 #include <asm/processor.h>
+#include <asm/macro.h>
 
 /*
- *  Board specific low level init code, called _very_ early in the
+ * Board specific low level init code, called _very_ early in the
- *  startup sequence. Relocation to SDRAM has not happened yet, no
+ * startup sequence. Relocation to SDRAM has not happened yet, no
- *  stack is available, bss section has not been initialised, etc.
+ * stack is available, bss section has not been initialised, etc.
  *
- *  (Note: As no stack is available, no subroutines can be called...).
+ * (Note: As no stack is available, no subroutines can be called...).
  */
 
 	.global	lowlevel_init
@@ -43,167 +44,96 @@
 
 lowlevel_init:
 
-	/* Address of Cache Control Register */
+	/*
-	mov.l	CCR_A, r1
+	 * Cache Control Register
-	/*Instruction Cache Invalidate */
+	 * Instruction Cache Invalidate
-	mov.l	CCR_D, r0
+	 */
-	mov.l	r0, @r1
+	write32	CCR_A, CCR_D
 
-	/* Address of MMU Control Register */
+	/*
-	mov.l	MMUCR_A, r1
+	 * Address of MMU Control Register
-	/* TI == TLB Invalidate bit */
+	 * TI == TLB Invalidate bit
-	mov.l	MMUCR_D, r0
+	 */
-	mov.l	r0, @r1
+	write32	MMUCR_A, MMUCR_D
 
 	/* Address of Power Control Register 0 */
-	mov.l	MSTPCR0_A, r1
+	write32	MSTPCR0_A, MSTPCR0_D
-	mov.l	MSTPCR0_D, r0
-	mov.l	r0, @r1
 
 	/* Address of Power Control Register 2 */
-	mov.l	MSTPCR2_A, r1
+	write32	MSTPCR2_A, MSTPCR2_D
-	mov.l	MSTPCR2_D, r0
-	mov.l	r0, @r1
 
-	mov.l	SBSCR_A, r1
+	write16	SBSCR_A, SBSCR_D
-	mov.w	SBSCR_D, r0
-	mov.w	r0, @r1
 
-	mov.l	PSCR_A, r1
+	write16	PSCR_A, PSCR_D
-	mov.w	PSCR_D, r0
-	mov.w	r0, @r1
 
 	/* 0xA4520004 (Watchdog Control / Status Register) */
-!	mov.l	RWTCSR_A, r1
+!	write16	RWTCSR_A, RWTCSR_D_1	/* 0xA507 -> timer_STOP/WDT_CLK=max */
-	/* 0xA507 -> timer_STOP/WDT_CLK=max */
-!	mov.w	RWTCSR_D_1, r0
-!	mov.w	r0, @r1
 
 	/* 0xA4520000 (Watchdog Count Register) */
-	mov.l	RWTCNT_A, r1
+	write16	RWTCNT_A, RWTCNT_D	/*0x5A00 -> Clear */
-	/*0x5A00 -> Clear */
-	mov.w	RWTCNT_D, r0
-	mov.w	r0, @r1
 
 	/* 0xA4520004 (Watchdog Control / Status Register) */
-	mov.l	RWTCSR_A, r1
+	write16	RWTCSR_A, RWTCSR_D_2	/* 0xA504 -> timer_STOP/CLK=500ms */
-	/* 0xA504 -> timer_STOP/CLK=500ms */
-	mov.w	RWTCSR_D_2, r0
-	mov.w	r0, @r1
 
 	/* 0xA4150000 Frequency control register */
-	mov.l	FRQCR_A, r1
+	write32	FRQCR_A, FRQCR_D
-	mov.l	FRQCR_D, r0	!
-	mov.l	r0, @r1
 
-	mov.l	CCR_A, r1
+	write32	CCR_A, CCR_D_2
-	mov.l	CCR_D_2, r0
-	mov.l	r0, @r1
 
 bsc_init:
 
-	mov.l	PSELA_A, r1
+	write16	PSELA_A, PSELA_D
-	mov.w	PSELA_D, r0
-	mov.w	r0, @r1
 
-	mov.l	DRVCR_A, r1
+	write16	DRVCR_A, DRVCR_D
-	mov.w	DRVCR_D, r0
-	mov.w	r0, @r1
 
-	mov.l	PCCR_A, r1
+	write16	PCCR_A, PCCR_D
-	mov.w	PCCR_D, r0
-	mov.w	r0, @r1
 
-	mov.l	PECR_A, r1
+	write16	PECR_A, PECR_D
-	mov.w	PECR_D, r0
-	mov.w	r0, @r1
 
-	mov.l	PJCR_A, r1
+	write16	PJCR_A, PJCR_D
-	mov.w	PJCR_D, r0
-	mov.w	r0, @r1
 
-	mov.l	PXCR_A, r1
+	write16	PXCR_A, PXCR_D
-	mov.w	PXCR_D, r0
-	mov.w	r0, @r1
 
-	mov.l	CMNCR_A, r1	! CMNCR address -> R1
+	write32	CMNCR_A, CMNCR_D
-	mov.l	CMNCR_D, r0	! CMNCR data    -> R0
-	mov.l	r0, @r1		! CMNCR set
 
-	mov.l	CS0BCR_A, r1	! CS0BCR address -> R1
+	write32	CS0BCR_A, CS0BCR_D
-	mov.l	CS0BCR_D, r0	! CS0BCR data    -> R0
-	mov.l	r0, @r1		! CS0BCR set
 
-	mov.l	CS2BCR_A, r1	! CS2BCR address -> R1
+	write32	CS2BCR_A, CS2BCR_D
-	mov.l	CS2BCR_D, r0	! CS2BCR data    -> R0
-	mov.l	r0, @r1		! CS2BCR set
 
-	mov.l	CS4BCR_A, r1	! CS4BCR address -> R1
+	write32	CS4BCR_A, CS4BCR_D
-	mov.l	CS4BCR_D, r0	! CS4BCR data    -> R0
-	mov.l	r0, @r1		! CS4BCR set
 
-	mov.l	CS5ABCR_A, r1	! CS5ABCR address -> R1
+	write32	CS5ABCR_A, CS5ABCR_D
-	mov.l	CS5ABCR_D, r0	! CS5ABCR data    -> R0
-	mov.l	r0, @r1		! CS5ABCR set
 
-	mov.l	CS5BBCR_A, r1	! CS5BBCR address -> R1
+	write32	CS5BBCR_A, CS5BBCR_D
-	mov.l	CS5BBCR_D, r0	! CS5BBCR data    -> R0
-	mov.l	r0, @r1		! CS5BBCR set
 
-	mov.l	CS6ABCR_A, r1	! CS6ABCR address -> R1
+	write32	CS6ABCR_A, CS6ABCR_D
-	mov.l	CS6ABCR_D, r0	! CS6ABCR data    -> R0
-	mov.l	r0, @r1		! CS6ABCR set
 
-	mov.l	CS0WCR_A, r1	! CS0WCR address -> R1
+	write32	CS0WCR_A, CS0WCR_D
-	mov.l	CS0WCR_D, r0	! CS0WCR data    -> R0
-	mov.l	r0, @r1		! CS0WCR set
 
-	mov.l	CS2WCR_A, r1	! CS2WCR address -> R1
+	write32	CS2WCR_A, CS2WCR_D
-	mov.l	CS2WCR_D, r0	! CS2WCR data    -> R0
-	mov.l	r0, @r1		! CS2WCR set
 
-	mov.l	CS4WCR_A, r1	! CS4WCR address -> R1
+	write32	CS4WCR_A, CS4WCR_D
-	mov.l	CS4WCR_D, r0	! CS4WCR data    -> R0
-	mov.l	r0, @r1		! CS4WCR set
 
-	mov.l	CS5AWCR_A, r1	! CS5AWCR address -> R1
+	write32	CS5AWCR_A, CS5AWCR_D
-	mov.l	CS5AWCR_D, r0	! CS5AWCR data    -> R0
-	mov.l	r0, @r1		! CS5AWCR set
 
-	mov.l	CS5BWCR_A, r1	! CS5BWCR address -> R1
+	write32	CS5BWCR_A, CS5BWCR_D
-	mov.l	CS5BWCR_D, r0	! CS5BWCR data    -> R0
-	mov.l	r0, @r1		! CS5BWCR set
 
-	mov.l	CS6AWCR_A, r1	! CS6AWCR address -> R1
+	write32	CS6AWCR_A, CS6AWCR_D
-	mov.l	CS6AWCR_D, r0	! CS6AWCR data    -> R0
-	mov.l	r0, @r1		! CS6AWCR set
 
 	! SDRAM initialization
-	mov.l	SDCR_A, r1	! SB_SDCR address -> R1
+	write32	SDCR_A, SDCR_D
-	mov.l	SDCR_D, r0	! SB_SDCR data    -> R0
-	mov.l	r0, @r1		! SB_SDCR set
 
-	mov.l	SDWCR_A, r1	! SB_SDWCR address -> R1
+	write32	SDWCR_A, SDWCR_D
-	mov.l	SDWCR_D, r0	! SB_SDWCR data    -> R0
-	mov.l	r0, @r1		! SB_SDWCR set
 
-	mov.l	SDPCR_A, r1	! SB_SDPCR address -> R1
+	write32	SDPCR_A, SDPCR_D
-	mov.l	SDPCR_D, r0	! SB_SDPCR data    -> R0
-	mov.l	r0, @r1		! SB_SDPCR set
 
-	mov.l	RTCOR_A, r1	! SB_RTCOR address -> R1
+	write32	RTCOR_A, RTCOR_D
-	mov.l	RTCOR_D, r0	! SB_RTCOR data    -> R0
-	mov.l	r0, @r1		! SB_RTCOR set
 
-	mov.l	RTCSR_A, r1	! SB_RTCSR address -> R1
+	write32	RTCSR_A, RTCSR_D
-	mov.l	RTCSR_D, r0	! SB_RTCSR data    -> R0
-	mov.l	r0, @r1		! SB_RTCSR set
 
-	mov.l	SDMR3_A, r1	! SDMR3 address -> R1
+	write8	SDMR3_A, SDMR3_D
-	mov	#0x00, r0	! SDMR3 data    -> R0
-	mov.b	r0, @r1		! SDMR3 set
 
-	! BL bit off (init = ON)  (?!?)
+	! BL bit off (init = ON) (?!?)
 
 	stc	sr, r0				! BL bit off(init=ON)
 	mov.l	SR_MASK_D, r1
@@ -232,28 +162,28 @@ MSTPCR0_D:	.long	0x00001001
 MSTPCR2_D:	.long	0xffffffff
 FRQCR_D:	.long	0x07022538
 
-PSELA_A:	.long   0xa405014E
+PSELA_A:	.long	0xa405014E
-PSELA_D:	.word   0x0A10
+PSELA_D:	.word	0x0A10
 	.align 2
 
-DRVCR_A:	.long   0xa405018A
+DRVCR_A:	.long	0xa405018A
-DRVCR_D:	.word   0x0554
+DRVCR_D:	.word	0x0554
 	.align 2
 
-PCCR_A:		.long   0xa4050104
+PCCR_A:		.long	0xa4050104
-PCCR_D:		.word   0x8800
+PCCR_D:		.word	0x8800
 	.align 2
 
-PECR_A:		.long   0xa4050108
+PECR_A:		.long	0xa4050108
-PECR_D:		.word   0x0000
+PECR_D:		.word	0x0000
 	.align 2
 
-PJCR_A:		.long   0xa4050110
+PJCR_A:		.long	0xa4050110
-PJCR_D:		.word   0x1000
+PJCR_D:		.word	0x1000
 	.align 2
 
-PXCR_A:		.long   0xa4050148
+PXCR_A:		.long	0xa4050148
-PXCR_D:		.word   0x0AAA
+PXCR_D:		.word	0x0AAA
 	.align 2
 
 CMNCR_A:	.long	CMNCR
@@ -295,6 +225,7 @@ RTCOR_D:	.long	0xA55A0034
 RTCSR_A:	.long	SBSC_RTCSR
 RTCSR_D:	.long	0xA55A0010
 SDMR3_A:	.long	0xFE500180
+SDMR3_D:	.long	0x0
 
 	.align	1
 

board/ms7750se/lowlevel_init.S

@@ -29,120 +29,94 @@
 #include <version.h>
 
 #include <asm/processor.h>
+#include <asm/macro.h>
 
 #ifdef CONFIG_CPU_SH7751
-#define BCR2_D_VALUE	0x2FFC	   /* Area 1-6 width: 32/32/32/32/32/16 */
+#define BCR2_D_VALUE	0x2FFC		/* Area 1-6 width: 32/32/32/32/32/16 */
-#define WCR1_D_VALUE    0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */
+#define WCR1_D_VALUE	0x02770771	/* DMA:0 A6:2 A3:0 A0:1 Others:15 */
 #ifdef CONFIG_MARUBUN_PCCARD
-#define WCR2_D_VALUE    0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15
+#define WCR2_D_VALUE	0xFFFE4FE7	/* A6:15 A6B:7 A5:15 A5B:7 A4:15
-				      A3:2  A2:15 A1:15 A0:6  A0B:7  */
+					   A3:2  A2:15 A1:15 A0:6  A0B:7  */
 #else /* CONFIG_MARUBUN_PCCARD */
-#define WCR2_D_VALUE    0x7FFE4FE7 /* A6:3  A6B:7 A5:15 A5B:7 A4:15
+#define WCR2_D_VALUE	0x7FFE4FE7	/* A6:3  A6B:7 A5:15 A5B:7 A4:15
-				      A3:2  A2:15 A1:15 A0:6  A0B:7  */
+					   A3:2  A2:15 A1:15 A0:6  A0B:7  */
 #endif /* CONFIG_MARUBUN_PCCARD */
-#define WCR3_D_VALUE	0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
+#define WCR3_D_VALUE	0x01777771	/* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
-				      A2: 1-3 A1: 1-3 A0: 0-1 */
+					   A2: 1-3 A1: 1-3 A0: 0-1 */
-#define RTCOR_D_VALUE	0xA50D	   /* Write code A5, data 0D (~15us?) */
+#define RTCOR_D_VALUE	0xA50D		/* Write code A5, data 0D (~15us?) */
-#define SDMR3_ADDRESS	0xFF940088 /* SDMR3 address on 32-bit bus */
+#define SDMR3_ADDRESS	0xFF940088	/* SDMR3 address on 32-bit bus */
-#define MCR_D1_VALUE	0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, ... */
+#define MCR_D1_VALUE	0x100901B4	/* SDRAM 32-bit, CAS/RAS Refresh, .. */
-#define MCR_D2_VALUE	0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */
+#define MCR_D2_VALUE	0x500901B4	/* Same w/MRSET now 1 (mode reg cmd) */
 #else /* CONFIG_CPU_SH7751 */
-#define BCR2_D_VALUE	0x2E3C	   /* Area 1-6 width: 32/32/64/16/32/16 */
+#define BCR2_D_VALUE	0x2E3C		/* Area 1-6 width: 32/32/64/16/32/16 */
-#define WCR1_D_VALUE	0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */
+#define WCR1_D_VALUE	0x02720777	/* DMA:0 A6:2 A4:2 A3:0 Others:15 */
-#define WCR2_D_VALUE	0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15
+#define WCR2_D_VALUE	0xFFFE4FFF	/* A6:15 A6B:7 A5:15 A5B:7 A4:15
-				      A3:2  A2:15 A1:15 A0:15 A0B:7  */
+					   A3:2  A2:15 A1:15 A0:15 A0B:7  */
-#define WCR3_D_VALUE	0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3
+#define WCR3_D_VALUE	0x01717771	/* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3
-				      A2: 1-3 A1: 1-3 A0: 0-1 */
+					   A2: 1-3 A1: 1-3 A0: 0-1 */
-#define RTCOR_D_VALUE	0xA510	   /* Write code A5, data 10 (~15us?) */
+#define RTCOR_D_VALUE	0xA510		/* Write code A5, data 10 (~15us?) */
-#define SDMR3_ADDRESS	0xFF940110 /* SDMR3 address on 64-bit bus */
+#define SDMR3_ADDRESS	0xFF940110	/* SDMR3 address on 64-bit bus */
-#define MCR_D1_VALUE	0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, ... */
+#define MCR_D1_VALUE	0x8801001C	/* SDRAM 64-bit, CAS/RAS Refresh, .. */
-#define MCR_D2_VALUE	0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */
+#define MCR_D2_VALUE	0xC801001C	/* Same w/MRSET now 1 (mode reg cmd) */
 #endif /* CONFIG_CPU_SH7751 */
 
 	.global lowlevel_init
 	.text
-	.align  2
+	.align	2
 
 lowlevel_init:
 
-	mov.l   CCR_A, r1               ! CCR Address
+	write32	CCR_A, CCR_D_DISABLE
-	mov.l   CCR_D_DISABLE, r0       ! CCR Data
-	mov.l   r0, @r1
 
 init_bsc:
-	mov.l	FRQCR_A,r1	/* FRQCR Address */
+	write16	FRQCR_A, FRQCR_D
-	mov.l	FRQCR_D,r0	/* FRQCR Data */
-	mov.w	r0,@r1
 
-	mov.l	BCR1_A,r1	/* BCR1 Address */
+	write32	BCR1_A, BCR1_D
-	mov.l	BCR1_D,r0	/* BCR1 Data */
-	mov.l	r0,@r1
 
-	mov.l	BCR2_A,r1	/* BCR2 Address */
+	write16	BCR2_A, BCR2_D
-	mov.l	BCR2_D,r0	/* BCR2 Data */
-	mov.w	r0,@r1
 
-	mov.l	WCR1_A,r1	/* WCR1 Address */
+	write32	WCR1_A, WCR1_D
-	mov.l	WCR1_D,r0	/* WCR1 Data */
-	mov.l	r0,@r1
 
-	mov.l	WCR2_A,r1	/* WCR2 Address */
+	write32	WCR2_A, WCR2_D
-	mov.l	WCR2_D,r0	/* WCR2 Data */
-	mov.l	r0,@r1
 
-	mov.l	WCR3_A,r1	/* WCR3 Address */
+	write32	WCR3_A, WCR3_D
-	mov.l	WCR3_D,r0	/* WCR3 Data */
-	mov.l	r0,@r1
 
-	mov.l	MCR_A,r1	/* MCR Address */
+	write32	MCR_A, MCR_D1
-	mov.l	MCR_D1,r0	/* MCR Data1 */
-	mov.l	r0,@r1
 
-	mov.l	SDMR3_A,r1	/* Set SDRAM mode */
+	/* Set SDRAM mode */
-	mov	#0,r0
+	write8	SDMR3_A, SDMR3_D
-	mov.b	r0,@r1
 
 	! Do you need PCMCIA setting?
 	! If so, please add the lines here...
 
-	mov.l	RTCNT_A,r1	/* RTCNT Address */
+	write16	RTCNT_A, RTCNT_D
-	mov.l	RTCNT_D,r0	/* RTCNT Data */
-	mov.w	r0,@r1
 
-	mov.l	RTCOR_A,r1	/* RTCOR Address */
+	write16	RTCOR_A, RTCOR_D
-	mov.l	RTCOR_D,r0	/* RTCOR Data */
-	mov.w	r0,@r1
 
-	mov.l	RTCSR_A,r1	/* RTCSR Address */
+	write16	RTCSR_A, RTCSR_D
-	mov.l	RTCSR_D,r0	/* RTCSR Data */
+
-	mov.w	r0,@r1
+	write16	RFCR_A, RFCR_D
 
-	mov.l	RFCR_A,r1	/* RFCR Address */
-	mov.l	RFCR_D,r0	/* RFCR Data */
-	mov.w	r0,@r1		/* Clear reflesh counter */
 	/* Wait DRAM refresh 30 times */
-	mov	#30,r3
+	mov	#30, r3
 1:
-	mov.w	@r1,r0
+	mov.w	@r1, r0
-	extu.w	r0,r2
+	extu.w	r0, r2
-	cmp/hi	r3,r2
+	cmp/hi	r3, r2
 	bf	1b
 
-	mov.l	MCR_A,r1	/* MCR Address */
+	write32	MCR_A, MCR_D2
-	mov.l	MCR_D2,r0	/* MCR Data2 */
-	mov.l	r0,@r1
 
-	mov.l	SDMR3_A,r1	/* Set SDRAM mode */
+	/* Set SDRAM mode */
-	mov	#0,r0
+	write8	SDMR3_A, SDMR3_D
-	mov.b	r0,@r1
 
 	rts
-	 nop
+	nop
 
 	.align	2
 
-CCR_A:          .long   CCR
+CCR_A:		 .long	CCR
-CCR_D_DISABLE:  .long   0x0808
+CCR_D_DISABLE:	.long	0x0808
 FRQCR_A:	.long	FRQCR
 FRQCR_D:
 #ifdef CONFIG_CPU_TYPE_R
@@ -172,6 +146,7 @@ RTCNT_D:	.long	0xA500		/* RTCNT Write Code A5h Data 00h */
 RTCOR_A:	.long	RTCOR
 RTCOR_D:	.long	RTCOR_D_VALUE	/* Set refresh time (about 15us) */
 SDMR3_A:	.long	SDMR3_ADDRESS
+SDMR3_D:	.long	0x00
 MCR_A:		.long	MCR
 MCR_D1:		.long	MCR_D1_VALUE
 MCR_D2:		.long	MCR_D2_VALUE

board/netstar/eeprom.c

@@ -26,6 +26,7 @@
 
 #include <common.h>
 #include <exports.h>
+#include <timestamp.h>
 #include "../drivers/net/smc91111.h"
 
 #define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE
@@ -173,7 +174,7 @@ int eeprom(int argc, char *argv[])
 	/* Print help message */
 	if (argv[1][1] == 'h') {
 		printf("VoiceBlue EEPROM writer\n");
-		printf("Built: %s at %s\n", __DATE__ , __TIME__ );
+		printf("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME);
 		printf("Usage:\n\t<mac_address> [<element_1>] [<...>]\n");
 		return 0;
 	}

board/pm854/pm854.c

@@ -150,7 +150,7 @@ local_bus_init(void)
 	 */
 
 	get_sys_info(&sysinfo);
-	clkdiv = lbc->lcrr & 0x0f;
+	clkdiv = lbc->lcrr & LCRR_CLKDIV;
 	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
 	if (lbc_hz < 66) {

board/pm856/pm856.c

@@ -306,7 +306,7 @@ local_bus_init(void)
 	 */
 
 	get_sys_info(&sysinfo);
-	clkdiv = lbc->lcrr & 0x0f;
+	clkdiv = lbc->lcrr & LCRR_CLKDIV;
 	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
 	if (lbc_hz < 66) {

board/renesas/MigoR/lowlevel_init.S

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2007
+ * Copyright (C) 2007-2008
  * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
  *
  * Copyright (C) 2007
@@ -27,13 +27,14 @@
 #include <version.h>
 
 #include <asm/processor.h>
+#include <asm/macro.h>
 
 /*
- *  Board specific low level init code, called _very_ early in the
+ * Board specific low level init code, called _very_ early in the
- *  startup sequence. Relocation to SDRAM has not happened yet, no
+ * startup sequence. Relocation to SDRAM has not happened yet, no
- *  stack is available, bss section has not been initialised, etc.
+ * stack is available, bss section has not been initialised, etc.
  *
- *  (Note: As no stack is available, no subroutines can be called...).
+ * (Note: As no stack is available, no subroutines can be called...).
  */
 
 	.global	lowlevel_init
@@ -42,141 +43,83 @@
 	.align	2
 
 lowlevel_init:
-	mov.l	CCR_A, r1	! Address of Cache Control Register
+	write32	CCR_A, CCR_D		! Address of Cache Control Register
-	mov.l	CCR_D, r0	! Instruction Cache Invalidate
+					! Instruction Cache Invalidate
-	mov.l	r0, @r1
 
-	mov.l	MMUCR_A, r1	! Address of MMU Control Register
+	write32	MMUCR_A, MMUCR_D	! Address of MMU Control Register
-	mov.l	MMUCR_D, r0	! TI == TLB Invalidate bit
+					! TI == TLB Invalidate bit
-	mov.l	r0, @r1
 
-	mov.l	MSTPCR0_A, r1	! Address of Power Control Register 0
+	write32	MSTPCR0_A, MSTPCR0_D	! Address of Power Control Register 0
-	mov.l	MSTPCR0_D, r0	!
-	mov.l	r0, @r1
 
-	mov.l	MSTPCR2_A, r1	! Address of Power Control Register 2
+	write32	MSTPCR2_A, MSTPCR2_D	! Address of Power Control Register 2
-	mov.l	MSTPCR2_D, r0	!
-	mov.l	r0, @r1
 
-	mov.l	PFC_PULCR_A, r1
+	write16	PFC_PULCR_A, PFC_PULCR_D
-	mov.w	PFC_PULCR_D, r0
-	mov.w	r0,@r1
 
-	mov.l	PFC_DRVCR_A, r1
+	write16	PFC_DRVCR_A, PFC_DRVCR_D
-	mov.w	PFC_DRVCR_D, r0
-	mov.w	r0, @r1
 
-	mov.l	SBSCR_A, r1	!
+	write16	SBSCR_A, SBSCR_D
-	mov.w	SBSCR_D, r0	!
-	mov.w	r0, @r1
 
-	mov.l	PSCR_A, r1	!
+	write16	PSCR_A, PSCR_D
-	mov.w	PSCR_D, r0	!
-	mov.w	r0, @r1
 
-	mov.l	RWTCSR_A, r1	! 0xA4520004 (Watchdog Control / Status Register)
+	write16	RWTCSR_A, RWTCSR_D_1	! 0xA4520004 (Watchdog Control / Status Register)
-	mov.w	RWTCSR_D_1, r0	! 0xA507 -> timer_STOP/WDT_CLK=max
+					! 0xA507 -> timer_STOP / WDT_CLK = max
-	mov.w	r0, @r1
 
-	mov.l	RWTCNT_A, r1	! 0xA4520000 (Watchdog Count Register)
+	write16	RWTCNT_A, RWTCNT_D	! 0xA4520000 (Watchdog Count Register)
-	mov.w	RWTCNT_D, r0	! 0x5A00 -> Clear
+					! 0x5A00 -> Clear
-	mov.w	r0, @r1
 
-	mov.l	RWTCSR_A, r1	! 0xA4520004 (Watchdog Control / Status Register)
+	write16	RWTCSR_A, RWTCSR_D_2	! 0xA4520004 (Watchdog Control / Status Register)
-	mov.w	RWTCSR_D_2, r0	! 0xA504 -> timer_STOP/CLK=500ms
+					! 0xA504 -> timer_STOP / CLK = 500ms
-	mov.w	r0, @r1
 
-	mov.l	DLLFRQ_A, r1	! 20080115
+	write32	DLLFRQ_A, DLLFRQ_D	! 20080115
-	mov.l	DLLFRQ_D, r0	! 20080115
+					! 20080115
-	mov.l	r0, @r1
 
-	mov.l	FRQCR_A, r1		! 0xA4150000 Frequency control register
+	write32	FRQCR_A, FRQCR_D	! 0xA4150000 Frequency control register
-	mov.l	FRQCR_D, r0	! 20080115
+					! 20080115
-	mov.l	r0, @r1
 
-	mov.l	CCR_A, r1		! Address of Cache Control Register
+	write32	CCR_A, CCR_D_2		! Address of Cache Control Register
-	mov.l	CCR_D_2, r0	! ??
+					! ??
-	mov.l	r0, @r1
 
 bsc_init:
-	mov.l	CMNCR_A, r1	! CMNCR address -> R1
+	write32	CMNCR_A, CMNCR_D
-	mov.l	CMNCR_D, r0	! CMNCR data    -> R0
-	mov.l	r0, @r1		! CMNCR set
 
-	mov.l	CS0BCR_A, r1	! CS0BCR address -> R1
+	write32	CS0BCR_A, CS0BCR_D
-	mov.l	CS0BCR_D, r0	! CS0BCR data    -> R0
-	mov.l	r0, @r1		! CS0BCR set
 
-	mov.l	CS4BCR_A, r1	! CS4BCR address -> R1
+	write32	CS4BCR_A, CS4BCR_D
-	mov.l	CS4BCR_D, r0	! CS4BCR data    -> R0
-	mov.l	r0, @r1		! CS4BCR set
 
-	mov.l	CS5ABCR_A, r1	! CS5ABCR address -> R1
+	write32	CS5ABCR_A, CS5ABCR_D
-	mov.l	CS5ABCR_D, r0	! CS5ABCR data    -> R0
-	mov.l	r0, @r1		! CS5ABCR set
 
-	mov.l	CS5BBCR_A, r1	! CS5BBCR address -> R1
+	write32	CS5BBCR_A, CS5BBCR_D
-	mov.l	CS5BBCR_D, r0	! CS5BBCR data    -> R0
-	mov.l	r0, @r1		! CS5BBCR set
 
-	mov.l	CS6ABCR_A, r1	! CS6ABCR address -> R1
+	write32	CS6ABCR_A, CS6ABCR_D
-	mov.l	CS6ABCR_D, r0	! CS6ABCR data    -> R0
-	mov.l	r0, @r1		! CS6ABCR set
 
-	mov.l	CS0WCR_A, r1	! CS0WCR address -> R1
+	write32	CS0WCR_A, CS0WCR_D
-	mov.l	CS0WCR_D, r0	! CS0WCR data    -> R0
-	mov.l	r0, @r1		! CS0WCR set
 
-	mov.l	CS4WCR_A, r1	! CS4WCR address -> R1
+	write32	CS4WCR_A, CS4WCR_D
-	mov.l	CS4WCR_D, r0	! CS4WCR data    -> R0
-	mov.l	r0, @r1		! CS4WCR set
 
-	mov.l	CS5AWCR_A, r1	! CS5AWCR address -> R1
+	write32	CS5AWCR_A, CS5AWCR_D
-	mov.l	CS5AWCR_D, r0	! CS5AWCR data    -> R0
-	mov.l	r0, @r1		! CS5AWCR set
 
-	mov.l	CS5BWCR_A, r1	! CS5BWCR address -> R1
+	write32	CS5BWCR_A, CS5BWCR_D
-	mov.l	CS5BWCR_D, r0	! CS5BWCR data    -> R0
-	mov.l	r0, @r1		! CS5BWCR set
 
-	mov.l	CS6AWCR_A, r1	! CS6AWCR address -> R1
+	write32	CS6AWCR_A, CS6AWCR_D
-	mov.l	CS6AWCR_D, r0	! CS6AWCR data    -> R0
-	mov.l	r0, @r1		! CS6AWCR set
 
 	! SDRAM initialization
-	mov.l	SDCR_A, r1	! SB_SDCR address -> R1
+	write32	SDCR_A, SDCR_D
-	mov.l	SDCR_D, r0	! SB_SDCR data    -> R0
-	mov.l	r0, @r1		! SB_SDCR set
 
-	mov.l	SDWCR_A, r1	! SB_SDWCR address -> R1
+	write32	SDWCR_A, SDWCR_D
-	mov.l	SDWCR_D, r0	! SB_SDWCR data    -> R0
-	mov.l	r0, @r1		! SB_SDWCR set
 
-	mov.l	SDPCR_A, r1	! SB_SDPCR address -> R1
+	write32	SDPCR_A, SDPCR_D
-	mov.l	SDPCR_D, r0	! SB_SDPCR data    -> R0
-	mov.l	r0, @r1		! SB_SDPCR set
 
-	mov.l	RTCOR_A, r1	! SB_RTCOR address -> R1
+	write32	RTCOR_A, RTCOR_D
-	mov.l	RTCOR_D, r0	! SB_RTCOR data    -> R0
-	mov.l	r0, @r1		! SB_RTCOR set
 
-	mov.l	RTCNT_A, r1	! SB_RTCNT address -> R1
+	write32	RTCNT_A, RTCNT_D
-	mov.l	RTCNT_D, r0	! SB_RTCNT data    -> R0
-	mov.l	r0, @r1
 
-	mov.l	RTCSR_A, r1	! SB_RTCSR address -> R1
+	write32	RTCSR_A, RTCSR_D
-	mov.l	RTCSR_D, r0	! SB_RTCSR data    -> R0
-	mov.l	r0, @r1		! SB_RTCSR set
 
-	mov.l	RFCR_A, r1	! SB_RFCR address -> R1
+	write32	RFCR_A, RFCR_D
-	mov.l	RFCR_D, r0	! SB_RFCR data    -> R0
-	mov.l	r0, @r1
 
-	mov.l	SDMR3_A, r1	! SDMR3 address -> R1
+	write8	SDMR3_A, SDMR3_D
-	mov	#0x00, r0	! SDMR3 data    -> R0
-	mov.b	r0, @r1		! SDMR3 set
 
-	! BL bit off (init = ON)  (?!?)
+	! BL bit off (init = ON) (?!?)
 
 	stc	sr, r0				! BL bit off(init=ON)
 	mov.l	SR_MASK_D, r1
@@ -211,25 +154,25 @@ PFC_PULCR_D:	.long	0x6000
 PFC_DRVCR_D:	.long	0x0464
 FRQCR_D:	.long	0x07033639
 PLLCR_D:	.long	0x00005000
-DLLFRQ_D:	.long	0x000004F6	! 20080115
+DLLFRQ_D:	.long	0x000004F6
 
 CMNCR_A:	.long	CMNCR
-CMNCR_D:	.long	0x0000001B	! 20080115
+CMNCR_D:	.long	0x0000001B
-CS0BCR_A:	.long	CS0BCR		! Flash bank 1
+CS0BCR_A:	.long	CS0BCR
 CS0BCR_D:	.long	0x24920400
-CS4BCR_A:	.long	CS4BCR		!
+CS4BCR_A:	.long	CS4BCR
-CS4BCR_D:	.long	0x10003400	! 20080115
+CS4BCR_D:	.long	0x00003400
-CS5ABCR_A:	.long	CS5ABCR		!
+CS5ABCR_A:	.long	CS5ABCR
 CS5ABCR_D:	.long	0x24920400
-CS5BBCR_A:	.long	CS5BBCR		!
+CS5BBCR_A:	.long	CS5BBCR
 CS5BBCR_D:	.long	0x24920400
-CS6ABCR_A:	.long	CS6ABCR		!
+CS6ABCR_A:	.long	CS6ABCR
 CS6ABCR_D:	.long	0x24920400
 
 CS0WCR_A:	.long	CS0WCR
 CS0WCR_D:	.long	0x00000380
 CS4WCR_A:	.long	CS4WCR
-CS4WCR_D:	.long	0x00100A81	! 20080115
+CS4WCR_D:	.long	0x00110080
 CS5AWCR_A:	.long	CS5AWCR
 CS5AWCR_D:	.long	0x00000300
 CS5BWCR_A:	.long	CS5BWCR
@@ -238,20 +181,21 @@ CS6AWCR_A:	.long	CS6AWCR
 CS6AWCR_D:	.long	0x00000300
 
 SDCR_A:		.long	SBSC_SDCR
-SDCR_D:		.long	0x80160809	! 20080115
+SDCR_D:		.long	0x80160809
 SDWCR_A:	.long	SBSC_SDWCR
-SDWCR_D:	.long	0x0014450C	! 20080115
+SDWCR_D:	.long	0x0014450C
 SDPCR_A:	.long	SBSC_SDPCR
 SDPCR_D:	.long	0x00000087
 RTCOR_A:	.long	SBSC_RTCOR
 RTCNT_A:	.long	SBSC_RTCNT
 RTCNT_D:	.long	0xA55A0012
-RTCOR_D:	.long	0xA55A001C	! 20080115
+RTCOR_D:	.long	0xA55A001C
 RTCSR_A:	.long	SBSC_RTCSR
 RFCR_A:		.long	SBSC_RFCR
 RFCR_D:		.long	0xA55A0221
-RTCSR_D:	.long	0xA55A009a	! 20080115
+RTCSR_D:	.long	0xA55A009a
-SDMR3_A:	.long	0xFE581180	! 20080115
+SDMR3_A:	.long	0xFE581180
+SDMR3_D:	.long	0x0
 
 SR_MASK_D:	.long	0xEFFFFF0F
 
@@ -260,5 +204,5 @@ SR_MASK_D:	.long	0xEFFFFF0F
 SBSCR_D:	.word	0x0044
 PSCR_D:		.word	0x0000
 RWTCSR_D_1:	.word	0xA507
-RWTCSR_D_2:	.word	0xA504		! 20080115
+RWTCSR_D_2:	.word	0xA504
 RWTCNT_D:	.word	0x5A00

board/renesas/ap325rxa/lowlevel_init.S

@@ -23,6 +23,7 @@
 #include <config.h>
 #include <version.h>
 #include <asm/processor.h>
+#include <asm/macro.h>
 
 /*
  * Board specific low level init code, called _very_ early in the
@@ -38,113 +39,59 @@
 	.align	2
 
 lowlevel_init:
-	mov.l	DRVCRA_A, r1
+	write16	DRVCRA_A, DRVCRA_D
-	mov.l 	DRVCRA_D, r0
-	mov.w	r0, @r1
 
-	mov.l	DRVCRB_A, r1
+	write16	DRVCRB_A, DRVCRB_D
-	mov.l 	DRVCRB_D, r0
-	mov.w	r0, @r1
 
-	mov.l	RWTCSR_A, r1
+	write16	RWTCSR_A, RWTCSR_D1
-	mov.l 	RWTCSR_D1, r0
-	mov.w	r0, @r1
 
-	mov.l	RWTCNT_A, r1
+	write16	RWTCNT_A, RWTCNT_D
-	mov.l 	RWTCNT_D, r0
-	mov.w	r0, @r1
 
-	mov.l	RWTCSR_A, r1
+	write16	RWTCSR_A, RWTCSR_D2
-	mov.l 	RWTCSR_D2, r0
-	mov.w	r0, @r1
 
-	mov.l	FRQCR_A, r1
+	write32	FRQCR_A, FRQCR_D
-	mov.l 	FRQCR_D, r0
-	mov.l	r0, @r1
 
-	mov.l	CMNCR_A, r1
+	write32	CMNCR_A, CMNCR_D
-	mov.l	CMNCR_D, r0
-	mov.l	r0, @r1
 
-	mov.l	CS0BCR_A ,r1
+	write32	CS0BCR_A, CS0BCR_D
-	mov.l	CS0BCR_D ,r0
-	mov.l	r0, @r1
 
-	mov.l	CS4BCR_A ,r1
+	write32	CS4BCR_A, CS4BCR_D
-	mov.l	CS4BCR_D ,r0
-	mov.l	r0, @r1
 
-	mov.l	CS5ABCR_A ,r1
+	write32	CS5ABCR_A, CS5ABCR_D
-	mov.l	CS5ABCR_D ,r0
-	mov.l	r0, @r1
 
-	mov.l	CS5BBCR_A ,r1
+	write32	CS5BBCR_A, CS5BBCR_D
-	mov.l	CS5BBCR_D ,r0
-	mov.l	r0, @r1
 
-	mov.l	CS6ABCR_A ,r1
+	write32	CS6ABCR_A, CS6ABCR_D
-	mov.l	CS6ABCR_D ,r0
-	mov.l	r0, @r1
 
-	mov.l	CS6BBCR_A ,r1
+	write32	CS6BBCR_A, CS6BBCR_D
-	mov.l	CS6BBCR_D ,r0
-	mov.l	r0, @r1
 
-	mov.l	CS0WCR_A ,r1
+	write32	CS0WCR_A, CS0WCR_D
-	mov.l	CS0WCR_D ,r0
-	mov.l	r0, @r1
 
-	mov.l	CS4WCR_A ,r1
+	write32	CS4WCR_A, CS4WCR_D
-	mov.l	CS4WCR_D ,r0
-	mov.l	r0, @r1
 
-	mov.l	CS5AWCR_A ,r1
+	write32	CS5AWCR_A, CS5AWCR_D
-	mov.l	CS5AWCR_D ,r0
-	mov.l	r0, @r1
 
-	mov.l	CS5BWCR_A ,r1
+	write32	CS5BWCR_A, CS5BWCR_D
-	mov.l	CS5BWCR_D ,r0
-	mov.l	r0, @r1
 
-	mov.l	CS6AWCR_A ,r1
+	write32	CS6AWCR_A, CS6AWCR_D
-	mov.l	CS6AWCR_D ,r0
-	mov.l	r0, @r1
 
-	mov.l	CS6BWCR_A ,r1
+	write32	CS6BWCR_A, CS6BWCR_D
-	mov.l	CS6BWCR_D ,r0
-	mov.l	r0, @r1
 
-	mov.l	SBSC_SDCR_A, r1
+	write32	SBSC_SDCR_A, SBSC_SDCR_D1
-	mov.l 	SBSC_SDCR_D1, r0
-	mov.l	r0, @r1
 
-	mov.l	SBSC_SDWCR_A, r1
+	write32	SBSC_SDWCR_A, SBSC_SDWCR_D
-	mov.l 	SBSC_SDWCR_D, r0
-	mov.l	r0, @r1
 
-	mov.l	SBSC_SDPCR_A, r1
+	write32	SBSC_SDPCR_A, SBSC_SDPCR_D
-	mov.l 	SBSC_SDPCR_D, r0
-	mov.l	r0, @r1
 
-	mov.l	SBSC_RTCSR_A, r1
+	write32	SBSC_RTCSR_A, SBSC_RTCSR_D
-	mov.l 	SBSC_RTCSR_D, r0
-	mov.l	r0, @r1
 
-	mov.l	SBSC_RTCNT_A, r1
+	write32	SBSC_RTCNT_A, SBSC_RTCNT_D
-	mov.l 	SBSC_RTCNT_D, r0
-	mov.l	r0, @r1
 
-	mov.l	SBSC_RTCOR_A, r1
+	write32	SBSC_RTCOR_A, SBSC_RTCOR_D
-	mov.l 	SBSC_RTCOR_D, r0
-	mov.l	r0, @r1
 
-	mov.l	SBSC_SDMR3_A1, r1
+	write8	SBSC_SDMR3_A1, SBSC_SDMR3_D
-	mov.l 	SBSC_SDMR3_D, r0
-	mov.b	r0, @r1
 
-	mov.l	SBSC_SDMR3_A2, r1
+	write8	SBSC_SDMR3_A2, SBSC_SDMR3_D
-	mov.l 	SBSC_SDMR3_D, r0
-	mov.b	r0, @r1
 
 	mov.l	SLEEP_CNT, r1
 2:	tst	r1, r1
@@ -152,19 +99,13 @@ lowlevel_init:
 	bf/s	2b
 	dt	r1
 
-	mov.l	SBSC_SDMR3_A3, r1
+	write8	SBSC_SDMR3_A3, SBSC_SDMR3_D
-	mov.l 	SBSC_SDMR3_D, r0
-	mov.b	r0, @r1
 
-	mov.l	SBSC_SDCR_A, r1
+	write32	SBSC_SDCR_A, SBSC_SDCR_D2
-	mov.l 	SBSC_SDCR_D2, r0
-	mov.l	r0, @r1
 
-	mov.l	CCR_A, r1
+	write32	CCR_A, CCR_D
-	mov.l 	CCR_D, r0
-	mov.l	r0, @r1
 
-	! BL bit off (init = ON)  (?!?)
+	! BL bit off (init = ON) (?!?)
 
 	stc	sr, r0				! BL bit off(init=ON)
 	mov.l	SR_MASK_D, r1
@@ -211,7 +152,7 @@ SBSC_SDMR3_D:	.long	0x00
 CMNCR_A:	.long	CMNCR
 CS0BCR_A:	.long	CS0BCR
 CS4BCR_A:	.long	CS4BCR
-CS5ABCR_A:	.long 	CS5ABCR
+CS5ABCR_A:	.long	CS5ABCR
 CS5BBCR_A:	.long	CS5BBCR
 CS6ABCR_A:	.long	CS6ABCR
 CS6BBCR_A:	.long	CS6BBCR

board/renesas/r2dplus/lowlevel_init.S

@@ -8,105 +8,64 @@
 #include <version.h>
 
 #include <asm/processor.h>
+#include <asm/macro.h>
 
 	.global lowlevel_init
 	.text
-	.align  2
+	.align	2
 
 lowlevel_init:
 
-	mov.l	CCR_A, r1
+	write32	CCR_A, CCR_D_D
-	mov.l	CCR_D_D, r0
-	mov.l	r0,@r1
 
-	mov.l	MMUCR_A,r1
+	write32	MMUCR_A, MMUCR_D
-	mov.l	MMUCR_D,r0
-	mov.w	r0,@r1
 
-	mov.l	BCR1_A,r1
+	write32	BCR1_A, BCR1_D
-	mov.l	BCR1_D,r0
-	mov.l	r0,@r1
 
-	mov.l	BCR2_A,r1
+	write16	BCR2_A, BCR2_D
-	mov.l	BCR2_D,r0
-	mov.w	r0,@r1
 
-	mov.l	BCR3_A,r1
+	write16	BCR3_A, BCR3_D
-	mov.l	BCR3_D,r0
-	mov.w	r0,@r1
 
-	mov.l	BCR4_A,r1
+	write32	BCR4_A, BCR4_D
-	mov.l	BCR4_D,r0
-	mov.l	r0,@r1
 
-	mov.l	WCR1_A,r1
+	write32	WCR1_A, WCR1_D
-	mov.l	WCR1_D,r0
-	mov.l	r0,@r1
 
-	mov.l	WCR2_A,r1
+	write32	WCR2_A, WCR2_D
-	mov.l	WCR2_D,r0
-	mov.l	r0,@r1
 
-	mov.l	WCR3_A,r1
+	write32	WCR3_A, WCR3_D
-	mov.l	WCR3_D,r0
-	mov.l	r0,@r1
 
-	mov.l	PCR_A,r1
+	write16	PCR_A, PCR_D
-	mov.l	PCR_D,r0
-	mov.w	r0,@r1
 
-	mov.l	LED_A,r1
+	write16	LED_A, LED_D
-	mov	#0xff,r0
-	mov.w	r0,@r1
 
-	mov.l	MCR_A,r1
+	write32	MCR_A, MCR_D1
-	mov.l	MCR_D1,r0
-	mov.l	r0,@r1
 
-	mov.l	RTCNT_A,r1
+	write16	RTCNT_A, RTCNT_D
-	mov.l	RTCNT_D,r0
-	mov.w	r0,@r1
 
-	mov.l	RTCOR_A,r1
+	write16	RTCOR_A, RTCOR_D
-	mov.l	RTCOR_D,r0
-	mov.w	r0,@r1
 
-	mov.l	RFCR_A,r1
+	write16	RFCR_A, RFCR_D
-	mov.l	RFCR_D,r0
-	mov.w	r0,@r1
 
-	mov.l	RTCSR_A,r1
+	write16	RTCSR_A, RTCSR_D
-	mov.l	RTCSR_D,r0
-	mov.w	r0,@r1
 
-	mov.l	SDMR3_A,r1
+	write8	SDMR3_A, SDMR3_D0
-	mov	#0x55,r0
-	mov.b	r0,@r1
 
 	/* Wait DRAM refresh 30 times */
-	mov.l	RFCR_A,r1
+	mov.l	RFCR_A, r1
-	mov	#30,r3
+	mov	#30, r3
 1:
-	mov.w	@r1,r0
+	mov.w	@r1, r0
-	extu.w	r0,r2
+	extu.w	r0, r2
-	cmp/hi	r3,r2
+	cmp/hi	r3, r2
 	bf	1b
 
-	mov.l	MCR_A,r1
+	write32	MCR_A, MCR_D2
-	mov.l	MCR_D2,r0
-	mov.l	r0,@r1
 
-	mov.l	SDMR3_A,r1
+	write8	SDMR3_A, SDMR3_D1
-	mov	#0,r0
-	mov.b	r0,@r1
 
-	mov.l	IRLMASK_A,r1
+	write32	IRLMASK_A, IRLMASK_D
-	mov.l	IRLMASK_D,r0
-	mov.l	r0,@r1
 
-	mov.l	CCR_A, r1
+	write32	CCR_A, CCR_D_E
-	mov.l	CCR_D_E, r0
-	mov.l	r0, @r1
 
 	rts
 	nop
@@ -118,34 +77,36 @@ CCR_D_E:	.long	0x8000090B
 
 FRQCR_A:	.long	FRQCR		/* FRQCR Address */
 FRQCR_D:	.long	0x00000e0a	/* 03/07/15 modify */
-BCR1_A:	.long	BCR1		/* BCR1 Address */
+BCR1_A:		.long	BCR1		/* BCR1 Address */
-BCR1_D:	.long	0x00180008
+BCR1_D:		.long	0x00180008
-BCR2_A:	.long	BCR2		/* BCR2 Address */
+BCR2_A:		.long	BCR2		/* BCR2 Address */
-BCR2_D:	.long   0xabe8
+BCR2_D:		.long	0xabe8
-BCR3_A:	.long	BCR3		/* BCR3 Address */
+BCR3_A:		.long	BCR3		/* BCR3 Address */
-BCR3_D:	.long	0x0000
+BCR3_D:		.long	0x0000
-BCR4_A:	.long	BCR4		/* BCR4 Address */
+BCR4_A:		.long	BCR4		/* BCR4 Address */
-BCR4_D:	.long	0x00000010
+BCR4_D:		.long	0x00000010
-WCR1_A:	.long	WCR1		/* WCR1 Address */
+WCR1_A:		.long	WCR1		/* WCR1 Address */
-WCR1_D:	.long	0x33343333
+WCR1_D:		.long	0x33343333
-WCR2_A:	.long	WCR2		/* WCR2 Address */
+WCR2_A:		.long	WCR2		/* WCR2 Address */
-WCR2_D:	.long	0xcff86fbf
+WCR2_D:		.long	0xcff86fbf
-WCR3_A:	.long	WCR3		/* WCR3 Address */
+WCR3_A:		.long	WCR3		/* WCR3 Address */
-WCR3_D:	.long	0x07777707
+WCR3_D:		.long	0x07777707
 LED_A:		.long	0x04000036	/* LED Address */
+LED_D:		.long	0xFF		/* LED Data */
 RTCNT_A:	.long	RTCNT		/* RTCNT Address */
 RTCNT_D:	.long	0xA500		/* RTCNT Write Code A5h Data 00h */
 RTCOR_A:	.long	RTCOR		/* RTCOR Address */
-RTCOR_D:	.long	0xA534		/* RTCOR Write Code  */
+RTCOR_D:	.long	0xA534		/* RTCOR Write Code */
 RTCSR_A:	.long	RTCSR		/* RTCSR Address */
 RTCSR_D:	.long	0xA510		/* RTCSR Write Code */
-SDMR3_A:	.long   0xFF9400CC	/* SDMR3 Address */
+SDMR3_A:	.long	0xFF9400CC	/* SDMR3 Address */
-SDMR3_D:	.long	0x55
+SDMR3_D0:	.long	0x55
+SDMR3_D1:	.long	0x00
 MCR_A:		.long	MCR		/* MCR Address */
-MCR_D1:	.long	0x081901F4	/* MRSET:'0' */
+MCR_D1:		.long	0x081901F4	/* MRSET:'0' */
-MCR_D2:	.long	0x481901F4	/* MRSET:'1' */
+MCR_D2:		.long	0x481901F4	/* MRSET:'1' */
-RFCR_A:	.long	RFCR		/* RFCR Address */
+RFCR_A:		.long	RFCR		/* RFCR Address */
-RFCR_D:	.long	0xA400		/* RFCR Write Code A4h Data 00h */
+RFCR_D:		.long	0xA400		/* RFCR Write Code A4h Data 00h */
 PCR_A:		.long	PCR		/* PCR Address */
 PCR_D:		.long	0x0000
 MMUCR_A:	.long	MMUCR		/* MMUCCR Address */

board/renesas/r7780mp/lowlevel_init.S

@@ -22,13 +22,14 @@
 #include <config.h>
 #include <version.h>
 #include <asm/processor.h>
+#include <asm/macro.h>
 
 /*
- *  Board specific low level init code, called _very_ early in the
+ * Board specific low level init code, called _very_ early in the
- *  startup sequence. Relocation to SDRAM has not happened yet, no
+ * startup sequence. Relocation to SDRAM has not happened yet, no
- *  stack is available, bss section has not been initialised, etc.
+ * stack is available, bss section has not been initialised, etc.
  *
- *  (Note: As no stack is available, no subroutines can be called...).
+ * (Note: As no stack is available, no subroutines can be called...).
  */
 
 	.global	lowlevel_init
@@ -38,63 +39,36 @@
 
 lowlevel_init:
 
-	mov.l	CCR_A, r1	/* Address of Cache Control Register */
+	write32	CCR_A, CCR_D		/* Address of Cache Control Register */
-	mov.l	CCR_D, r0	/* Instruction Cache Invalidate */
+					/* Instruction Cache Invalidate */
-	mov.l	r0, @r1
 
-	mov.l	FRQCR_A, r1	/* Frequency control register */
+	write32	FRQCR_A, FRQCR_D	/* Frequency control register */
-	mov.l	FRQCR_D, r0
-	mov.l	r0, @r1
 
 	/* pin_multi_setting */
-	mov.l   BBG_PMMR_A,r1
+	write32	BBG_PMMR_A, BBG_PMMR_D_PMSR1
-	mov.l   BBG_PMMR_D_PMSR1,r0
-	mov.l   r0,@r1
 
-	mov.l   BBG_PMSR1_A,r1
+	write32	BBG_PMSR1_A, BBG_PMSR1_D
-	mov.l   BBG_PMSR1_D,r0
-	mov.l   r0,@r1
 
-	mov.l   BBG_PMMR_A,r1
+	write32	BBG_PMMR_A, BBG_PMMR_D_PMSR2
-	mov.l   BBG_PMMR_D_PMSR2,r0
-	mov.l   r0,@r1
 
-	mov.l   BBG_PMSR2_A,r1
+	write32	BBG_PMSR2_A, BBG_PMSR2_D
-	mov.l   BBG_PMSR2_D,r0
-	mov.l   r0,@r1
 
-	mov.l   BBG_PMMR_A,r1
+	write32	BBG_PMMR_A, BBG_PMMR_D_PMSR3
-	mov.l   BBG_PMMR_D_PMSR3,r0
-	mov.l   r0,@r1
 
-	mov.l   BBG_PMSR3_A,r1
+	write32	BBG_PMSR3_A, BBG_PMSR3_D
-	mov.l   BBG_PMSR3_D,r0
-	mov.l   r0,@r1
 
-	mov.l   BBG_PMMR_A,r1
+	write32	BBG_PMMR_A, BBG_PMMR_D_PMSR4
-	mov.l   BBG_PMMR_D_PMSR4,r0
-	mov.l   r0,@r1
 
-	mov.l   BBG_PMSR4_A,r1
+	write32	BBG_PMSR4_A, BBG_PMSR4_D
-	mov.l   BBG_PMSR4_D,r0
-	mov.l   r0,@r1
 
-	mov.l   BBG_PMMR_A,r1
+	write32	BBG_PMMR_A, BBG_PMMR_D_PMSRG
-	mov.l   BBG_PMMR_D_PMSRG,r0
-	mov.l   r0,@r1
 
-	mov.l   BBG_PMSRG_A,r1
+	write32	BBG_PMSRG_A, BBG_PMSRG_D
-	mov.l   BBG_PMSRG_D,r0
-	mov.l   r0,@r1
 
 	/* cpg_setting */
-	mov.l   FRQCR_A,r1
+	write32	FRQCR_A, FRQCR_D
-	mov.l   FRQCR_D,r0
-	mov.l   r0,@r1
 
-	mov.l   DLLCSR_A,r1
+	write32	DLLCSR_A, DLLCSR_D
-	mov.l   DLLCSR_D,r0
-	mov.l   r0,@r1
 
 	nop
 	nop
@@ -108,111 +82,79 @@ lowlevel_init:
 	nop
 
 	/* wait 200us */
-	mov.l   REPEAT0_R3,r3
+	mov.l	REPEAT0_R3, r3
-	mov     #0,r2
+	mov	#0, r2
 repeat0:
-	add     #1,r2
+	add	#1, r2
-	cmp/hs  r3,r2
+	cmp/hs	r3, r2
-	bf      repeat0
+	bf	repeat0
 	nop
 
 	/* bsc_setting */
-	mov.l	MMSELR_A,r1
+	write32	MMSELR_A, MMSELR_D
-	mov.l	MMSELR_D,r0
-	mov.l	r0,@r1
 
-	mov.l	BCR_A,r1
+	write32	BCR_A, BCR_D
-	mov.l	BCR_D,r0
-	mov.l	r0,@r1
 
-	mov.l	CS0BCR_A,r1
+	write32	CS0BCR_A, CS0BCR_D
-	mov.l	CS0BCR_D,r0
-	mov.l	r0,@r1
 
-	mov.l	CS1BCR_A,r1
+	write32	CS1BCR_A, CS1BCR_D
-	mov.l	CS1BCR_D,r0
-	mov.l	r0,@r1
 
-	mov.l	CS2BCR_A,r1
+	write32	CS2BCR_A, CS2BCR_D
-	mov.l	CS2BCR_D,r0
-	mov.l	r0,@r1
 
-	mov.l	CS4BCR_A,r1
+	write32	CS4BCR_A, CS4BCR_D
-	mov.l	CS4BCR_D,r0
-	mov.l	r0,@r1
 
-	mov.l	CS5BCR_A,r1
+	write32	CS5BCR_A, CS5BCR_D
-	mov.l	CS5BCR_D,r0
-	mov.l	r0,@r1
 
-	mov.l	CS6BCR_A,r1
+	write32	CS6BCR_A, CS6BCR_D
-	mov.l	CS6BCR_D,r0
-	mov.l	r0,@r1
 
-	mov.l	CS0WCR_A,r1
+	write32	CS0WCR_A, CS0WCR_D
-	mov.l	CS0WCR_D,r0
-	mov.l	r0,@r1
 
-	mov.l	CS1WCR_A,r1
+	write32	CS1WCR_A, CS1WCR_D
-	mov.l	CS1WCR_D,r0
-	mov.l	r0,@r1
 
-	mov.l	CS2WCR_A,r1
+	write32	CS2WCR_A, CS2WCR_D
-	mov.l	CS2WCR_D,r0
-	mov.l	r0,@r1
 
-	mov.l	CS4WCR_A,r1
+	write32	CS4WCR_A, CS4WCR_D
-	mov.l	CS4WCR_D,r0
-	mov.l	r0,@r1
 
-	mov.l	CS5WCR_A,r1
+	write32	CS5WCR_A, CS5WCR_D
-	mov.l	CS5WCR_D,r0
-	mov.l	r0,@r1
 
-	mov.l	CS6WCR_A,r1
+	write32	CS6WCR_A, CS6WCR_D
-	mov.l	CS6WCR_D,r0
-	mov.l	r0,@r1
 
-	mov.l	CS5PCR_A,r1
+	write32	CS5PCR_A, CS5PCR_D
-	mov.l	CS5PCR_D,r0
-	mov.l	r0,@r1
 
-	mov.l	CS6PCR_A,r1
+	write32	CS6PCR_A, CS6PCR_D
-	mov.l	CS6PCR_D,r0
-	mov.l	r0,@r1
 
 	/* ddr_setting */
 	/* wait 200us */
-	mov.l   REPEAT0_R3,r3
+	mov.l	REPEAT0_R3, r3
-	mov     #0,r2
+	mov	#0, r2
 repeat1:
-	add     #1,r2
+	add	#1, r2
-	cmp/hs  r3,r2
+	cmp/hs	r3, r2
-	bf      repeat1
+	bf	repeat1
 	nop
 
-	mov.l   MIM_U_A,r0
+	mov.l	MIM_U_A, r0
-	mov.l   MIM_U_D,r1
+	mov.l	MIM_U_D, r1
 	synco
-	mov.l   r1,@r0
+	mov.l	r1, @r0
 	synco
 
-	mov.l	MIM_L_A,r0
+	mov.l	MIM_L_A, r0
-	mov.l	MIM_L_D0,r1
+	mov.l	MIM_L_D0, r1
 	synco
-	mov.l	r1,@r0
+	mov.l	r1, @r0
 	synco
 
-	mov.l   STR_L_A,r0
+	mov.l	STR_L_A, r0
-	mov.l   STR_L_D,r1
+	mov.l	STR_L_D, r1
 	synco
-	mov.l   r1,@r0
+	mov.l	r1, @r0
 	synco
 
-	mov.l   SDR_L_A,r0
+	mov.l	SDR_L_A, r0
-	mov.l   SDR_L_D,r1
+	mov.l	SDR_L_D, r1
 	synco
-	mov.l   r1,@r0
+	mov.l	r1, @r0
 	synco
 
 	nop
@@ -220,193 +162,193 @@ repeat1:
 	nop
 	nop
 
-	mov.l   SCR_L_A,r0
+	mov.l	SCR_L_A, r0
-	mov.l   SCR_L_D0,r1
+	mov.l	SCR_L_D0, r1
 	synco
-	mov.l   r1,@r0
+	mov.l	r1, @r0
 	synco
 
-	mov.l   SCR_L_A,r0
+	mov.l	SCR_L_A, r0
-	mov.l   SCR_L_D1,r1
+	mov.l	SCR_L_D1, r1
 	synco
-	mov.l   r1,@r0
+	mov.l	r1, @r0
 	synco
 
 	nop
 	nop
 	nop
 
-	mov.l   EMRS_A,r0
+	mov.l	EMRS_A, r0
-	mov.l   EMRS_D,r1
+	mov.l	EMRS_D, r1
 	synco
-	mov.l   r1,@r0
+	mov.l	r1, @r0
 	synco
 
 	nop
 	nop
 	nop
 
-	mov.l   MRS1_A,r0
+	mov.l	MRS1_A, r0
-	mov.l   MRS1_D,r1
+	mov.l	MRS1_D, r1
 	synco
-	mov.l   r1,@r0
+	mov.l	r1, @r0
 	synco
 
 	nop
 	nop
 	nop
 
-	mov.l   SCR_L_A,r0
+	mov.l	SCR_L_A, r0
-	mov.l   SCR_L_D2,r1
+	mov.l	SCR_L_D2, r1
 	synco
-	mov.l   r1,@r0
+	mov.l	r1, @r0
 	synco
 
 	nop
 	nop
 	nop
 
-	mov.l   SCR_L_A,r0
+	mov.l	SCR_L_A, r0
-	mov.l   SCR_L_D3,r1
+	mov.l	SCR_L_D3, r1
 	synco
-	mov.l   r1,@r0
+	mov.l	r1, @r0
 	synco
 
 	nop
 	nop
 	nop
 
-	mov.l   SCR_L_A,r0
+	mov.l	SCR_L_A, r0
-	mov.l   SCR_L_D4,r1
+	mov.l	SCR_L_D4, r1
 	synco
-	mov.l   r1,@r0
+	mov.l	r1, @r0
 	synco
 
 	nop
 	nop
 	nop
 
-	mov.l   MRS2_A,r0
+	mov.l	MRS2_A, r0
-	mov.l   MRS2_D,r1
+	mov.l	MRS2_D, r1
 	synco
-	mov.l   r1,@r0
+	mov.l	r1, @r0
 	synco
 
 	nop
 	nop
 	nop
 
-	mov.l   SCR_L_A,r0
+	mov.l	SCR_L_A, r0
-	mov.l   SCR_L_D5,r1
+	mov.l	SCR_L_D5, r1
 	synco
-	mov.l   r1,@r0
+	mov.l	r1, @r0
 	synco
 
 	/* wait 200us */
-	mov.l   REPEAT0_R1,r3
+	mov.l	REPEAT0_R1, r3
-	mov     #0,r2
+	mov	#0, r2
 repeat2:
-	add     #1,r2
+	add	#1, r2
-	cmp/hs  r3,r2
+	cmp/hs	r3, r2
-	bf      repeat2
+	bf	repeat2
 
 	synco
 
-	mov.l   MIM_L_A,r0
+	mov.l	MIM_L_A, r0
-	mov.l   MIM_L_D1,r1
+	mov.l	MIM_L_D1, r1
 	synco
-	mov.l   r1,@r0
+	mov.l	r1, @r0
 	synco
 
 	rts
 	nop
 	.align	4
 
-RWTCSR_D_1:				.word	0xA507
+RWTCSR_D_1:		.word	0xA507
-RWTCSR_D_2:				.word	0xA507
+RWTCSR_D_2:		.word	0xA507
-RWTCNT_D:				.word	0x5A00
+RWTCNT_D:		.word	0x5A00
 	.align	2
 
-BBG_PMMR_A:				.long	0xFF800010
+BBG_PMMR_A:		.long	0xFF800010
-BBG_PMSR1_A:			.long	0xFF800014
+BBG_PMSR1_A:		.long	0xFF800014
-BBG_PMSR2_A:			.long	0xFF800018
+BBG_PMSR2_A:		.long	0xFF800018
-BBG_PMSR3_A:			.long	0xFF80001C
+BBG_PMSR3_A:		.long	0xFF80001C
-BBG_PMSR4_A:			.long	0xFF800020
+BBG_PMSR4_A:		.long	0xFF800020
-BBG_PMSRG_A:			.long	0xFF800024
+BBG_PMSRG_A:		.long	0xFF800024
 
-BBG_PMMR_D_PMSR1:       .long	0xffffbffd
+BBG_PMMR_D_PMSR1:	.long	0xffffbffd
-BBG_PMSR1_D:            .long	0x00004002
+BBG_PMSR1_D:		.long	0x00004002
-BBG_PMMR_D_PMSR2:       .long	0xfc21a7ff
+BBG_PMMR_D_PMSR2:	.long	0xfc21a7ff
-BBG_PMSR2_D:            .long	0x03de5800
+BBG_PMSR2_D:		.long	0x03de5800
-BBG_PMMR_D_PMSR3:       .long	0xfffffff8
+BBG_PMMR_D_PMSR3:	.long	0xfffffff8
-BBG_PMSR3_D:            .long	0x00000007
+BBG_PMSR3_D:		.long	0x00000007
-BBG_PMMR_D_PMSR4:       .long	0xdffdfff9
+BBG_PMMR_D_PMSR4:	.long	0xdffdfff9
-BBG_PMSR4_D:            .long	0x20020006
+BBG_PMSR4_D:		.long	0x20020006
-BBG_PMMR_D_PMSRG:       .long	0xffffffff
+BBG_PMMR_D_PMSRG:	.long	0xffffffff
-BBG_PMSRG_D:            .long	0x00000000
+BBG_PMSRG_D:		.long	0x00000000
 
-FRQCR_A:				.long	FRQCR
+FRQCR_A:		.long	FRQCR
-DLLCSR_A:				.long	0xffc40010
+DLLCSR_A:		.long	0xffc40010
-FRQCR_D:				.long	0x40233035
+FRQCR_D:		.long	0x40233035
-DLLCSR_D:				.long	0x00000000
+DLLCSR_D:		.long	0x00000000
 
 /* for DDR-SDRAM */
-MIM_U_A:				.long	MIM_1
+MIM_U_A:		.long	MIM_1
-MIM_L_A:				.long	MIM_2
+MIM_L_A:		.long	MIM_2
-SCR_U_A:				.long	SCR_1
+SCR_U_A:		.long	SCR_1
-SCR_L_A:				.long	SCR_2
+SCR_L_A:		.long	SCR_2
-STR_U_A:				.long	STR_1
+STR_U_A:		.long	STR_1
-STR_L_A:				.long	STR_2
+STR_L_A:		.long	STR_2
-SDR_U_A:				.long	SDR_1
+SDR_U_A:		.long	SDR_1
-SDR_L_A:				.long	SDR_2
+SDR_L_A:		.long	SDR_2
 
-EMRS_A:					.long	0xFEC02000
+EMRS_A:			.long	0xFEC02000
-MRS1_A:					.long	0xFEC00B08
+MRS1_A:			.long	0xFEC00B08
-MRS2_A:					.long	0xFEC00308
+MRS2_A:			.long	0xFEC00308
 
-MIM_U_D:				.long	0x00004000
+MIM_U_D:		.long	0x00004000
-MIM_L_D0:				.long	0x03e80009
+MIM_L_D0:		.long	0x03e80009
-MIM_L_D1:				.long	0x03e80209
+MIM_L_D1:		.long	0x03e80209
-SCR_L_D0:				.long	0x3
+SCR_L_D0:		.long	0x3
-SCR_L_D1:				.long	0x2
+SCR_L_D1:		.long	0x2
-SCR_L_D2:				.long	0x2
+SCR_L_D2:		.long	0x2
-SCR_L_D3:				.long	0x4
+SCR_L_D3:		.long	0x4
-SCR_L_D4:				.long	0x4
+SCR_L_D4:		.long	0x4
-SCR_L_D5:				.long	0x0
+SCR_L_D5:		.long	0x0
-STR_L_D:				.long	0x000f0000
+STR_L_D:		.long	0x000f0000
-SDR_L_D:				.long	0x00000400
+SDR_L_D:		.long	0x00000400
-EMRS_D:					.long	0x0
+EMRS_D:			.long	0x0
-MRS1_D:					.long	0x0
+MRS1_D:			.long	0x0
-MRS2_D:					.long	0x0
+MRS2_D:			.long	0x0
 
 /* Cache Controller */
-CCR_A:		.long	CCR
+CCR_A:			.long	CCR
-MMUCR_A:	.long	MMUCR
+MMUCR_A:		.long	MMUCR
-RWTCNT_A:	.long	WTCNT
+RWTCNT_A:		.long	WTCNT
 
-CCR_D:		.long	0x0000090b
+CCR_D:			.long	0x0000090b
-CCR_D_2:	.long	0x00000103
+CCR_D_2:		.long	0x00000103
-MMUCR_D:	.long	0x00000004
+MMUCR_D:		.long	0x00000004
-MSTPCR0_D:	.long	0x00001001
+MSTPCR0_D:		.long	0x00001001
-MSTPCR2_D:	.long	0xffffffff
+MSTPCR2_D:		.long	0xffffffff
 
 /* local Bus State Controller */
-MMSELR_A:   .long   MMSELR
+MMSELR_A:		.long	MMSELR
-BCR_A:      .long   BCR
+BCR_A:			.long	BCR
-CS0BCR_A:   .long   CS0BCR
+CS0BCR_A:		.long	CS0BCR
-CS1BCR_A:   .long   CS1BCR
+CS1BCR_A:		.long	CS1BCR
-CS2BCR_A:   .long   CS2BCR
+CS2BCR_A:		.long	CS2BCR
-CS4BCR_A:   .long   CS4BCR
+CS4BCR_A:		.long	CS4BCR
-CS5BCR_A:   .long   CS5BCR
+CS5BCR_A:		.long	CS5BCR
-CS6BCR_A:   .long   CS6BCR
+CS6BCR_A:		.long	CS6BCR
-CS0WCR_A:   .long   CS0WCR
+CS0WCR_A:		.long	CS0WCR
-CS1WCR_A:   .long   CS1WCR
+CS1WCR_A:		.long	CS1WCR
-CS2WCR_A:   .long   CS2WCR
+CS2WCR_A:		.long	CS2WCR
-CS4WCR_A:   .long   CS4WCR
+CS4WCR_A:		.long	CS4WCR
-CS5WCR_A:   .long   CS5WCR
+CS5WCR_A:		.long	CS5WCR
-CS6WCR_A:   .long   CS6WCR
+CS6WCR_A:		.long	CS6WCR
-CS5PCR_A:   .long   CS5PCR
+CS5PCR_A:		.long	CS5PCR
-CS6PCR_A:   .long   CS6PCR
+CS6PCR_A:		.long	CS6PCR
 
 MMSELR_D:		.long	0xA5A50003
 BCR_D:			.long	0x00000000
@@ -425,5 +367,5 @@ CS6WCR_D:		.long	0x77777703
 CS5PCR_D:		.long	0x77000000
 CS6PCR_D:		.long	0x77000000
 
-REPEAT0_R3:	.long   0x00002000
+REPEAT0_R3:		.long	0x00002000
-REPEAT0_R1:	.long   0x0000200
+REPEAT0_R1:		.long	0x0000200

board/renesas/rsk7203/Makefile

@@ -26,6 +26,10 @@ LIB	= lib$(BOARD).a
 OBJS	:= rsk7203.o
 SOBJS	:= lowlevel_init.o
 
+LIB	:= $(addprefix $(obj),$(LIB))
+OBJS	:= $(addprefix $(obj),$(OBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
 $(LIB):	$(obj).depend $(OBJS) $(SOBJS)
 	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
 

board/renesas/rsk7203/lowlevel_init.S

@@ -21,6 +21,7 @@
 #include <version.h>
 
 #include <asm/processor.h>
+#include <asm/macro.h>
 
 	.global	lowlevel_init
 
@@ -29,153 +30,89 @@
 
 lowlevel_init:
 	/* Cache setting */
-	mov.l CCR1_A ,r1
+	write32	CCR1_A ,CCR1_D
-	mov.l CCR1_D ,r0
-	mov.l r0,@r1
 
 	/* ConfigurePortPins */
-	mov.l PECRL3_A, r1
+	write16	PECRL3_A, PECRL3_D
-	mov.l PECRL3_D, r0
-	mov.w r0,@r1
 
-	mov.l PCCRL4_A, r1
+	write16	PCCRL4_A, PCCRL4_D0
-	mov.l PCCRL4_D0, r0
-	mov.w r0,@r1
 
-	mov.l PECRL4_A, r1
+	write16	PECRL4_A, PECRL4_D0
-	mov.l PECRL4_D0, r0
-	mov.w r0,@r1
 
-	mov.l PEIORL_A, r1
+	write16	PEIORL_A, PEIORL_D0
-	mov.l PEIORL_D0, r0
-	mov.w r0,@r1
 
-	mov.l PCIORL_A, r1
+	write16	PCIORL_A, PCIORL_D
-	mov.l PCIORL_D, r0
-	mov.w r0,@r1
 
-	mov.l PFCRH2_A, r1
+	write16	PFCRH2_A, PFCRH2_D
-	mov.l PFCRH2_D, r0
-	mov.w r0,@r1
 
-	mov.l PFCRH3_A, r1
+	write16	PFCRH3_A, PFCRH3_D
-	mov.l PFCRH3_D, r0
-	mov.w r0,@r1
 
-	mov.l PFCRH1_A, r1
+	write16	PFCRH1_A, PFCRH1_D
-	mov.l PFCRH1_D, r0
-	mov.w r0,@r1
 
-	mov.l PFIORH_A, r1
+	write16	PFIORH_A, PFIORH_D
-	mov.l PFIORH_D, r0
-	mov.w r0,@r1
 
-	mov.l PECRL1_A, r1
+	write16	PECRL1_A, PECRL1_D0
-	mov.l PECRL1_D0, r0
-	mov.w r0,@r1
 
-	mov.l PEIORL_A, r1
+	write16	PEIORL_A, PEIORL_D1
-	mov.l PEIORL_D1, r0
-	mov.w r0,@r1
 
 	/* Configure Operating Frequency */
-	mov.l WTCSR_A ,r1
+	write16	WTCSR_A, WTCSR_D0
-	mov.l WTCSR_D0 ,r0
-	mov.w r0,@r1
 
-	mov.l WTCSR_A ,r1
+	write16	WTCSR_A, WTCSR_D1
-	mov.l WTCSR_D1 ,r0
-	mov.w r0,@r1
 
-	mov.l WTCNT_A ,r1
+	write16	WTCNT_A, WTCNT_D
-	mov.l WTCNT_D ,r0
-	mov.w r0,@r1
 
 	/* Set clock mode*/
-	mov.l FRQCR_A,r1
+	write16	FRQCR_A, FRQCR_D
-	mov.l FRQCR_D,r0
-	mov.w r0,@r1
 
 	/* Configure Bus And Memory */
 init_bsc_cs0:
-	mov.l   PCCRL4_A,r1
+	write16	PCCRL4_A, PCCRL4_D1
-	mov.l   PCCRL4_D1,r0
-	mov.w   r0,@r1
 
-	mov.l   PECRL1_A,r1
+	write16	PECRL1_A, PECRL1_D1
-	mov.l   PECRL1_D1,r0
-	mov.w   r0,@r1
 
-	mov.l CMNCR_A,r1
+	write32	CMNCR_A, CMNCR_D
-	mov.l CMNCR_D,r0
-	mov.l r0,@r1
 
-	mov.l SC0BCR_A,r1
+	write32	SC0BCR_A, SC0BCR_D
-	mov.l SC0BCR_D,r0
-	mov.l r0,@r1
 
-	mov.l CS0WCR_A,r1
+	write32	CS0WCR_A, CS0WCR_D
-	mov.l CS0WCR_D,r0
-	mov.l r0,@r1
 
 init_bsc_cs1:
-	mov.l   PECRL4_A,r1
+	write16	PECRL4_A, PECRL4_D1
-	mov.l   PECRL4_D1,r0
-	mov.w   r0,@r1
 
-	mov.l CS1WCR_A,r1
+	write32	CS1WCR_A, CS1WCR_D
-	mov.l CS1WCR_D,r0
-	mov.l r0,@r1
 
 init_sdram:
-	mov.l	PCCRL2_A,r1
+	write16	PCCRL2_A, PCCRL2_D
-	mov.l	PCCRL2_D,r0
-	mov.w	r0,@r1
 
-	mov.l	PCCRL4_A,r1
+	write16	PCCRL4_A, PCCRL4_D2
-	mov.l	PCCRL4_D2,r0
-	mov.w   r0,@r1
 
-	mov.l   PCCRL1_A,r1
+	write16	PCCRL1_A, PCCRL1_D
-	mov.l	PCCRL1_D,r0
-	mov.w   r0,@r1
 
-	mov.l   PCCRL3_A,r1
+	write16	PCCRL3_A, PCCRL3_D
-	mov.l	PCCRL3_D,r0
-	mov.w   r0,@r1
 
-	mov.l CS3BCR_A,r1
+	write32	CS3BCR_A, CS3BCR_D
-	mov.l CS3BCR_D,r0
-	mov.l r0,@r1
 
-	mov.l CS3WCR_A,r1
+	write32	CS3WCR_A, CS3WCR_D
-	mov.l CS3WCR_D,r0
-	mov.l r0,@r1
 
-	mov.l SDCR_A,r1
+	write32	SDCR_A, SDCR_D
-	mov.l SDCR_D,r0
-	mov.l r0,@r1
 
-	mov.l RTCOR_A,r1
+	write32	RTCOR_A, RTCOR_D
-	mov.l RTCOR_D,r0
-	mov.l r0,@r1
 
-	mov.l RTCSR_A,r1
+	write32	RTCSR_A, RTCSR_D
-	mov.l RTCSR_D,r0
-	mov.l r0,@r1
 
 	/* wait 200us */
-	mov.l   REPEAT_D,r3
+	mov.l	REPEAT_D, r3
-	mov     #0,r2
+	mov	#0, r2
 repeat0:
-	add     #1,r2
+	add	#1, r2
-	cmp/hs  r3,r2
+	cmp/hs	r3, r2
-	bf      repeat0
+	bf	repeat0
 	nop
 
-	mov.l SDRAM_MODE, r1
+	mov.l	SDRAM_MODE, r1
-	mov   #0,r0
+	mov	#0, r0
-	mov.l r0, @r1
+	mov.l	r0, @r1
 
 	nop
 	rts
@@ -208,8 +145,8 @@ PECRL1_D0:	.long 0x00000033
 
 
 WTCSR_A:	.long 0xFFFE0000
-WTCSR_D0: 	.long 0x0000A518
+WTCSR_D0:	.long 0x0000A518
-WTCSR_D1: 	.long 0x0000A51D
+WTCSR_D1:	.long 0x0000A51D
 WTCNT_A:	.long 0xFFFE0002
 WTCNT_D:	.long 0x00005A84
 FRQCR_A:	.long 0xFFFE0010
@@ -259,7 +196,7 @@ STBCR4_A:	.long 0xFFFE040C
 STBCR4_D:	.long 0x00000008
 STBCR5_A:	.long 0xFFFE0410
 STBCR5_D:	.long 0x00000000
-STBCR6_A: 	.long 0xFFFE0414
+STBCR6_A:	.long 0xFFFE0414
 STBCR6_D:	.long 0x00000002
 SDRAM_MODE:	.long 0xFFFC5040
 REPEAT_D:	.long 0x00009C40

board/renesas/sh7763rdp/lowlevel_init.S

@@ -25,6 +25,7 @@
 #include <version.h>
 
 #include <asm/processor.h>
+#include <asm/macro.h>
 
 	.global	lowlevel_init
 
@@ -33,218 +34,141 @@
 
 lowlevel_init:
 
-	mov.l   WDTCSR_A, r1	/* Watchdog Control / Status Register */
+	write32	WDTCSR_A, WDTCSR_D	/* Watchdog Control / Status Register */
-	mov.l   WDTCSR_D, r0
-	mov.l   r0, @r1
 
-	mov.l   WDTST_A, r1		/* Watchdog Stop Time Register */
+	write32	WDTST_A, WDTST_D	/* Watchdog Stop Time Register */
-	mov.l   WDTST_D, r0
-	mov.l   r0, @r1
 
-	mov.l   WDTBST_A, r1	/* 0xFFCC0008 (Watchdog Base Stop Time Register */
+	write32	WDTBST_A, WDTBST_D	/*
-	mov.l   WDTBST_D, r0
+					 * 0xFFCC0008
-	mov.l   r0, @r1
+					 * Watchdog Base Stop Time Register
+					 */
 
-	mov.l	CCR_A, r1		/* Address of Cache Control Register */
+	write32	CCR_A, CCR_CACHE_ICI_D	/* Address of Cache Control Register */
-	mov.l	CCR_CACHE_ICI_D, r0	/* Instruction Cache Invalidate */
+					/* Instruction Cache Invalidate */
-	mov.l	r0, @r1
 
-	mov.l	MMUCR_A, r1		/* Address of MMU Control Register */
+	write32	MMUCR_A, MMU_CONTROL_TI_D	/* MMU Control Register */
-	mov.l	MMU_CONTROL_TI_D, r0	/* TI == TLB Invalidate bit */
+						/* TI == TLB Invalidate bit */
-	mov.l	r0, @r1
 
-	mov.l	MSTPCR0_A, r1	/* Address of Power Control Register 0 */
+	write32	MSTPCR0_A, MSTPCR0_D	/* Address of Power Control Register 0 */
-	mov.l	MSTPCR0_D, r0
-	mov.l	r0, @r1
 
-	mov.l	MSTPCR1_A, r1	/*i Address of Power Control Register 1 */
+	write32	MSTPCR1_A, MSTPCR1_D	/* Address of Power Control Register 1 */
-	mov.l	MSTPCR1_D, r0
-	mov.l	r0, @r1
 
-	mov.l	RAMCR_A,r1
+	write32	RAMCR_A, RAMCR_D
-	mov.l	RAMCR_D,r0
-	mov.l	r0, @r1
 
-	mov.l	MMSELR_A,r1
+	mov.l	MMSELR_A, r1
-	mov.l	MMSELR_D,r0
+	mov.l	MMSELR_D, r0
 	synco
 	mov.l	r0, @r1
 
-	mov.l	@r1,r2		/* execute two reads after setting MMSELR*/
+	mov.l	@r1, r2		/* execute two reads after setting MMSELR */
-	mov.l	@r1,r2
+	mov.l	@r1, r2
 	synco
 
 	/* issue memory read */
-	mov.l   DDRSD_START_A,r1	/* memory address to read*/
+	mov.l	DDRSD_START_A, r1	/* memory address to read*/
-	mov.l   @r1,r0
+	mov.l	@r1, r0
 	synco
 
-	mov.l	MIM8_A,r1
+	write32	MIM8_A, MIM8_D
-	mov.l	MIM8_D,r0
-	mov.l	r0,@r1
 
-	mov.l	MIMC_A,r1
+	write32	MIMC_A, MIMC_D1
-	mov.l	MIMC_D1,r0
-	mov.l	r0,@r1
 
-	mov.l	STRC_A,r1
+	write32	STRC_A, STRC_D
-	mov.l	STRC_D,r0
-	mov.l	r0,@r1
 
-	mov.l	SDR4_A,r1
+	write32	SDR4_A, SDR4_D
-	mov.l	SDR4_D,r0
-	mov.l	r0,@r1
 
-	mov.l	MIMC_A,r1
+	write32	MIMC_A, MIMC_D2
-	mov.l	MIMC_D2,r0
-	mov.l	r0,@r1
 
 	nop
 	nop
 	nop
 
-	mov.l	SCR4_A,r1
+	write32	SCR4_A, SCR4_D3
-	mov.l	SCR4_D3,r0
-	mov.l	r0,@r1
 
-	mov.l	SCR4_A,r1
+	write32	SCR4_A, SCR4_D2
-	mov.l	SCR4_D2,r0
-	mov.l	r0,@r1
 
-	mov.l	SDMR02000_A,r1
+	write32	SDMR02000_A, SDMR02000_D
-	mov.l	SDMR02000_D,r0
-	mov.l	r0,@r1
 
-	mov.l	SDMR00B08_A,r1
+	write32	SDMR00B08_A, SDMR00B08_D
-	mov.l	SDMR00B08_D,r0
-	mov.l	r0,@r1
 
-	mov.l	SCR4_A,r1
+	write32	SCR4_A, SCR4_D2
-	mov.l	SCR4_D2,r0
-	mov.l	r0,@r1
 
-	mov.l	SCR4_A,r1
+	write32	SCR4_A, SCR4_D4
-	mov.l	SCR4_D4,r0
-	mov.l	r0,@r1
 
 	nop
 	nop
 	nop
 	nop
 
-	mov.l	SCR4_A,r1
+	write32	SCR4_A, SCR4_D4
-	mov.l	SCR4_D4,r0
-	mov.l	r0,@r1
 
 	nop
 	nop
 	nop
 	nop
 
-	mov.l	SDMR00308_A,r1
+	write32	SDMR00308_A, SDMR00308_D
-	mov.l	SDMR00308_D,r0
-	mov.l	r0,@r1
 
-	mov.l	MIMC_A,r1
+	write32	MIMC_A, MIMC_D3
-	mov.l	MIMC_D3,r0
-	mov.l	r0,@r1
 
-	mov.l	SCR4_A,r1
+	mov.l	SCR4_A, r1
-	mov.l	SCR4_D1,r0
+	mov.l	SCR4_D1, r0
-	mov.l	DELAY60_D,r3
+	mov.l	DELAY60_D, r3
 
 delay_loop_60:
-	mov.l	r0,@r1
+	mov.l	r0, @r1
 	dt	r3
 	bf	delay_loop_60
 	nop
 
-	mov.l   CCR_A, r1	/* Address of Cache Control Register */
+	write32	CCR_A, CCR_CACHE_D_2	/* Address of Cache Control Register */
-	mov.l   CCR_CACHE_D_2, r0
-	mov.l   r0, @r1
 
 bsc_init:
-	mov.l	BCR_A, r1
+	write32	BCR_A, BCR_D
-	mov.l	BCR_D, r0
-	mov.l	r0, @r1
 
-	mov.l	CS0BCR_A, r1
+	write32	CS0BCR_A, CS0BCR_D
-	mov.l	CS0BCR_D, r0
-	mov.l	r0, @r1
 
-	mov.l	CS1BCR_A,r1
+	write32	CS1BCR_A, CS1BCR_D
-	mov.l	CS1BCR_D,r0
-	mov.l	r0,@r1
 
-	mov.l	CS2BCR_A, r1
+	write32	CS2BCR_A, CS2BCR_D
-	mov.l	CS2BCR_D, r0
-	mov.l	r0, @r1
 
-	mov.l	CS4BCR_A, r1
+	write32	CS4BCR_A, CS4BCR_D
-	mov.l	CS4BCR_D, r0
-	mov.l	r0, @r1
 
-	mov.l	CS5BCR_A, r1
+	write32	CS5BCR_A, CS5BCR_D
-	mov.l	CS5BCR_D, r0
-	mov.l	r0, @r1
 
-	mov.l	CS6BCR_A, r1
+	write32	CS6BCR_A, CS6BCR_D
-	mov.l	CS6BCR_D, r0
-	mov.l	r0, @r1
 
-	mov.l	CS0WCR_A, r1
+	write32	CS0WCR_A, CS0WCR_D
-	mov.l	CS0WCR_D, r0
-	mov.l	r0, @r1
 
-	mov.l	CS1WCR_A, r1
+	write32	CS1WCR_A, CS1WCR_D
-	mov.l	CS1WCR_D, r0
-	mov.l	r0, @r1
 
-	mov.l	CS2WCR_A, r1
+	write32	CS2WCR_A, CS2WCR_D
-	mov.l	CS2WCR_D, r0
-	mov.l	r0, @r1
 
-	mov.l	CS4WCR_A, r1
+	write32	CS4WCR_A, CS4WCR_D
-	mov.l	CS4WCR_D, r0
-	mov.l	r0, @r1
 
-	mov.l	CS5WCR_A, r1
+	write32	CS5WCR_A, CS5WCR_D
-	mov.l	CS5WCR_D, r0
-	mov.l	r0, @r1
 
-	mov.l	CS6WCR_A, r1
+	write32	CS6WCR_A, CS6WCR_D
-	mov.l	CS6WCR_D, r0
-	mov.l	r0, @r1
 
-	mov.l	CS5PCR_A, r1
+	write32	CS5PCR_A, CS5PCR_D
-	mov.l	CS5PCR_D, r0
-	mov.l	r0, @r1
 
-	mov.l	CS6PCR_A, r1
+	write32	CS6PCR_A, CS6PCR_D
-	mov.l	CS6PCR_D, r0
-	mov.l	r0, @r1
 
-	mov.l	DELAY200_D,r3
+	mov.l	DELAY200_D, r3
 
 delay_loop_200:
 	dt	r3
 	bf	delay_loop_200
 	nop
 
-	mov.l	PSEL0_A,r1
+	write16	PSEL0_A, PSEL0_D
-	mov.l	PSEL0_D,r0
-	mov.w	r0,@r1
 
-	mov.l	PSEL1_A,r1
+	write16	PSEL1_A, PSEL1_D
-	mov.l	PSEL1_D,r0
-	mov.w	r0,@r1
 
-	mov.l	ICR0_A,r1
+	write32	ICR0_A, ICR0_D
-	mov.l	ICR0_D,r0
-	mov.l	r0,@r1
 
 	stc sr, r0	/* BL bit off(init=ON) */
-	mov.l   SR_MASK_D, r1
+	mov.l	SR_MASK_D, r1
 	and r1, r0
 	ldc r0, sr
 
@@ -321,7 +245,7 @@ CS4BCR_D:	.long	0x77777670
 CS5BCR_D:	.long	0x77777670
 CS6BCR_D:	.long	0x77777670
 CS0WCR_D:	.long	0x7777770F
-CS1WCR_D:	.long   0x22000002
+CS1WCR_D:	.long	0x22000002
 CS2WCR_D:	.long	0x7777770F
 CS4WCR_D:	.long	0x7777770F
 CS5WCR_D:	.long	0x7777770F

board/renesas/sh7785lcr/lowlevel_init.S

@@ -19,33 +19,7 @@
 #include <config.h>
 #include <version.h>
 #include <asm/processor.h>
-
+#include <asm/macro.h>
-.macro	write32, addr, data
-	mov.l \addr ,r1
-	mov.l \data ,r0
-	mov.l r0, @r1
-.endm
-
-.macro	write16, addr, data
-	mov.l \addr ,r1
-	mov.l \data ,r0
-	mov.w r0, @r1
-.endm
-
-.macro	write8, addr, data
-	mov.l \addr ,r1
-	mov.l \data ,r0
-	mov.b r0, @r1
-.endm
-
-.macro	wait_timer, time
-	mov.l	\time ,r3
-1:
-	nop
-	tst	r3, r3
-	bf/s	1b
-	dt	r3
-.endm
 
 #include <asm/processor.h>
 
@@ -305,7 +279,7 @@ CS4WCR_D:	.long	0x00101012
 CS_USB_BCR_D:	.long	0x11111200
 CS_USB_WCR_D:	.long	0x00020004
 
-/* SD setting  : 32bit mode = CS3, 29bit mode = CS6 */
+/* SD setting : 32bit mode = CS3, 29bit mode = CS6 */
 CS_SD_BCR_D:	.long	0x00000300
 CS_SD_WCR_D:	.long	0x00030108
 

board/sandburst/karef/karef.c

@@ -26,6 +26,7 @@
 #include <command.h>
 #include "karef.h"
 #include "karef_version.h"
+#include <timestamp.h>
 #include <asm/processor.h>
 #include <asm/io.h>
 #include <spd_sdram.h>
@@ -299,7 +300,7 @@ int checkboard (void)
 		"Serial Number: %d\n", sernum);
 	printf ("%s\n", KAREF_U_BOOT_REL_STR);
 
-	printf ("Built %s %s by %s\n", __DATE__, __TIME__, BUILDUSER);
+	printf ("Built %s %s by %s\n", U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
 	if (sbcommon_get_master()) {
 		printf("Slot 0 - Master\nSlave board");
 		if (sbcommon_secondary_present())
@@ -366,7 +367,8 @@ int misc_init_r (void)
 	setenv("ubrelver", KAREF_U_BOOT_REL_STR);
 
 	memset(envstr, 0, 255);
-	sprintf (envstr, "Built %s %s by %s", __DATE__, __TIME__, BUILDUSER);
+	sprintf (envstr, "Built %s %s by %s",
+		 U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
 	setenv("bldstr", envstr);
 	saveenv();
 

board/sandburst/metrobox/metrobox.c

@@ -25,6 +25,7 @@
 #include <command.h>
 #include "metrobox.h"
 #include "metrobox_version.h"
+#include <timestamp.h>
 #include <asm/processor.h>
 #include <asm/io.h>
 #include <spd_sdram.h>
@@ -270,7 +271,7 @@ int checkboard (void)
 	printf ("Board: Sandburst Corporation MetroBox Serial Number: %d\n", sernum);
 	printf ("%s\n", METROBOX_U_BOOT_REL_STR);
 
-	printf ("Built %s %s by %s\n", __DATE__, __TIME__, BUILDUSER);
+	printf ("Built %s %s by %s\n", U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
 	if (sbcommon_get_master()) {
 		printf("Slot 0 - Master\nSlave board");
 		if (sbcommon_secondary_present())
@@ -335,7 +336,8 @@ int misc_init_r (void)
 	setenv("ubrelver", METROBOX_U_BOOT_REL_STR);
 
 	memset(envstr, 0, 255);
-	sprintf (envstr, "Built %s %s by %s", __DATE__, __TIME__, BUILDUSER);
+	sprintf (envstr, "Built %s %s by %s",
+		 U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
 	setenv("bldstr", envstr);
 	saveenv();
 

board/sbc8548/sbc8548.c

@@ -36,10 +36,6 @@
 #include <libfdt.h>
 #include <fdt_support.h>
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
 DECLARE_GLOBAL_DATA_PTR;
 
 void local_bus_init(void);
@@ -65,13 +61,6 @@ int checkboard (void)
 	 */
 	local_bus_init ();
 
-	/*
-	 * Fix CPU2 errata: A core hang possible while executing a
-	 * msync instruction and a snoopable transaction from an I/O
-	 * master tagged to make quick forward progress is present.
-	 */
-	ecm->eebpcr |= (1 << 16);
-
 	/*
 	 * Hack TSEC 3 and 4 IO voltages.
 	 */
@@ -114,12 +103,6 @@ initdram(int board_type)
 	dram_size = fixed_sdram ();
 #endif
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-	/*
-	 * Initialize and enable DDR ECC.
-	 */
-	ddr_enable_ecc(dram_size);
-#endif
 	/*
 	 * SDRAM Initialization
 	 */
@@ -143,7 +126,7 @@ local_bus_init(void)
 	sys_info_t sysinfo;
 
 	get_sys_info(&sysinfo);
-	clkdiv = (lbc->lcrr & 0x0f) * 2;
+	clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
 	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
 	gur->lbiuiplldcr1 = 0x00078080;
@@ -429,7 +412,7 @@ pci_init_board(void)
 		first_free_busno=hose->last_busno+1;
 		printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
 #ifdef CONFIG_PCIX_CHECK
-		if (!(gur->pordevsr & PORDEVSR_PCI)) {
+		if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
 			/* PCI-X init */
 			if (CONFIG_SYS_CLK_FREQ < 66000000)
 				printf("PCI-X will only work at 66 MHz\n");

board/sbc8641d/law.c

@@ -45,14 +45,14 @@
 
 struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
-	SET_LAW(CONFIG_SYS_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
+	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CONFIG_SYS_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+	SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
 	SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_PCI1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
+	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CONFIG_SYS_PCI2_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
+	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
 	SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2),
-	SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
+	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);

board/sbc8641d/sbc8641d.c

@@ -247,14 +247,14 @@ void pci_init_board(void)
 
 		/* outbound memory */
 		pci_set_region(r++,
-			       CONFIG_SYS_PCI1_MEM_BASE,
+			       CONFIG_SYS_PCI1_MEM_BUS,
 			       CONFIG_SYS_PCI1_MEM_PHYS,
 			       CONFIG_SYS_PCI1_MEM_SIZE,
 			       PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(r++,
-			       CONFIG_SYS_PCI1_IO_BASE,
+			       CONFIG_SYS_PCI1_IO_BUS,
 			       CONFIG_SYS_PCI1_IO_PHYS,
 			       CONFIG_SYS_PCI1_IO_SIZE,
 			       PCI_REGION_IO);
@@ -290,14 +290,14 @@ void pci_init_board(void)
 
 	/* outbound memory */
 	pci_set_region(r++,
-		       CONFIG_SYS_PCI2_MEM_BASE,
+		       CONFIG_SYS_PCI2_MEM_BUS,
 		       CONFIG_SYS_PCI2_MEM_PHYS,
 		       CONFIG_SYS_PCI2_MEM_SIZE,
 		       PCI_REGION_MEM);
 
 	/* outbound io */
 	pci_set_region(r++,
-		       CONFIG_SYS_PCI2_IO_BASE,
+		       CONFIG_SYS_PCI2_IO_BUS,
 		       CONFIG_SYS_PCI2_IO_PHYS,
 		       CONFIG_SYS_PCI2_IO_SIZE,
 		       PCI_REGION_IO);

board/socrates/socrates.c

@@ -156,7 +156,7 @@ void local_bus_init (void)
 	uint lcrr = CONFIG_SYS_LBC_LCRR;
 
 	get_sys_info (&sysinfo);
-	clkdiv = lbc->lcrr & 0x0f;
+	clkdiv = lbc->lcrr & LCRR_CLKDIV;
 	lbc_mhz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
 	/* Disable PLL bypass for Local Bus Clock >= 66 MHz */

board/socrates/tlb.c

@@ -100,6 +100,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 6, BOOKE_PAGESZ_64M, 1),
 
+#if !defined(CONFIG_SPD_EEPROM)
 	/*
 	 * TLB 7+8:	512M	DDR, cache disabled (needed for memory test)
 	 * 0x00000000  512M	DDR System memory
@@ -114,6 +115,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 8, BOOKE_PAGESZ_256M, 1),
+#endif
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);

board/tqc/tqm85xx/tqm85xx.c

@@ -361,7 +361,7 @@ uint get_lbc_clock (void)
 {
 	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 	sys_info_t sys_info;
-	ulong clkdiv = lbc->lcrr & 0x0f;
+	ulong clkdiv = lbc->lcrr & LCRR_CLKDIV;
 
 	get_sys_info (&sys_info);
 
@@ -610,7 +610,7 @@ static inline void init_pci1(void)
 
 		first_free_busno = hose->last_busno + 1;
 #ifdef CONFIG_PCIX_CHECK
-		if (!(gur->pordevsr & PORDEVSR_PCI)) {
+		if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
 			ushort reg16 =
 				PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ |
 				PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;

board/tqc/tqm8xx/tqm8xx.c

@@ -570,17 +570,19 @@ void ide_led (uchar led, uchar status)
 
 #ifdef CONFIG_LCD_INFO
 #include <lcd.h>
+#include <version.h>
+#include <timestamp.h>
 
 void lcd_show_board_info(void)
 {
-	lcd_printf ("%s (%s - %s)\n", U_BOOT_VERSION, __DATE__, __TIME__);
+	char temp[32];
+
+	lcd_printf ("%s (%s - %s)\n", U_BOOT_VERSION, U_BOOT_DATE, U_BOOT_TIME);
 	lcd_printf ("(C) 2008 DENX Software Engineering GmbH\n");
 	lcd_printf ("    Wolfgang DENK, wd@denx.de\n");
 #ifdef CONFIG_LCD_INFO_BELOW_LOGO
 	lcd_printf ("MPC823 CPU at %s MHz\n",
 		strmhz(temp, gd->cpu_clk));
-	lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT * 3,
-					info, strlen(info));
 	lcd_printf ("  %ld MB RAM, %ld MB Flash\n",
 		gd->ram_size >> 20,
 		gd->bd->bi_flashsize >> 20 );

board/trab/Makefile

@@ -51,7 +51,8 @@ $(obj)trab_fkt.srec:	$(OBJS_FKT) $(LIB)
 	$(LD) -g -Ttext $(LOAD_ADDR) -o $(<:.o=) -e trab_fkt $^ $(LIB) \
 		-L$(obj)../../examples -lstubs \
 		-L$(obj)../../lib_generic -lgeneric \
-		-L$(gcclibdir) -lgcc
+		$(obj)../../lib_arm/div0.o \
+		$(obj)../../lib_arm/_*.o
 	$(OBJCOPY) -O srec $(<:.o=) $@
 
 $(obj)trab_fkt.bin:	$(obj)trab_fkt.srec

board/trab/memory.c

@@ -184,7 +184,7 @@
  *
  * For other processors, let the compiler generate the best code it can.
  */
-static void move64(unsigned long long *src, unsigned long long *dest)
+static void move64(const unsigned long long *src, unsigned long long *dest)
 {
 #if defined(CONFIG_MPC8260) || defined(CONFIG_MPC824X)
 	asm ("lfd  0, 0(3)\n\t" /* fpr0	  =  *scr	*/
@@ -231,12 +231,12 @@ static int memory_post_dataline(unsigned long long * pmem)
 	int ret = 0;
 
 	for ( i = 0; i < num_patterns; i++) {
-		move64((unsigned long long *)&(pattern[i]), pmem++);
+		move64(&(pattern[i]), pmem++);
 		/*
 		 * Put a different pattern on the data lines: otherwise they
 		 * may float long enough to read back what we wrote.
 		 */
-		move64((unsigned long long *)&otherpattern, pmem--);
+		move64(&otherpattern, pmem--);
 		move64(pmem, &temp64);
 
 #ifdef INJECT_DATA_ERRORS

board/trab/trab_fkt.c

@@ -25,6 +25,7 @@
 
 #include <common.h>
 #include <exports.h>
+#include <timestamp.h>
 #include <s3c2400.h>
 #include "tsc2000.h"
 #include "rs485.h"
@@ -293,10 +294,16 @@ int trab_fkt (int argc, char *argv[])
 	return 1;
 }
 
+void hang (void)
+{
+	puts ("### ERROR ### Please RESET the board ###\n");
+	for (;;);
+}
+
 int do_info (void)
 {
 	printf ("Stand-alone application for TRAB board function test\n");
-	printf ("Built: %s at %s\n", __DATE__ , __TIME__ );
+	printf ("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME);
 
 	return 0;
 }

board/voiceblue/eeprom.c

@@ -26,6 +26,7 @@
 
 #include <common.h>
 #include <exports.h>
+#include <timestamp.h>
 #include "../drivers/net/smc91111.h"
 
 #define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE
@@ -169,7 +170,7 @@ int eeprom(int argc, char *argv[])
 	/* Print help message */
 	if (argv[1][1] == 'h') {
 		printf("VoiceBlue EEPROM writer\n");
-		printf("Built: %s at %s\n", __DATE__ , __TIME__ );
+		printf("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME);
 		printf("Usage:\n\t<mac_address> [<element_1>] [<...>]\n");
 		return 0;
 	}

board/xes/common/Makefile

@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2000-2006
+# (C) Copyright 2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -23,16 +23,23 @@
 
 include $(TOPDIR)/config.mk
 
-LIB	= $(obj)lib$(BOARD).a
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)board/$(VENDOR)/common)
+endif
 
-COBJS	= $(BOARD).o
+LIB	= $(obj)lib$(VENDOR).a
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+COBJS-$(CONFIG_FSL_PCI_INIT)	+= fsl_85xx_pci.o
-OBJS	:= $(addprefix $(obj),$(COBJS))
+COBJS-$(CONFIG_MPC8572)		+= fsl_8572_clk.o
+COBJS-$(CONFIG_MPC85xx)		+= fsl_85xx_ddr.o
+COBJS-$(CONFIG_NAND_ACTL)	+= actl_nand.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(OBJS) $(SOBJS)
+$(LIB):	$(obj).depend $(OBJS)
-	$(AR) $(ARFLAGS) $@ $^
+	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 clean:
 	rm -f $(SOBJS) $(OBJS)

board/xes/common/actl_nand.c

@@ -0,0 +1,65 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * This driver support NAND devices which have address lines
+ * connected as ALE and CLE inputs.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <asm/io.h>
+
+/*
+ * Hardware specific access to control-lines
+ */
+static void nand_addr_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl)
+{
+	struct nand_chip *this = mtd->priv;
+	ulong IO_ADDR_W;
+
+	if (ctrl & NAND_CTRL_CHANGE) {
+		IO_ADDR_W = (ulong)this->IO_ADDR_W;
+
+		IO_ADDR_W &= ~(CONFIG_SYS_NAND_ACTL_CLE |
+				CONFIG_SYS_NAND_ACTL_ALE |
+				CONFIG_SYS_NAND_ACTL_NCE);
+		if (ctrl & NAND_CLE)
+			IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_CLE;
+		if (ctrl & NAND_ALE)
+			IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_ALE;
+		if (ctrl & NAND_NCE)
+			IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_NCE;
+
+		this->IO_ADDR_W = (void *)IO_ADDR_W;
+	}
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	nand->ecc.mode = NAND_ECC_SOFT;
+	nand->cmd_ctrl = nand_addr_hwcontrol;
+	nand->chip_delay = CONFIG_SYS_NAND_ACTL_DELAY;
+
+	return 0;
+}

board/xes/common/fsl_8572_clk.c

@@ -1,7 +1,5 @@
 /*
- * (C) Copyright 2007 Michal Simek
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
- *
- * Michal  SIMEK <monstr@monstr.eu>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -22,28 +20,32 @@
  * MA 02111-1307 USA
  */
 
-/* This is a board specific file.  It's OK to include board specific
- * header files */
-
 #include <common.h>
-#include <config.h>
 
-void do_reset (void)
+/*
+ * Return SYSCLK input frequency - 50 MHz or 66 MHz depending on POR config
+ */
+unsigned long get_board_sys_clk(ulong dummy)
 {
-#ifdef CONFIG_SYS_GPIO_0
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	*((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)) =
+	u32 gpporcr = gur->gpporcr;
-	    ++(*((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)));
+
-#endif
+	if (gpporcr & 0x10000)
-#ifdef CONFIG_SYS_RESET_ADDRESS
+		return 66666666;
-	puts ("Reseting board\n");
+	else
-	asm ("bra r0");
+		return 50000000;
-#endif
 }
 
-int gpio_init (void)
+/*
+ * Return DDR input clock - synchronous with SYSCLK or 66 MHz
+ */
+unsigned long get_board_ddr_clk(ulong dummy)
 {
-#ifdef CONFIG_SYS_GPIO_0
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	*((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)) = 0x0;
+	u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
-#endif
+
-	return 0;
+	if (ddr_ratio == 0x7)
+		return get_board_sys_clk(dummy);
+
+	return 66666666;
 }

board/xes/common/fsl_85xx_ddr.c

@@ -0,0 +1,93 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/mmu.h>
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+phys_size_t initdram(int board_type)
+{
+	phys_size_t dram_size = fsl_ddr_sdram();
+
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+
+	dram_size *= 0x100000;
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	/* Initialize and enable DDR ECC */
+	ddr_enable_ecc(dram_size);
+#endif
+
+	return dram_size;
+}
+
+#if defined(CONFIG_DDR_ECC) || (CONFIG_NUM_DDR_CONTROLLERS > 1)
+void board_add_ram_info(int use_default)
+{
+#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
+	volatile ccsr_ddr_t *ddr1 = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
+#endif
+
+	puts(" (");
+
+#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
+	/* Print interleaving information */
+	if (ddr1->cs0_config & 0x20000000) {
+		switch ((ddr1->cs0_config >> 24) & 0xf) {
+		case 0:
+			puts("cache line");
+			break;
+		case 1:
+			puts("page");
+			break;
+		case 2:
+			puts("bank");
+			break;
+		case 3:
+			puts("super-bank");
+			break;
+		default:
+			puts("invalid");
+			break;
+		}
+	} else {
+		puts("no");
+	}
+
+	puts(" interleaving");
+#endif
+
+#if (CONFIG_NUM_DDR_CONTROLLERS > 1) && defined(CONFIG_DDR_ECC)
+	puts(", ");
+#endif
+
+#if defined(CONFIG_DDR_ECC)
+	puts("ECC enabled");
+#endif
+
+	puts(")");
+}
+#endif /* CONFIG_DDR_ECC || CONFIG_NUM_DDR_CONTROLLERS > 1 */

board/xes/common/fsl_85xx_pci.c

@@ -0,0 +1,379 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/immap_85xx.h>
+#include <asm/immap_fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
+extern void fsl_pci_config_unlock(struct pci_controller *hose);
+extern void fsl_pci_init(struct pci_controller *hose);
+
+int first_free_busno = 0;
+
+#ifdef CONFIG_PCI1
+static struct pci_controller pci1_hose;
+#endif
+#ifdef CONFIG_PCIE1
+static struct pci_controller pcie1_hose;
+#endif
+#ifdef CONFIG_PCIE2
+static struct pci_controller pcie2_hose;
+#endif
+#ifdef CONFIG_PCIE3
+static struct pci_controller pcie3_hose;
+#endif
+
+#ifdef CONFIG_MPC8572
+/* Correlate host/agent POR bits to usable info. Table 4-14 */
+struct host_agent_cfg_t {
+	uchar pcie_root[3];
+	uchar rio_host;
+} host_agent_cfg[8] = {
+	{{0, 0, 0}, 0},
+	{{0, 1, 1}, 1},
+	{{1, 0, 1}, 0},
+	{{1, 1, 0}, 1},
+	{{0, 0, 1}, 0},
+	{{0, 1, 0}, 1},
+	{{1, 0, 0}, 0},
+	{{1, 1, 1}, 1}
+};
+
+/* Correlate port width POR bits to usable info. Table 4-15 */
+struct io_port_cfg_t {
+	uchar pcie_width[3];
+	uchar rio_width;
+} io_port_cfg[16] = {
+	{{0, 0, 0}, 0},
+	{{0, 0, 0}, 0},
+	{{4, 0, 0}, 0},
+	{{4, 4, 0}, 0},
+	{{0, 0, 0}, 0},
+	{{0, 0, 0}, 0},
+	{{0, 0, 0}, 4},
+	{{4, 2, 2}, 0},
+	{{0, 0, 0}, 0},
+	{{0, 0, 0}, 0},
+	{{0, 0, 0}, 0},
+	{{4, 0, 0}, 4},
+	{{4, 0, 0}, 4},
+	{{0, 0, 0}, 4},
+	{{0, 0, 0}, 4},
+	{{8, 0, 0}, 0},
+};
+#elif defined CONFIG_MPC8548
+/* Correlate host/agent POR bits to usable info. Table 4-12 */
+struct host_agent_cfg_t {
+	uchar pci_host[2];
+	uchar pcie_root[1];
+	uchar rio_host;
+} host_agent_cfg[8] = {
+	{{1, 1}, {0}, 0},
+	{{1, 1}, {1}, 0},
+	{{1, 1}, {0}, 1},
+	{{0, 0}, {0}, 0}, /* reserved */
+	{{0, 1}, {1}, 0},
+	{{1, 1}, {1}, 0},
+	{{0, 1}, {1}, 1},
+	{{1, 1}, {1}, 1}
+};
+
+/* Correlate port width POR bits to usable info. Table 4-13 */
+struct io_port_cfg_t {
+	uchar pcie_width[1];
+	uchar rio_width;
+} io_port_cfg[8] = {
+	{{0}, 0},
+	{{0}, 0},
+	{{0}, 0},
+	{{4}, 4},
+	{{4}, 4},
+	{{0}, 4},
+	{{0}, 4},
+	{{8}, 0},
+};
+#endif
+
+void pci_init_board(void)
+{
+	struct pci_controller *hose;
+	volatile ccsr_fsl_pci_t *pci;
+	int width;
+	int host;
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	uint devdisr = gur->devdisr;
+	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
+	struct pci_region *r;
+
+#ifdef CONFIG_PCI1
+	uint pci_spd_norm = (gur->pordevsr & MPC85xx_PORDEVSR_PCI1_SPD);
+	uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
+	uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
+	uint pcix = gur->pordevsr & MPC85xx_PORDEVSR_PCI1;
+	uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000;
+
+	width = 0; /* Silence compiler warning... */
+	io_sel &= 0xf; /* Silence compiler warning... */
+	pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
+	hose = &pci1_hose;
+	host = host_agent_cfg[host_agent].pci_host[0];
+	r = hose->regions;
+
+
+	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+		printf("\n    PCI1: %d bit %s, %s %d MHz, %s, %s\n",
+			pci_32 ? 32 : 64,
+			pcix ? "PCIX" : "PCI",
+			pci_spd_norm ?  ">=" : "<=",
+			pcix ? freq * 2 : freq,
+			host ? "host" : "agent",
+			pci_arb ? "arbiter" : "external-arbiter");
+
+		/* inbound */
+		r += fsl_pci_setup_inbound_windows(r);
+
+		/* outbound memory */
+		pci_set_region(r++,
+				CONFIG_SYS_PCI1_MEM_BASE,
+				CONFIG_SYS_PCI1_MEM_PHYS,
+				CONFIG_SYS_PCI1_MEM_SIZE,
+				PCI_REGION_MEM);
+
+		/* outbound io */
+		pci_set_region(r++,
+				CONFIG_SYS_PCI1_IO_BASE,
+				CONFIG_SYS_PCI1_IO_PHYS,
+				CONFIG_SYS_PCI1_IO_SIZE,
+				PCI_REGION_IO);
+
+		hose->region_count = r - hose->regions;
+
+		hose->first_busno = first_free_busno;
+		pci_setup_indirect(hose, (int)&pci->cfg_addr,
+				   (int)&pci->cfg_data);
+
+		fsl_pci_init(hose);
+
+		/* Unlock inbound PCI configuration cycles */
+		if (!host)
+			fsl_pci_config_unlock(hose);
+
+		first_free_busno = hose->last_busno + 1;
+		printf("    PCI1 on bus %02x - %02x\n",
+			hose->first_busno, hose->last_busno);
+	} else {
+		printf("    PCI1: disabled\n");
+	}
+#elif defined CONFIG_MPC8548
+	/* PCI1 not present on MPC8572 */
+	gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
+#endif
+#ifdef CONFIG_PCIE1
+	pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
+	hose = &pcie1_hose;
+	host = host_agent_cfg[host_agent].pcie_root[0];
+	width = io_port_cfg[io_sel].pcie_width[0];
+	r = hose->regions;
+
+	if (width && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
+		printf("\n    PCIE1 connected as %s (x%d)",
+			host ? "Root Complex" : "End Point", width);
+		if (pci->pme_msg_det) {
+			pci->pme_msg_det = 0xffffffff;
+			debug(" with errors.  Clearing.  Now 0x%08x",
+				pci->pme_msg_det);
+		}
+		printf("\n");
+
+		/* inbound */
+		r += fsl_pci_setup_inbound_windows(r);
+
+		/* outbound memory */
+		pci_set_region(r++,
+				CONFIG_SYS_PCIE1_MEM_BASE,
+				CONFIG_SYS_PCIE1_MEM_PHYS,
+				CONFIG_SYS_PCIE1_MEM_SIZE,
+				PCI_REGION_MEM);
+
+		/* outbound io */
+		pci_set_region(r++,
+				CONFIG_SYS_PCIE1_IO_BASE,
+				CONFIG_SYS_PCIE1_IO_PHYS,
+				CONFIG_SYS_PCIE1_IO_SIZE,
+				PCI_REGION_IO);
+
+		hose->region_count = r - hose->regions;
+
+		hose->first_busno = first_free_busno;
+		pci_setup_indirect(hose, (int)&pci->cfg_addr,
+					(int) &pci->cfg_data);
+
+		fsl_pci_init(hose);
+
+		/* Unlock inbound PCI configuration cycles */
+		if (!host)
+			fsl_pci_config_unlock(hose);
+
+		first_free_busno = hose->last_busno + 1;
+		printf("    PCIE1 on bus %02x - %02x\n",
+				hose->first_busno, hose->last_busno);
+	}
+#else
+	gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+#endif /* CONFIG_PCIE1 */
+
+#ifdef CONFIG_PCIE2
+	pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
+	hose = &pcie2_hose;
+	host = host_agent_cfg[host_agent].pcie_root[1];
+	width = io_port_cfg[io_sel].pcie_width[1];
+	r = hose->regions;
+
+	if (width && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
+		printf("\n    PCIE2 connected as %s (x%d)",
+			host ? "Root Complex" : "End Point", width);
+		if (pci->pme_msg_det) {
+			pci->pme_msg_det = 0xffffffff;
+			debug(" with errors.  Clearing.  Now 0x%08x",
+				pci->pme_msg_det);
+		}
+		printf("\n");
+
+		/* inbound */
+		r += fsl_pci_setup_inbound_windows(r);
+
+		/* outbound memory */
+		pci_set_region(r++,
+				CONFIG_SYS_PCIE2_MEM_BASE,
+				CONFIG_SYS_PCIE2_MEM_PHYS,
+				CONFIG_SYS_PCIE2_MEM_SIZE,
+				PCI_REGION_MEM);
+
+		/* outbound io */
+		pci_set_region(r++,
+				CONFIG_SYS_PCIE2_IO_BASE,
+				CONFIG_SYS_PCIE2_IO_PHYS,
+				CONFIG_SYS_PCIE2_IO_SIZE,
+				PCI_REGION_IO);
+
+		hose->region_count = r - hose->regions;
+
+		hose->first_busno = first_free_busno;
+		pci_setup_indirect(hose, (int)&pci->cfg_addr,
+					(int)&pci->cfg_data);
+
+		fsl_pci_init(hose);
+
+		/* Unlock inbound PCI configuration cycles */
+		if (!host)
+			fsl_pci_config_unlock(hose);
+
+		first_free_busno = hose->last_busno + 1;
+		printf("    PCIE2 on bus %02x - %02x\n",
+				hose->first_busno, hose->last_busno);
+	}
+#else
+	gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
+#endif /* CONFIG_PCIE2 */
+
+#ifdef CONFIG_PCIE3
+	pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
+	hose = &pcie3_hose;
+	host = host_agent_cfg[host_agent].pcie_root[2];
+	width = io_port_cfg[io_sel].pcie_width[2];
+	r = hose->regions;
+
+	if (width && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
+		printf("\n    PCIE3 connected as %s (x%d)",
+			host ? "Root Complex" : "End Point", width);
+		if (pci->pme_msg_det) {
+			pci->pme_msg_det = 0xffffffff;
+			debug(" with errors.  Clearing.  Now 0x%08x",
+				pci->pme_msg_det);
+		}
+		printf("\n");
+
+		/* inbound */
+		r += fsl_pci_setup_inbound_windows(r);
+
+		/* outbound memory */
+		pci_set_region(r++,
+				CONFIG_SYS_PCIE3_MEM_BASE,
+				CONFIG_SYS_PCIE3_MEM_PHYS,
+				CONFIG_SYS_PCIE3_MEM_SIZE,
+				PCI_REGION_MEM);
+
+		/* outbound io */
+		pci_set_region(r++,
+				CONFIG_SYS_PCIE3_IO_BASE,
+				CONFIG_SYS_PCIE3_IO_PHYS,
+				CONFIG_SYS_PCIE3_IO_SIZE,
+				PCI_REGION_IO);
+
+		hose->region_count = r - hose->regions;
+
+		hose->first_busno = first_free_busno;
+		pci_setup_indirect(hose, (int)&pci->cfg_addr,
+					(int)&pci->cfg_data);
+
+		fsl_pci_init(hose);
+
+		/* Unlock inbound PCI configuration cycles */
+		if (!host)
+			fsl_pci_config_unlock(hose);
+
+		first_free_busno = hose->last_busno + 1;
+		printf("    PCIE3 on bus %02x - %02x\n",
+				hose->first_busno, hose->last_busno);
+	}
+#else
+	gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
+#endif /* CONFIG_PCIE3 */
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
+				struct pci_controller *hose);
+
+void ft_board_pci_setup(void *blob, bd_t *bd)
+{
+	/* TODO - make node name (eg pci0) dynamic */
+#ifdef CONFIG_PCI1
+	ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
+#endif
+#ifdef CONFIG_PCIE1
+	ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
+#endif
+#ifdef CONFIG_PCIE2
+	ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
+#endif
+#ifdef CONFIG_PCIE3
+	ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
+#endif
+}
+#endif /* CONFIG_OF_BOARD_SETUP */

board/xes/xpedite5200/Makefile

@@ -0,0 +1,55 @@
+#
+# Copyright 2008 Extreme Engineering Solutions, Inc.
+# Copyright 2004 Freescale Semiconductor.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= ddr.o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/xes/xpedite5200/config.mk

@@ -1,7 +1,6 @@
 #
-# (C) Copyright 2007 Michal Simek
+# Copyright 2008 Extreme Engineering Solutions, Inc.
-#
+# Copyright 2004, 2007 Freescale Semiconductor.
-# Michal  SIMEK <monstr@monstr.eu>
 #
 # See file CREDITS for list of people who contributed to this
 # project.
@@ -13,7 +12,7 @@
 #
 # This program is distributed in the hope that it will be useful,
 # but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 # GNU General Public License for more details.
 #
 # You should have received a copy of the GNU General Public License
@@ -21,12 +20,15 @@
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
-# CAUTION: This file is automatically generated by libgen.
+
-# Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4
 #
+# xpedite5200 board
+#
+ifndef TEXT_BASE
+TEXT_BASE = 0xfff80000
+endif
 
-TEXT_BASE = 0x38000000
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
-
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
-PLATFORM_CPPFLAGS += -mno-xl-soft-mul
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1
-PLATFORM_CPPFLAGS += -mno-xl-soft-div
+PLATFORM_CPPFLAGS += -mrelocatable
-PLATFORM_CPPFLAGS += -mxl-barrel-shift

board/xes/xpedite5200/ddr.c

@@ -0,0 +1,91 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void
+get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
+
+	/* We use soldered memory, but use an SPD EEPROM to describe it.
+	 * The SPD has an unspecified dimm type, but the DDR2 initialization
+	 * code requires a specific type to be specified. This sets the type
+	 * as a standard unregistered SO-DIMM. */
+	if (spd->dimm_type == 0) {
+		spd->dimm_type = 0x4;
+		((uchar *)spd)[63] += 0x4;
+	}
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+	return get_ddr_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
+			unsigned int ctrl_num)
+{
+	unsigned int i;
+
+	if (ctrl_num) {
+		printf("%s: invalid ctrl_num = %d\n", __func__, ctrl_num);
+		return;
+	}
+
+	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++)
+		get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS);
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	/*
+	 * Factors to consider for clock adjust:
+	 *	- number of chips on bus
+	 *	- position of slot
+	 *	- DDR1 vs. DDR2?
+	 *	- ???
+	 *
+	 * This needs to be determined on a board-by-board basis.
+	 *	0110	3/4 cycle late
+	 *	0111	7/8 cycle late
+	 */
+	popts->clk_adjust = 7;
+
+	/*
+	 * Factors to consider for CPO:
+	 *	- frequency
+	 *	- ddr1 vs. ddr2
+	 */
+	popts->cpo_override = 9;
+
+	/*
+	 * Factors to consider for write data delay:
+	 *	- number of DIMMs
+	 *
+	 * 1 = 1/4 clock delay
+	 * 2 = 1/2 clock delay
+	 * 3 = 3/4 clock delay
+	 * 4 = 1   clock delay
+	 * 5 = 5/4 clock delay
+	 * 6 = 3/2 clock delay
+	 */
+	popts->write_data_delay = 3;
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+}

board/xes/xpedite5200/law.c

@@ -0,0 +1,51 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+#if CONFIG_SYS_PCI1_MEM_PHYS
+	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCI_1),
+	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAWAR_SIZE_8M, LAW_TRGT_IF_PCI_1),
+#endif
+#if CONFIG_SYS_PCI2_MEM_PHYS
+	SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_2),
+	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_2),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);