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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

This commit is contained in:
Wolfgang Denk 2010-07-16 23:15:01 +02:00
parent 16909f34b7 9f43d7997e
commit b6c208ab1e
117 changed files with 2372 additions and 1357 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
MAINTAINERS
View File

@ -448,6 +448,7 @@ Timur Tabi <timur@freescale.com>
MPC8349E-mITX MPC8349
MPC8349E-mITX-GP MPC8349
P1022DS P1022
Erik Theisen <etheisen@mindspring.com>

1
MAKEALL
View File

@ -410,6 +410,7 @@ LIST_85xx=" \
MPC8569MDS_NAND \
MPC8572DS \
MPC8572DS_36BIT \
P1022DS \
P2020DS \
P2020DS_36BIT \
P1011RDB \

1
Makefile
View File

@ -221,6 +221,7 @@ LIBS += drivers/power/libpower.a
LIBS += drivers/spi/libspi.a
ifeq ($(CPU),mpc83xx)
LIBS += drivers/qe/qe.a
LIBS += arch/powerpc/cpu/mpc8xxx/lib8xxx.a
endif
ifeq ($(CPU),mpc85xx)
LIBS += drivers/qe/qe.a

66
arch/powerpc/cpu/mpc83xx/cpu.c
View File

@ -126,72 +126,6 @@ int checkcpu(void)
return 0;
}
/*
* Program a UPM with the code supplied in the table.
*
* The 'dummy' variable is used to increment the MAD. 'dummy' is
* supposed to be a pointer to the memory of the device being
* programmed by the UPM. The data in the MDR is written into
* memory and the MAD is incremented every time there's a write
* to 'dummy'. Unfortunately, the current prototype for this
* function doesn't allow for passing the address of this
* device, and changing the prototype will break a number lots
* of other code, so we need to use a round-about way of finding
* the value for 'dummy'.
*
* The value can be extracted from the base address bits of the
* Base Register (BR) associated with the specific UPM. To find
* that BR, we need to scan all 8 BRs until we find the one that
* has its MSEL bits matching the UPM we want. Once we know the
* right BR, we can extract the base address bits from it.
*
* The MxMR and the BR and OR of the chosen bank should all be
* configured before calling this function.
*
* Parameters:
* upm: 0=UPMA, 1=UPMB, 2=UPMC
* table: Pointer to an array of values to program
* size: Number of elements in the array. Must be 64 or less.
*/
void upmconfig (uint upm, uint *table, uint size)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile fsl_lbus_t *lbus = &immap->lbus;
volatile uchar *dummy = NULL;
const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */
volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */
uint i;
/* Scan all the banks to determine the base address of the device */
for (i = 0; i < 8; i++) {
if ((lbus->bank[i].br & BR_MSEL) == msel) {
dummy = (uchar *) (lbus->bank[i].br & BR_BA);
break;
}
}
if (!dummy) {
printf("Error: %s() could not find matching BR\n", __FUNCTION__);
hang();
}
/* Set the OP field in the MxMR to "write" and the MAD field to 000000 */
*mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000;
for (i = 0; i < size; i++) {
lbus->mdr = table[i];
__asm__ __volatile__ ("sync");
*dummy = 0; /* Write the value to memory and increment MAD */
__asm__ __volatile__ ("sync");
while(((*mxmr & 0x3f) != ((i + 1) & 0x3f)));
}
/* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */
*mxmr &= 0xCFFFFFC0;
}
int
do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{

53
arch/powerpc/cpu/mpc83xx/cpu_init.c
View File

@ -236,8 +236,8 @@ void cpu_init_f (volatile immap_t * im)
/* LCRR - Clock Ratio Register (10.3.1.16)
* write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
*/
clrsetbits_be32(&im->lbus.lcrr, lcrr_mask, lcrr_val);
__raw_readl(&im->lbus.lcrr);
clrsetbits_be32(&im->im_lbc.lcrr, lcrr_mask, lcrr_val);
__raw_readl(&im->im_lbc.lcrr);
isync();
/* Enable Time Base & Decrementer ( so we will have udelay() )*/
@ -267,80 +267,41 @@ void cpu_init_f (volatile immap_t * im)
/* Config QE ioports */
config_qe_ioports();
#endif
/* Set up preliminary BR/OR regs */
init_early_memctl_regs();
/*
* Memory Controller:
*/
/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
* addresses - these have to be modified later when FLASH size
* has been determined
*/
#if defined(CONFIG_SYS_BR0_PRELIM) \
&& defined(CONFIG_SYS_OR0_PRELIM) \
&& defined(CONFIG_SYS_LBLAWBAR0_PRELIM) \
&& defined(CONFIG_SYS_LBLAWAR0_PRELIM)
im->lbus.bank[0].br = CONFIG_SYS_BR0_PRELIM;
im->lbus.bank[0].or = CONFIG_SYS_OR0_PRELIM;
/* Local Access window setup */
#if defined(CONFIG_SYS_LBLAWBAR0_PRELIM) && defined(CONFIG_SYS_LBLAWAR0_PRELIM)
im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM;
im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM;
#else
#error CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
#error CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
#endif
#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
im->lbus.bank[1].br = CONFIG_SYS_BR1_PRELIM;
im->lbus.bank[1].or = CONFIG_SYS_OR1_PRELIM;
#endif
#if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM)
im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM;
im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM;
#endif
#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
im->lbus.bank[2].br = CONFIG_SYS_BR2_PRELIM;
im->lbus.bank[2].or = CONFIG_SYS_OR2_PRELIM;
#endif
#if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM;
im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM;
#endif
#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
im->lbus.bank[3].br = CONFIG_SYS_BR3_PRELIM;
im->lbus.bank[3].or = CONFIG_SYS_OR3_PRELIM;
#endif
#if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM)
im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM;
im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM;
#endif
#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
im->lbus.bank[4].br = CONFIG_SYS_BR4_PRELIM;
im->lbus.bank[4].or = CONFIG_SYS_OR4_PRELIM;
#endif
#if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM)
im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM;
im->sysconf.lblaw[4].ar = CONFIG_SYS_LBLAWAR4_PRELIM;
#endif
#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
im->lbus.bank[5].br = CONFIG_SYS_BR5_PRELIM;
im->lbus.bank[5].or = CONFIG_SYS_OR5_PRELIM;
#endif
#if defined(CONFIG_SYS_LBLAWBAR5_PRELIM) && defined(CONFIG_SYS_LBLAWAR5_PRELIM)
im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM;
im->sysconf.lblaw[5].ar = CONFIG_SYS_LBLAWAR5_PRELIM;
#endif
#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
im->lbus.bank[6].br = CONFIG_SYS_BR6_PRELIM;
im->lbus.bank[6].or = CONFIG_SYS_OR6_PRELIM;
#endif
#if defined(CONFIG_SYS_LBLAWBAR6_PRELIM) && defined(CONFIG_SYS_LBLAWAR6_PRELIM)
im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM;
im->sysconf.lblaw[6].ar = CONFIG_SYS_LBLAWAR6_PRELIM;
#endif
#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
im->lbus.bank[7].br = CONFIG_SYS_BR7_PRELIM;
im->lbus.bank[7].or = CONFIG_SYS_OR7_PRELIM;
#endif
#if defined(CONFIG_SYS_LBLAWBAR7_PRELIM) && defined(CONFIG_SYS_LBLAWAR7_PRELIM)
im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM;
im->sysconf.lblaw[7].ar = CONFIG_SYS_LBLAWAR7_PRELIM;

4
arch/powerpc/cpu/mpc83xx/nand_init.c
View File

@ -88,8 +88,8 @@ void cpu_init_f (volatile immap_t * im)
&& defined(CONFIG_SYS_NAND_OR_PRELIM) \
&& defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \
&& defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM)
im->lbus.bank[0].br = CONFIG_SYS_NAND_BR_PRELIM;
im->lbus.bank[0].or = CONFIG_SYS_NAND_OR_PRELIM;
set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM;
im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM;
#else

2
arch/powerpc/cpu/mpc83xx/speed.c
View File

@ -393,7 +393,7 @@ int get_clocks(void)
lbiu_clk = csb_clk *
(1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
switch (lcrr) {
case 2:
case 4:

2
arch/powerpc/cpu/mpc85xx/Makefile
View File

@ -32,6 +32,7 @@ START = start.o resetvec.o
SOBJS-$(CONFIG_MP) += release.o
SOBJS = $(SOBJS-y)
COBJS-$(CONFIG_CMD_ERRATA) += cmd_errata.o
COBJS-$(CONFIG_CPM2) += commproc.o
# supports ddr1
@ -63,6 +64,7 @@ COBJS-$(CONFIG_CPM2) += ether_fcc.o
COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
COBJS-$(CONFIG_MP) += mp.o
COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o
COBJS-$(CONFIG_P1022) += p1022_serdes.o
COBJS-$(CONFIG_PCI) += pci.o
COBJS-$(CONFIG_QE) += qe_io.o
COBJS-$(CONFIG_CPM2) += serial_scc.o

51
arch/powerpc/cpu/mpc85xx/cmd_errata.c Normal file
View File

@ -0,0 +1,51 @@
/*
* Copyright 2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <linux/compiler.h>
#include <asm/processor.h>
static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
__maybe_unused u32 svr = get_svr();
#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
if (IS_SVR_REV(svr, 1, 0)) {
switch (SVR_SOC_VER(svr)) {
case SVR_P1013:
case SVR_P1013_E:
case SVR_P1022:
case SVR_P1022_E:
puts("Work-around for Erratum SATA A001 enabled\n");
}
}
#endif
return 0;
}
U_BOOT_CMD(
errata, 1, 0, do_errata,
"Report errata workarounds",
""
);

106
arch/powerpc/cpu/mpc85xx/cpu.c
View File

@ -32,6 +32,8 @@
#include <fsl_esdhc.h>
#include <asm/cache.h>
#include <asm/io.h>
#include <asm/mmu.h>
#include <asm/fsl_law.h>
DECLARE_GLOBAL_DATA_PTR;
@ -93,18 +95,26 @@ int checkcpu (void)
minor = PVR_MIN(pvr);
printf("Core: ");
switch (fam) {
case PVR_FAM(PVR_85xx):
puts("E500");
break;
default:
puts("Unknown");
break;
if (PVR_FAM(PVR_85xx)) {
switch(PVR_MEM(pvr)) {
case 0x1:
case 0x2:
puts("E500");
break;
case 0x3:
puts("E500MC");
break;
case 0x4:
puts("E5500");
break;
default:
puts("Unknown");
break;
}
} else {
puts("Unknown");
}
if (PVR_MEM(pvr) == 0x03)
puts("MC");
printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
get_sys_info(&sysinfo);
@ -249,71 +259,6 @@ reset_85xx_watchdog(void)
}
#endif /* CONFIG_WATCHDOG */
/*
* Configures a UPM. The function requires the respective MxMR to be set
* before calling this function. "size" is the number or entries, not a sizeof.
*/
void upmconfig (uint upm, uint * table, uint size)
{
int i, mdr, mad, old_mad = 0;
volatile u32 *mxmr;
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile u32 *brp,*orp;
volatile u8* dummy = NULL;
int upmmask;
switch (upm) {
case UPMA:
mxmr = &lbc->mamr;
upmmask = BR_MS_UPMA;
break;
case UPMB:
mxmr = &lbc->mbmr;
upmmask = BR_MS_UPMB;
break;
case UPMC:
mxmr = &lbc->mcmr;
upmmask = BR_MS_UPMC;
break;
default:
printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm);
hang();
}
/* Find the address for the dummy write transaction */
for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8;
i++, brp += 2, orp += 2) {
/* Look for a valid BR with selected UPM */
if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) {
dummy = (volatile u8*)(in_be32(brp) & BR_BA);
break;
}
}
if (i == 8) {
printf("Error: %s() could not find matching BR\n", __FUNCTION__);
hang();
}
for (i = 0; i < size; i++) {
/* 1 */
out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_WARR | i);
/* 2 */
out_be32(&lbc->mdr, table[i]);
/* 3 */
mdr = in_be32(&lbc->mdr);
/* 4 */
*(volatile u8 *)dummy = 0;
/* 5 */
do {
mad = in_be32(mxmr) & MxMR_MAD_MSK;
} while (mad <= old_mad && !(!mad && i == (size-1)));
old_mad = mad;
}
out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_NORM);
}
/*
* Initializes on-chip MMC controllers.
* to override, implement board_mmc_init()
@ -326,3 +271,14 @@ int cpu_mmc_init(bd_t *bis)
return 0;
#endif
}
/*
* Print out the state of various machine registers.
* Currently prints out LAWs, BR0/OR0, and TLBs
*/
void mpc85xx_reginfo(void)
{
print_tlbcam();
print_laws();
print_lbc_regs();
}

58
arch/powerpc/cpu/mpc85xx/cpu_init.c
View File

@ -154,7 +154,6 @@ static void corenet_tb_init(void)
void cpu_init_f (void)
{
volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
extern void m8560_cpm_reset (void);
#ifdef CONFIG_MPC8548
ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
@ -177,60 +176,7 @@ void cpu_init_f (void)
config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
#endif
/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
* addresses - these have to be modified later when FLASH size
* has been determined
*/
#if defined(CONFIG_SYS_OR0_REMAP)
out_be32(&memctl->or0, CONFIG_SYS_OR0_REMAP);
#endif
#if defined(CONFIG_SYS_OR1_REMAP)
out_be32(&memctl->or1, CONFIG_SYS_OR1_REMAP);
#endif
/* now restrict to preliminary range */
/* if cs1 is already set via debugger, leave cs0/cs1 alone */
if (! memctl->br1 & 1) {
#if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM)
out_be32(&memctl->br0, CONFIG_SYS_BR0_PRELIM);
out_be32(&memctl->or0, CONFIG_SYS_OR0_PRELIM);
#endif
#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
out_be32(&memctl->or1, CONFIG_SYS_OR1_PRELIM);
out_be32(&memctl->br1, CONFIG_SYS_BR1_PRELIM);
#endif
}
#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
out_be32(&memctl->or2, CONFIG_SYS_OR2_PRELIM);
out_be32(&memctl->br2, CONFIG_SYS_BR2_PRELIM);
#endif
#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
out_be32(&memctl->or3, CONFIG_SYS_OR3_PRELIM);
out_be32(&memctl->br3, CONFIG_SYS_BR3_PRELIM);
#endif
#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
out_be32(&memctl->or4, CONFIG_SYS_OR4_PRELIM);
out_be32(&memctl->br4, CONFIG_SYS_BR4_PRELIM);
#endif
#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
out_be32(&memctl->or5, CONFIG_SYS_OR5_PRELIM);
out_be32(&memctl->br5, CONFIG_SYS_BR5_PRELIM);
#endif
#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
out_be32(&memctl->or6, CONFIG_SYS_OR6_PRELIM);
out_be32(&memctl->br6, CONFIG_SYS_BR6_PRELIM);
#endif
#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
out_be32(&memctl->or7, CONFIG_SYS_OR7_PRELIM);
out_be32(&memctl->br7, CONFIG_SYS_BR7_PRELIM);
#endif
init_early_memctl_regs();
#if defined(CONFIG_CPM2)
m8560_cpm_reset();
@ -263,7 +209,7 @@ void cpu_init_f (void)
int cpu_init_r(void)
{
#ifdef CONFIG_SYS_LBC_LCRR
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
#endif
puts ("L2: ");

6
arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
View File

@ -25,7 +25,7 @@
void cpu_init_f(void)
{
ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
fsl_lbc_t *lbc = LBC_BASE_ADDR;
/*
* LCRR - Clock Ratio Register - set up local bus timing
@ -34,8 +34,8 @@ void cpu_init_f(void)
out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8);
#if defined(CONFIG_NAND_BR_PRELIM) && defined(CONFIG_NAND_OR_PRELIM)
out_be32(&lbc->br0, CONFIG_NAND_BR_PRELIM);
out_be32(&lbc->or0, CONFIG_NAND_OR_PRELIM);
set_lbc_br(0, CONFIG_NAND_BR_PRELIM);
set_lbc_or(0, CONFIG_NAND_OR_PRELIM);
#else
#error CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must be defined
#endif

4
arch/powerpc/cpu/mpc85xx/fdt.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2007-2009 Freescale Semiconductor, Inc.
* Copyright 2007-2010 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@ -404,8 +404,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
#ifdef CONFIG_MP
ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize);
#endif
ft_fixup_num_cores(blob);
#endif
ft_fixup_cache(blob);

23
arch/powerpc/cpu/mpc85xx/mp.c
View File

@ -77,6 +77,13 @@ int cpu_disable(int nr)
return 0;
}
int is_core_disabled(int nr) {
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 coredisrl = in_be32(&gur->coredisrl);
return (coredisrl & (1 << nr));
}
#else
int cpu_disable(int nr)
{
@ -96,6 +103,22 @@ int cpu_disable(int nr)
return 0;
}
int is_core_disabled(int nr) {
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 devdisr = in_be32(&gur->devdisr);
switch (nr) {
case 0:
return (devdisr & MPC85xx_DEVDISR_CPU0);
case 1:
return (devdisr & MPC85xx_DEVDISR_CPU1);
default:
printf("Invalid cpu number for disable %d\n", nr);
}
return 0;
}
#endif
static u8 boot_entry_map[4] = {

98
arch/powerpc/cpu/mpc85xx/p1022_serdes.c Normal file
View File

@ -0,0 +1,98 @@
/*
* Copyright 2010 Freescale Semiconductor, Inc.
* Author: Timur Tabi <timur@freescale.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*/
#include <config.h>
#include <common.h>
#include <asm/io.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>
#define SRDS1_MAX_LANES 4
#define SRDS2_MAX_LANES 2
static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
[0x00] = {NONE, NONE, NONE, NONE},
[0x01] = {NONE, NONE, NONE, NONE},
[0x02] = {NONE, NONE, NONE, NONE},
[0x03] = {NONE, NONE, NONE, NONE},
[0x04] = {NONE, NONE, NONE, NONE},
[0x06] = {PCIE1, PCIE3, SGMII_TSEC1, PCIE2},
[0x07] = {PCIE1, PCIE3, SGMII_TSEC1, PCIE2},
[0x09] = {PCIE1, NONE, NONE, NONE},
[0x0a] = {PCIE1, PCIE3, SGMII_TSEC1, SGMII_TSEC2},
[0x0b] = {PCIE1, PCIE3, SGMII_TSEC1, SGMII_TSEC2},
[0x0d] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
[0x0e] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
[0x0f] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
[0x15] = {PCIE1, PCIE3, PCIE2, PCIE2},
[0x16] = {PCIE1, PCIE3, PCIE2, PCIE2},
[0x17] = {PCIE1, PCIE3, PCIE2, PCIE2},
[0x18] = {PCIE1, PCIE1, PCIE2, PCIE2},
[0x19] = {PCIE1, PCIE1, PCIE2, PCIE2},
[0x1a] = {PCIE1, PCIE1, PCIE2, PCIE2},
[0x1b] = {PCIE1, PCIE1, PCIE2, PCIE2},
[0x1c] = {PCIE1, PCIE1, PCIE1, PCIE1},
[0x1d] = {PCIE1, PCIE1, PCIE2, PCIE2},
[0x1e] = {PCIE1, PCIE1, PCIE2, PCIE2},
[0x1f] = {PCIE1, PCIE1, PCIE2, PCIE2},
};
static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
[0x00] = {PCIE3, PCIE3},
[0x01] = {PCIE2, PCIE3},
[0x02] = {SATA1, SATA2},
[0x03] = {SGMII_TSEC1, SGMII_TSEC2},
[0x04] = {NONE, NONE},
[0x06] = {SATA1, SATA2},
[0x07] = {NONE, NONE},
[0x09] = {PCIE3, PCIE2},
[0x0a] = {SATA1, SATA2},
[0x0b] = {NONE, NONE},
[0x0d] = {PCIE3, PCIE2},
[0x0e] = {SATA1, SATA2},
[0x0f] = {NONE, NONE},
[0x15] = {SGMII_TSEC1, SGMII_TSEC2},
[0x16] = {SATA1, SATA2},
[0x17] = {NONE, NONE},
[0x18] = {PCIE3, PCIE3},
[0x19] = {SGMII_TSEC1, SGMII_TSEC2},
[0x1a] = {SATA1, SATA2},
[0x1b] = {NONE, NONE},
[0x1c] = {PCIE3, PCIE3},
[0x1d] = {SGMII_TSEC1, SGMII_TSEC2},
[0x1e] = {SATA1, SATA2},
[0x1f] = {NONE, NONE},
};
int is_serdes_configured(enum srds_prtcl device)
{
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
u32 pordevsr = in_be32(&gur->pordevsr);
u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
unsigned int i;
debug("%s: dev = %d\n", __FUNCTION__, device);
debug("PORDEVSR[IO_SEL] = 0x%x\n", srds_cfg);
if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
printf("Invalid PORDEVSR[IO_SEL] = %d\n", srds_cfg);
return 0;
}
for (i = 0; i < SRDS1_MAX_LANES; i++) {
if (serdes1_cfg_tbl[srds_cfg][i] == device)
return 1;
if (serdes2_cfg_tbl[srds_cfg][i] == device)
return 1;
}
return 0;
}

5
arch/powerpc/cpu/mpc85xx/speed.c
View File

@ -172,10 +172,7 @@ void get_sys_info (sys_info_t * sysInfo)
/* We will program LCRR to this value later */
lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
#else
{
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
lcrr_div = in_be32(&lbc->lcrr) & LCRR_CLKDIV;
}
lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
#endif
if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
#if defined(CONFIG_FSL_CORENET)

70
arch/powerpc/cpu/mpc85xx/tlb.c
View File

@ -55,7 +55,45 @@ void init_tlbs(void)
return ;
}
void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
phys_addr_t *rpn)
{
u32 _mas1;
mtspr(MAS0, FSL_BOOKE_MAS0(1, idx, 0));
asm volatile("tlbre;isync");
_mas1 = mfspr(MAS1);
*valid = (_mas1 & MAS1_VALID);
*tsize = (_mas1 >> 8) & 0xf;
*epn = mfspr(MAS2) & MAS2_EPN;
*rpn = mfspr(MAS3) & MAS3_RPN;
#ifdef CONFIG_ENABLE_36BIT_PHYS
*rpn |= ((u64)mfspr(MAS7)) << 32;
#endif
}
#ifndef CONFIG_NAND_SPL
void print_tlbcam(void)
{
int i;
unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;
/* walk all the entries */
printf("TLBCAM entries\n");
for (i = 0; i < num_cam; i++) {
unsigned long epn;
u32 tsize, valid;
phys_addr_t rpn;
read_tlbcam_entry(i, &valid, &tsize, &epn, &rpn);
printf("entry %02d: V: %d EPN 0x%08x RPN 0x%08llx size:",
i, (valid == 0) ? 0 : 1, (unsigned int)epn,
(unsigned long long)rpn);
print_size(TSIZE_TO_BYTES(tsize), "\n");
}
}
static inline void use_tlb_cam(u8 idx)
{
int i = idx / 32;
@ -82,15 +120,9 @@ void init_used_tlb_cams(void)
/* walk all the entries */
for (i = 0; i < num_cam; i++) {
u32 _mas1;
mtspr(MAS0, FSL_BOOKE_MAS0(1, i, 0));
asm volatile("tlbre;isync");
_mas1 = mfspr(MAS1);
/* if the entry isn't valid skip it */
if ((_mas1 & MAS1_VALID))
if (mfspr(MAS1) & MAS1_VALID)
use_tlb_cam(i);
}
}
@ -134,7 +166,7 @@ void set_tlb(u8 tlb, u32 epn, u64 rpn,
#ifdef CONFIG_ADDR_MAP
if ((tlb == 1) && (gd->flags & GD_FLG_RELOC))
addrmap_set_entry(epn, rpn, (1UL << ((tsize * 2) + 10)), esel);
addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), esel);
#endif
}
@ -201,26 +233,12 @@ void init_addr_map(void)
/* walk all the entries */
for (i = 0; i < num_cam; i++) {
unsigned long epn;
u32 tsize, _mas1;
u32 tsize, valid;
phys_addr_t rpn;
mtspr(MAS0, FSL_BOOKE_MAS0(1, i, 0));
asm volatile("tlbre;isync");
_mas1 = mfspr(MAS1);
/* if the entry isn't valid skip it */
if (!(_mas1 & MAS1_VALID))
continue;
tsize = (_mas1 >> 8) & 0xf;
epn = mfspr(MAS2) & MAS2_EPN;
rpn = mfspr(MAS3) & MAS3_RPN;
#ifdef CONFIG_ENABLE_36BIT_PHYS
rpn |= ((phys_addr_t)mfspr(MAS7)) << 32;
#endif
addrmap_set_entry(epn, rpn, (1UL << ((tsize * 2) + 10)), i);
read_tlbcam_entry(i, &valid, &tsize, &epn, &rpn);
if (valid & MAS1_VALID)
addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), i);
}
return ;

15
arch/powerpc/cpu/mpc86xx/cpu.c
View File

@ -180,22 +180,9 @@ watchdog_reset(void)
*/
void mpc86xx_reginfo(void)
{
immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
ccsr_lbc_t *lbc = &immap->im_lbc;
print_bats();
print_laws();
printf ("Local Bus Controller Registers\n"
"\tBR0\t0x%08X\tOR0\t0x%08X \n", in_be32(&lbc->br0), in_be32(&lbc->or0));
printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", in_be32(&lbc->br1), in_be32(&lbc->or1));
printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", in_be32(&lbc->br2), in_be32(&lbc->or2));
printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", in_be32(&lbc->br3), in_be32(&lbc->or3));
printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", in_be32(&lbc->br4), in_be32(&lbc->or4));
printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", in_be32(&lbc->br5), in_be32(&lbc->or5));
printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", in_be32(&lbc->br6), in_be32(&lbc->or6));
printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", in_be32(&lbc->br7), in_be32(&lbc->or7));
print_lbc_regs();
}
/*

55
arch/powerpc/cpu/mpc86xx/cpu_init.c
View File

@ -46,9 +46,6 @@ DECLARE_GLOBAL_DATA_PTR;
void cpu_init_f(void)
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile ccsr_lbc_t *memctl = &immap->im_lbc;
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
@ -61,58 +58,8 @@ void cpu_init_f(void)
setup_bats();
/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
* addresses - these have to be modified later when FLASH size
* has been determined
*/
init_early_memctl_regs();
#if defined(CONFIG_SYS_OR0_REMAP)
memctl->or0 = CONFIG_SYS_OR0_REMAP;
#endif
#if defined(CONFIG_SYS_OR1_REMAP)
memctl->or1 = CONFIG_SYS_OR1_REMAP;
#endif
/* now restrict to preliminary range */
#if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM)
memctl->br0 = CONFIG_SYS_BR0_PRELIM;
memctl->or0 = CONFIG_SYS_OR0_PRELIM;
#endif
#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
memctl->or1 = CONFIG_SYS_OR1_PRELIM;
memctl->br1 = CONFIG_SYS_BR1_PRELIM;
#endif
#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
memctl->or2 = CONFIG_SYS_OR2_PRELIM;
memctl->br2 = CONFIG_SYS_BR2_PRELIM;
#endif
#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
memctl->or3 = CONFIG_SYS_OR3_PRELIM;
memctl->br3 = CONFIG_SYS_BR3_PRELIM;
#endif
#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
memctl->or4 = CONFIG_SYS_OR4_PRELIM;
memctl->br4 = CONFIG_SYS_BR4_PRELIM;
#endif
#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
memctl->or5 = CONFIG_SYS_OR5_PRELIM;
memctl->br5 = CONFIG_SYS_BR5_PRELIM;
#endif
#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
memctl->or6 = CONFIG_SYS_OR6_PRELIM;
memctl->br6 = CONFIG_SYS_BR6_PRELIM;
#endif
#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
memctl->or7 = CONFIG_SYS_OR7_PRELIM;
memctl->br7 = CONFIG_SYS_BR7_PRELIM;
#endif
#if defined(CONFIG_FSL_DMA)
dma_init();
#endif

5
arch/powerpc/cpu/mpc86xx/fdt.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
* Copyright 2008,2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@ -55,6 +55,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
if (off < 0)
printf("%s: %s\n", __FUNCTION__, fdt_strerror(off));
#endif
ft_fixup_num_cores(blob);
#endif
}

17
arch/powerpc/cpu/mpc86xx/mp.c
View File

@ -66,6 +66,23 @@ int cpu_disable(int nr)
return 0;
}
int is_core_disabled(int nr) {
immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
ccsr_gur_t *gur = &immap->im_gur;
u32 devdisr = in_be32(&gur->devdisr);
switch (nr) {
case 0:
return (devdisr & MPC86xx_DEVDISR_CPU0);
case 1:
return (devdisr & MPC86xx_DEVDISR_CPU1);
default:
printf("Invalid cpu number for disable %d\n", nr);
}
return 0;
}
int cpu_release(int nr, int argc, char * const argv[])
{
/* dummy function so common/cmd_mp.c will build

5
arch/powerpc/cpu/mpc86xx/speed.c
View File

@ -97,10 +97,7 @@ void get_sys_info(sys_info_t *sysInfo)
/* We will program LCRR to this value later */
lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
#else
{
volatile ccsr_lbc_t *lbc = &immap->im_lbc;
lcrr_div = in_be32(&lbc->lcrr) & LCRR_CLKDIV;
}
lcrr_div = in_be32(&immap->im_lbc.lcrr) & LCRR_CLKDIV;
#endif
if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
sysInfo->freqLocalBus = sysInfo->freqSystemBus / (lcrr_div * 2);

8
arch/powerpc/cpu/mpc8xxx/Makefile
View File

@ -1,5 +1,5 @@
#
# Copyright 2009 Freescale Semiconductor, Inc.
# Copyright 2009-2010 Freescale Semiconductor, Inc.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License
@ -10,9 +10,13 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib8xxx.a
ifneq ($(CPU),mpc83xx)
COBJS-y += cpu.o
COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
COBJS-$(CONFIG_PCI) += pci_cfg.o
endif
COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o
SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))

178
arch/powerpc/cpu/mpc8xxx/fdt.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2009 Freescale Semiconductor, Inc.
* Copyright 2009-2010 Freescale Semiconductor, Inc.
*
* This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and
* arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains
@ -26,6 +26,27 @@
#include <common.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/mp.h>
#if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx))
static int ft_del_cpuhandle(void *blob, int cpuhandle)
{
int off, ret = -FDT_ERR_NOTFOUND;
/* if we find a match, we'll delete at it which point the offsets are
* invalid so we start over from the beginning
*/
off = fdt_node_offset_by_prop_value(blob, -1, "cpu-handle",
&cpuhandle, 4);
while (off != -FDT_ERR_NOTFOUND) {
fdt_delprop(blob, off, "cpu-handle");
ret = 1;
off = fdt_node_offset_by_prop_value(blob, -1, "cpu-handle",
&cpuhandle, 4);
}
return ret;
}
void ft_fixup_num_cores(void *blob) {
int off, num_cores, del_cores;
@ -37,13 +58,18 @@ void ft_fixup_num_cores(void *blob) {
while (off != -FDT_ERR_NOTFOUND) {
u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
/* if we find a cpu node outside of what we expect delete it
* and reset the offset back to the start since we can't
* trust the offsets anymore
*/
if (*reg > num_cores-1) {
fdt_del_node(blob, off);
del_cores++;
if ((*reg > num_cores-1) || (is_core_disabled(*reg))) {
int ph = fdt_get_phandle(blob, off);
/* Delete the cpu node once there are no cpu handles */
if (-FDT_ERR_NOTFOUND == ft_del_cpuhandle(blob, ph)) {
fdt_del_node(blob, off);
del_cores++;
}
/* either we deleted some cpu handles or the cpu node
* so we reset the offset back to the start since we
* can't trust the offsets anymore
*/
off = -1;
}
off = fdt_node_offset_by_prop_value(blob, off,
@ -53,3 +79,139 @@ void ft_fixup_num_cores(void *blob) {
debug ("deleted %d extra core entry entries from device tree\n",
del_cores);
}
#endif /* defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) */
#ifdef CONFIG_HAS_FSL_DR_USB
void fdt_fixup_dr_usb(void *blob, bd_t *bd)
{
char *mode;
char *type;
const char *compat = "fsl-usb2-dr";
const char *prop_mode = "dr_mode";
const char *prop_type = "phy_type";
int node_offset;
int err;
mode = getenv("usb_dr_mode");
type = getenv("usb_phy_type");
if (!mode && !type)
return;
node_offset = fdt_node_offset_by_compatible(blob, 0, compat);
if (node_offset < 0) {
printf("WARNING: could not find compatible node %s: %s.\n",
compat, fdt_strerror(node_offset));
return;
}
if (mode) {
err = fdt_setprop(blob, node_offset, prop_mode, mode,
strlen(mode) + 1);
if (err < 0)
printf("WARNING: could not set %s for %s: %s.\n",
prop_mode, compat, fdt_strerror(err));
}
if (type) {
err = fdt_setprop(blob, node_offset, prop_type, type,
strlen(type) + 1);
if (err < 0)
printf("WARNING: could not set %s for %s: %s.\n",
prop_type, compat, fdt_strerror(err));
}
}
#endif /* CONFIG_HAS_FSL_DR_USB */
/*
* update crypto node properties to a specified revision of the SEC
* called with sec_rev == 0 if not on an E processor
*/
#if CONFIG_SYS_FSL_SEC_COMPAT == 2 /* SEC 2.x/3.x */
void fdt_fixup_crypto_node(void *blob, int sec_rev)
{
const struct sec_rev_prop {
u32 sec_rev;
u32 num_channels;
u32 channel_fifo_len;
u32 exec_units_mask;
u32 descriptor_types_mask;
} sec_rev_prop_list [] = {
{ 0x0200, 4, 24, 0x07e, 0x01010ebf }, /* SEC 2.0 */
{ 0x0201, 4, 24, 0x0fe, 0x012b0ebf }, /* SEC 2.1 */
{ 0x0202, 1, 24, 0x04c, 0x0122003f }, /* SEC 2.2 */
{ 0x0204, 4, 24, 0x07e, 0x012b0ebf }, /* SEC 2.4 */
{ 0x0300, 4, 24, 0x9fe, 0x03ab0ebf }, /* SEC 3.0 */
{ 0x0301, 4, 24, 0xbfe, 0x03ab0ebf }, /* SEC 3.1 */
{ 0x0303, 4, 24, 0x97c, 0x03a30abf }, /* SEC 3.3 */
};
char compat_strlist[ARRAY_SIZE(sec_rev_prop_list) *
sizeof("fsl,secX.Y")];
int crypto_node, sec_idx, err;
char *p;
u32 val;
/* locate crypto node based on lowest common compatible */
crypto_node = fdt_node_offset_by_compatible(blob, -1, "fsl,sec2.0");
if (crypto_node == -FDT_ERR_NOTFOUND)
return;
/* delete it if not on an E-processor */
if (crypto_node > 0 && !sec_rev) {
fdt_del_node(blob, crypto_node);
return;
}
/* else we got called for possible uprev */
for (sec_idx = 0; sec_idx < ARRAY_SIZE(sec_rev_prop_list); sec_idx++)
if (sec_rev_prop_list[sec_idx].sec_rev == sec_rev)
break;
if (sec_idx == ARRAY_SIZE(sec_rev_prop_list)) {
puts("warning: unknown SEC revision number\n");
return;
}
val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].num_channels);
err = fdt_setprop(blob, crypto_node, "fsl,num-channels", &val, 4);
if (err < 0)
printf("WARNING: could not set crypto property: %s\n",
fdt_strerror(err));
val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].descriptor_types_mask);
err = fdt_setprop(blob, crypto_node, "fsl,descriptor-types-mask", &val, 4);
if (err < 0)
printf("WARNING: could not set crypto property: %s\n",
fdt_strerror(err));
val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].exec_units_mask);
err = fdt_setprop(blob, crypto_node, "fsl,exec-units-mask", &val, 4);
if (err < 0)
printf("WARNING: could not set crypto property: %s\n",
fdt_strerror(err));
val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].channel_fifo_len);
err = fdt_setprop(blob, crypto_node, "fsl,channel-fifo-len", &val, 4);
if (err < 0)
printf("WARNING: could not set crypto property: %s\n",
fdt_strerror(err));
val = 0;
while (sec_idx >= 0) {
p = compat_strlist + val;
val += sprintf(p, "fsl,sec%d.%d",
(sec_rev_prop_list[sec_idx].sec_rev & 0xff00) >> 8,
sec_rev_prop_list[sec_idx].sec_rev & 0x00ff) + 1;
sec_idx--;
}
err = fdt_setprop(blob, crypto_node, "compatible", &compat_strlist, val);
if (err < 0)
printf("WARNING: could not set crypto property: %s\n",
fdt_strerror(err));
}
#elif CONFIG_SYS_FSL_SEC_COMPAT >= 4 /* SEC4 */
void fdt_fixup_crypto_node(void *blob, int sec_rev)
{
if (!sec_rev)
fdt_del_node_and_alias(blob, "crypto");
}
#endif

134
arch/powerpc/cpu/mpc8xxx/fsl_lbc.c Normal file
View File

@ -0,0 +1,134 @@
/*
* Copyright 2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*/
#include <common.h>
#include <asm/fsl_lbc.h>
void print_lbc_regs(void)
{
int i;
printf("\nLocal Bus Controller Registers\n");
for (i = 0; i < 8; i++) {
printf("BR%d\t0x%08X\tOR%d\t0x%08X\n",
i, get_lbc_br(i), i, get_lbc_or(i));
}
}
void init_early_memctl_regs(void)
{
uint init_br1 = 1;
#ifdef CONFIG_MPC85xx
/* if cs1 is already set via debugger, leave cs0/cs1 alone */
if (get_lbc_br(1) & BR_V)
init_br1 = 0;
#endif
/*
* Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at
* preliminary addresses - these have to be modified later
* when FLASH size has been determined
*/
#if defined(CONFIG_SYS_OR0_REMAP)
set_lbc_or(0, CONFIG_SYS_OR0_REMAP);
#endif
#if defined(CONFIG_SYS_OR1_REMAP)
set_lbc_or(1, CONFIG_SYS_OR1_REMAP);
#endif
/* now restrict to preliminary range */
if (init_br1) {
set_lbc_br(0, CONFIG_SYS_BR0_PRELIM);
set_lbc_or(0, CONFIG_SYS_OR0_PRELIM);
#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
set_lbc_or(1, CONFIG_SYS_OR1_PRELIM);
set_lbc_br(1, CONFIG_SYS_BR1_PRELIM);
#endif
}
#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
#endif
#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
#endif
#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);
#endif
#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
set_lbc_or(5, CONFIG_SYS_OR5_PRELIM);
set_lbc_br(5, CONFIG_SYS_BR5_PRELIM);
#endif
#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
set_lbc_or(6, CONFIG_SYS_OR6_PRELIM);
set_lbc_br(6, CONFIG_SYS_BR6_PRELIM);
#endif
#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
set_lbc_or(7, CONFIG_SYS_OR7_PRELIM);
set_lbc_br(7, CONFIG_SYS_BR7_PRELIM);
#endif
}
/*
* Configures a UPM. The function requires the respective MxMR to be set
* before calling this function. "size" is the number or entries, not a sizeof.
*/
void upmconfig(uint upm, uint *table, uint size)
{
fsl_lbc_t *lbc = LBC_BASE_ADDR;
int i, mdr, mad, old_mad = 0;
u32 mask = (~MxMR_OP_MSK & ~MxMR_MAD_MSK);
u32 msel = BR_UPMx_TO_MSEL(upm);
u32 *mxmr = &lbc->mamr + upm;
volatile u8 *dummy = NULL;
if (upm < UPMA || upm > UPMC) {
printf("Error: %s() Bad UPM index %d\n", __func__, upm);
hang();
}
/*
* Find the address for the dummy write - scan all of the BRs until we
* find one matching the UPM and extract the base address bits from it.
*/
for (i = 0; i < 8; i++) {
if ((get_lbc_br(i) & (BR_V | BR_MSEL)) == (BR_V | msel)) {
dummy = (volatile u8 *)(get_lbc_br(i) & BR_BA);
break;
}
}
if (!dummy) {
printf("Error: %s() No matching BR\n", __func__);
hang();
}
/* Program UPM using steps outlined by the reference manual */
for (i = 0; i < size; i++) {
out_be32(mxmr, (in_be32(mxmr) & mask) | MxMR_OP_WARR | i);
out_be32(&lbc->mdr, table[i]);
mdr = in_be32(&lbc->mdr);
*dummy = 0;
do {
mad = in_be32(mxmr) & MxMR_MAD_MSK;
} while (mad <= old_mad && !(!mad && i == (size-1)));
old_mad = mad;
}
/* Return to normal operation */
out_be32(mxmr, (in_be32(mxmr) & mask) | MxMR_OP_NORM);
}

15
arch/powerpc/include/asm/config.h
View File

@ -66,6 +66,15 @@
#define CONFIG_TSECV2
#endif
/*
* SEC (crypto unit) major compatible version determination
*/
#if defined(CONFIG_FSL_CORENET)
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#elif defined(CONFIG_MPC85xx) || defined(CONFIG_MPC83xx)
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#endif
/* Number of TLB CAM entries we have on FSL Book-E chips */
#if defined(CONFIG_E500MC)
#define CONFIG_SYS_NUM_TLBCAMS 64
@ -76,4 +85,10 @@
/* Relocation to SDRAM works on all PPC boards */
#define CONFIG_RELOC_FIXUP_WORKS
/* Since so many PPC SOCs have a semi-common LBC, define this here */
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
defined(CONFIG_MPC83xx)
#define CONFIG_FSL_LBC
#endif
#endif /* _ASM_CONFIG_H_ */

1
arch/powerpc/include/asm/fsl_law.h
View File

@ -47,6 +47,7 @@ enum law_size {
};
#define law_size_bits(sz) (__ilog2_u64(sz) - 1)
#define lawar_size(x) (1ULL << ((x & 0x3f) + 1))
#ifdef CONFIG_FSL_CORENET
enum law_trgt_if {

110
arch/powerpc/include/asm/fsl_lbc.h
View File

@ -14,6 +14,7 @@
#define __ASM_PPC_FSL_LBC_H
#include <config.h>
#include <common.h>
/* BR - Base Registers
*/
@ -61,6 +62,8 @@
#define BR_V 0x00000001
#define BR_V_SHIFT 0
#define BR_UPMx_TO_MSEL(x) ((x + 4) << BR_MSEL_SHIFT)
#define UPMA 0
#define UPMB 1
#define UPMC 2
@ -453,49 +456,70 @@
#define LTESR_CC 0x00000001
#ifndef __ASSEMBLY__
/*
* Local Bus Controller Registers.
*/
typedef struct lbus_bank {
u32 br; /* Base Register */
u32 or; /* Option Register */
} lbus_bank_t;
#include <asm/io.h>
extern void print_lbc_regs(void);
extern void init_early_memctl_regs(void);
extern void upmconfig(uint upm, uint *table, uint size);
#define LBC_BASE_ADDR ((fsl_lbc_t *)CONFIG_SYS_LBC_ADDR)
#define get_lbc_br(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].br))
#define get_lbc_or(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].or))
#define set_lbc_br(i, v) (out_be32(&(LBC_BASE_ADDR)->bank[i].br, v))
#define set_lbc_or(i, v) (out_be32(&(LBC_BASE_ADDR)->bank[i].or, v))
typedef struct lbc_bank {
u32 br;
u32 or;
} lbc_bank_t;
/* Local Bus Controller Registers */
typedef struct fsl_lbc {
lbc_bank_t bank[8];
u8 res1[40];
u32 mar; /* LBC UPM Addr */
u8 res2[4];
u32 mamr; /* LBC UPMA Mode */
u32 mbmr; /* LBC UPMB Mode */
u32 mcmr; /* LBC UPMC Mode */
u8 res3[8];
u32 mrtpr; /* LBC Memory Refresh Timer Prescaler */
u32 mdr; /* LBC UPM Data */
#ifdef CONFIG_FSL_ELBC
u8 res4[4];
u32 lsor;
u8 res5[12];
u32 lurt; /* LBC UPM Refresh Timer */
u8 res6[4];
#else
u8 res4[8];
u32 lsdmr; /* LBC SDRAM Mode */
u8 res5[8];
u32 lurt; /* LBC UPM Refresh Timer */
u32 lsrt; /* LBC SDRAM Refresh Timer */
#endif
u8 res7[8];
u32 ltesr; /* LBC Transfer Error Status */
u32 ltedr; /* LBC Transfer Error Disable */
u32 lteir; /* LBC Transfer Error IRQ */
u32 lteatr; /* LBC Transfer Error Attrs */
u32 ltear; /* LBC Transfer Error Addr */
u8 res8[12];
u32 lbcr; /* LBC Configuration */
u32 lcrr; /* LBC Clock Ratio */
#ifdef CONFIG_NAND_FSL_ELBC
u8 res9[0x8];
u32 fmr; /* Flash Mode Register */
u32 fir; /* Flash Instruction Register */
u32 fcr; /* Flash Command Register */
u32 fbar; /* Flash Block Addr Register */
u32 fpar; /* Flash Page Addr Register */
u32 fbcr; /* Flash Byte Count Register */
u8 res10[0xF08];
#else
u8 res9[0xF28];
#endif
} fsl_lbc_t;
typedef struct fsl_lbus {
lbus_bank_t bank[8];
u8 res0[0x28];
u32 mar; /* UPM Address Register */
u8 res1[0x4];
u32 mamr; /* UPMA Mode Register */
u32 mbmr; /* UPMB Mode Register */
u32 mcmr; /* UPMC Mode Register */
u8 res2[0x8];
u32 mrtpr; /* Memory Refresh Timer Prescaler Register */
u32 mdr; /* UPM Data Register */
u8 res3[0x4];
u32 lsor; /* Special Operation Initiation Register */
u32 lsdmr; /* SDRAM Mode Register */
u8 res4[0x8];
u32 lurt; /* UPM Refresh Timer */
u32 lsrt; /* SDRAM Refresh Timer */
u8 res5[0x8];
u32 ltesr; /* Transfer Error Status Register */
u32 ltedr; /* Transfer Error Disable Register */
u32 lteir; /* Transfer Error Interrupt Register */
u32 lteatr; /* Transfer Error Attributes Register */
u32 ltear; /* Transfer Error Address Register */
u8 res6[0xC];
u32 lbcr; /* Configuration Register */
u32 lcrr; /* Clock Ratio Register */
u8 res7[0x8];
u32 fmr; /* Flash Mode Register */
u32 fir; /* Flash Instruction Register */
u32 fcr; /* Flash Command Register */
u32 fbar; /* Flash Block Addr Register */
u32 fpar; /* Flash Page Addr Register */
u32 fbcr; /* Flash Byte Count Register */
u8 res8[0xF08];
} fsl_lbus_t;
#endif /* __ASSEMBLY__ */
#endif /* __ASM_PPC_FSL_LBC_H */

19
arch/powerpc/include/asm/fsl_pci.h
View File

@ -162,14 +162,15 @@ typedef struct ccsr_pci {
} ccsr_fsl_pci_t;
struct fsl_pci_info {
unsigned long regs;
pci_addr_t mem_bus;
phys_size_t mem_phys;
pci_size_t mem_size;
pci_addr_t io_bus;
phys_size_t io_phys;
pci_size_t io_size;
int pci_num;
unsigned long regs;
pci_addr_t mem_bus;
phys_size_t mem_phys;
pci_size_t mem_size;
pci_addr_t io_bus;
phys_size_t io_phys;
pci_size_t io_size;
enum law_trgt_if law;
int pci_num;
};
int fsl_pci_init_port(struct fsl_pci_info *pci_info,
@ -184,6 +185,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info,
x.io_bus = CONFIG_SYS_PCI##num##_IO_BUS; \
x.io_phys = CONFIG_SYS_PCI##num##_IO_PHYS; \
x.io_size = CONFIG_SYS_PCI##num##_IO_SIZE; \
x.law = LAW_TRGT_IF_PCI_##num; \
x.pci_num = num; \
}
@ -196,6 +198,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info,
x.io_bus = CONFIG_SYS_PCIE##num##_IO_BUS; \
x.io_phys = CONFIG_SYS_PCIE##num##_IO_PHYS; \
x.io_size = CONFIG_SYS_PCIE##num##_IO_SIZE; \
x.law = LAW_TRGT_IF_PCIE_##num; \
x.pci_num = num; \
}

13
arch/powerpc/include/asm/immap_83xx.h
View File

@ -646,7 +646,7 @@ typedef struct immap {
u8 res2[0x1300];
duart83xx_t duart[2]; /* DUART */
u8 res3[0x900];
fsl_lbus_t lbus; /* Local Bus Controller Registers */
fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
u8 res4[0x1000];
spi8xxx_t spi; /* Serial Peripheral Interface */
dma83xx_t dma; /* DMA */
@ -686,7 +686,7 @@ typedef struct immap {
u8 res1[0x1300];
duart83xx_t duart[2]; /* DUART */
u8 res2[0x900];
fsl_lbus_t lbus; /* Local Bus Controller Registers */
fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
u8 res3[0x1000];
spi8xxx_t spi; /* Serial Peripheral Interface */
dma83xx_t dma; /* DMA */
@ -721,7 +721,7 @@ typedef struct immap {
u8 res1[0x1300];
duart83xx_t duart[2]; /* DUART */
u8 res2[0x900];
fsl_lbus_t lbus; /* Local Bus Controller Registers */
fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
u8 res3[0x1000];
spi8xxx_t spi; /* Serial Peripheral Interface */
dma83xx_t dma; /* DMA */
@ -766,7 +766,7 @@ typedef struct immap {
u8 res1[0x1300];
duart83xx_t duart[2]; /* DUART */
u8 res2[0x900];
fsl_lbus_t lbus; /* Local Bus Controller Registers */
fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
u8 res3[0x1000];
spi8xxx_t spi; /* Serial Peripheral Interface */
dma83xx_t dma; /* DMA */
@ -816,7 +816,7 @@ typedef struct immap {
u8 res4[0x1300];
duart83xx_t duart[2]; /* DUART */
u8 res5[0x900];
fsl_lbus_t lbus; /* Local Bus Controller Registers */
fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
u8 res6[0x2000];
dma83xx_t dma; /* DMA */
pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
@ -855,7 +855,7 @@ typedef struct immap {
u8 res3[0x1300];
duart83xx_t duart[2]; /* DUART */
u8 res4[0x900];
fsl_lbus_t lbus; /* Local Bus Controller Registers */
fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
u8 res5[0x2000];
dma83xx_t dma; /* DMA */
pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
@ -879,6 +879,7 @@ typedef struct immap {
#endif
#define CONFIG_SYS_MPC83xx_USB_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB_OFFSET)
#define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
#define CONFIG_SYS_MDIO1_OFFSET 0x24000

84
arch/powerpc/include/asm/immap_85xx.h
View File

@ -266,50 +266,6 @@ typedef struct ccsr_duart {
} ccsr_duart_t;
#endif
/* Local Bus Controller Registers */
typedef struct ccsr_lbc {
u32 br0; /* LBC Base 0 */
u32 or0; /* LBC Options 0 */
u32 br1; /* LBC Base 1 */
u32 or1; /* LBC Options 1 */
u32 br2; /* LBC Base 2 */
u32 or2; /* LBC Options 2 */
u32 br3; /* LBC Base 3 */
u32 or3; /* LBC Options 3 */
u32 br4; /* LBC Base 4 */
u32 or4; /* LBC Options 4 */
u32 br5; /* LBC Base 5 */
u32 or5; /* LBC Options 5 */
u32 br6; /* LBC Base 6 */
u32 or6; /* LBC Options 6 */
u32 br7; /* LBC Base 7 */
u32 or7; /* LBC Options 7 */
u8 res1[40];
u32 mar; /* LBC UPM Addr */
u8 res2[4];
u32 mamr; /* LBC UPMA Mode */
u32 mbmr; /* LBC UPMB Mode */
u32 mcmr; /* LBC UPMC Mode */
u8 res3[8];
u32 mrtpr; /* LBC Memory Refresh Timer Prescaler */
u32 mdr; /* LBC UPM Data */
u8 res4[8];
u32 lsdmr; /* LBC SDRAM Mode */
u8 res5[8];
u32 lurt; /* LBC UPM Refresh Timer */
u32 lsrt; /* LBC SDRAM Refresh Timer */
u8 res6[8];
u32 ltesr; /* LBC Transfer Error Status */
u32 ltedr; /* LBC Transfer Error Disable */
u32 lteir; /* LBC Transfer Error IRQ */
u32 lteatr; /* LBC Transfer Error Attrs */
u32 ltear; /* LBC Transfer Error Addr */
u8 res7[12];
u32 lbcr; /* LBC Configuration */
u32 lcrr; /* LBC Clock Ratio */
u8 res8[3880];
} ccsr_lbc_t;
/* eSPI Registers */
typedef struct ccsr_espi {
u32 mode; /* eSPI mode */
@ -2045,6 +2001,41 @@ enum {
FSL_SRDS_B3_LANE_D = 23,
};
/* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
typedef struct ccsr_sec {
u8 res1[0xfa0];
u32 crnr_ms; /* CHA Revision Number Register, MS */
u32 crnr_ls; /* CHA Revision Number Register, LS */
u32 ctpr_ms; /* Compile Time Parameters Register, MS */
#define SEC_CTPR_MS_AXI_LIODN 0x08000000
#define SEC_CTPR_MS_QI 0x02000000
u32 ctpr_ls; /* Compile Time Parameters Register, LS */
u8 res2[0x10];
u32 far_ms; /* Fault Address Register, MS */
u32 far_ls; /* Fault Address Register, LS */
u32 falr; /* Fault Address LIODN Register */
u32 fadr; /* Fault Address Detail Register */
u8 res3[0x4];
u32 csta; /* CAAM Status Register */
u8 res4[0x8];
u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/
#define SEC_RVID_MA 0x0f000000
u32 ccbvid; /* CHA Cluster Block Version ID Register */
u32 chavid_ms; /* CHA Version ID Register, MS */
u32 chavid_ls; /* CHA Version ID Register, LS */
u32 chanum_ms; /* CHA Number Register, MS */
#define SEC_CHANUM_MS_JQNUM_MASK 0xf0000000
#define SEC_CHANUM_MS_JQNUM_SHIFT 28
#define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000
#define SEC_CHANUM_MS_DECONUM_SHIFT 24
u32 chanum_ls; /* CHA Number Register, LS */
u32 caamvid_ms; /* CAAM Version ID Register, MS */
u32 caamvid_ls; /* CAAM Version ID Register, LS */
u8 res5[0xf000];
} ccsr_sec_t;
#endif
#ifdef CONFIG_FSL_CORENET
#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
#define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000
@ -2059,6 +2050,7 @@ enum {
#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
#define CONFIG_SYS_MPC85xx_USB_OFFSET 0x210000
#define CONFIG_SYS_FSL_SEC_OFFSET 0x300000
#define CONFIG_SYS_FSL_CORENET_QMAN_OFFSET 0x318000
#define CONFIG_SYS_FSL_CORENET_BMAN_OFFSET 0x31a000
#define CONFIG_SYS_TSEC1_OFFSET 0x4e0000 /* FM1@DTSEC0 */
@ -2111,7 +2103,7 @@ enum {
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET)
#define CONFIG_SYS_MPC85xx_DDR2_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET)
#define CONFIG_SYS_MPC85xx_LBC_ADDR \
#define CONFIG_SYS_LBC_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
#define CONFIG_SYS_MPC85xx_ESPI_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET)
@ -2143,6 +2135,8 @@ enum {
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
#define CONFIG_SYS_MPC85xx_USB_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET)
#define CONFIG_SYS_FSL_SEC_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)

49
arch/powerpc/include/asm/immap_86xx.h
View File

@ -12,6 +12,7 @@
#include <asm/types.h>
#include <asm/fsl_dma.h>
#include <asm/fsl_lbc.h>
#include <asm/fsl_i2c.h>
/* Local-Access Registers and MCM Registers(0x0000-0x2000) */
@ -190,51 +191,6 @@ typedef struct ccsr_duart {
char res5[2543];
} ccsr_duart_t;
/* Local Bus Controller Registers(0x5000-0x6000) */
typedef struct ccsr_lbc {
uint br0; /* 0x5000 - LBC Base Register 0 */
uint or0; /* 0x5004 - LBC Options Register 0 */
uint br1; /* 0x5008 - LBC Base Register 1 */
uint or1; /* 0x500c - LBC Options Register 1 */
uint br2; /* 0x5010 - LBC Base Register 2 */
uint or2; /* 0x5014 - LBC Options Register 2 */
uint br3; /* 0x5018 - LBC Base Register 3 */
uint or3; /* 0x501c - LBC Options Register 3 */
uint br4; /* 0x5020 - LBC Base Register 4 */
uint or4; /* 0x5024 - LBC Options Register 4 */
uint br5; /* 0x5028 - LBC Base Register 5 */
uint or5; /* 0x502c - LBC Options Register 5 */
uint br6; /* 0x5030 - LBC Base Register 6 */
uint or6; /* 0x5034 - LBC Options Register 6 */
uint br7; /* 0x5038 - LBC Base Register 7 */
uint or7; /* 0x503c - LBC Options Register 7 */
char res1[40];
uint mar; /* 0x5068 - LBC UPM Address Register */
char res2[4];
uint mamr; /* 0x5070 - LBC UPMA Mode Register */
uint mbmr; /* 0x5074 - LBC UPMB Mode Register */
uint mcmr; /* 0x5078 - LBC UPMC Mode Register */
char res3[8];
uint mrtpr; /* 0x5084 - LBC Memory Refresh Timer Prescaler Register */
uint mdr; /* 0x5088 - LBC UPM Data Register */
char res4[8];
uint lsdmr; /* 0x5094 - LBC SDRAM Mode Register */
char res5[8];
uint lurt; /* 0x50a0 - LBC UPM Refresh Timer */
uint lsrt; /* 0x50a4 - LBC SDRAM Refresh Timer */
char res6[8];
uint ltesr; /* 0x50b0 - LBC Transfer Error Status Register */
uint ltedr; /* 0x50b4 - LBC Transfer Error Disable Register */
uint lteir; /* 0x50b8 - LBC Transfer Error Interrupt Register */
uint lteatr; /* 0x50bc - LBC Transfer Error Attributes Register */
uint ltear; /* 0x50c0 - LBC Transfer Error Address Register */
char res7[12];
uint lbcr; /* 0x50d0 - LBC Configuration Register */
uint lcrr; /* 0x50d4 - LBC Clock Ratio Register */
char res8[3880];
} ccsr_lbc_t;
/* PCI Express Registers(0x8000-0x9000) and (0x9000-0xA000) */
typedef struct ccsr_pex {
uint cfg_addr; /* 0x8000 - PEX Configuration Address Register */
@ -1270,7 +1226,7 @@ typedef struct immap {
ccsr_ddr_t im_ddr1;
ccsr_i2c_t im_i2c;
ccsr_duart_t im_duart;
ccsr_lbc_t im_lbc;
fsl_lbc_t im_lbc;
ccsr_ddr_t im_ddr2;
char res1[4096];
ccsr_pex_t im_pex1;
@ -1303,6 +1259,7 @@ extern immap_t *immr;
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
#define CONFIG_SYS_MDIO1_OFFSET 0x24000
#define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)

2
arch/powerpc/include/asm/mmu.h
View File

@ -402,6 +402,7 @@ extern void print_bats(void);
#define MAS1_TID(x) ((x << 16) & 0x3FFF0000)
#define MAS1_TS 0x00001000
#define MAS1_TSIZE(x) ((x << 8) & 0x00000F00)
#define TSIZE_TO_BYTES(x) ((phys_addr_t)(1UL << ((tsize * 2) + 10)))
#define MAS2_EPN 0xFFFFF000
#define MAS2_X0 0x00000040
@ -485,6 +486,7 @@ extern void init_tlbs(void);
extern int find_tlb_idx(void *addr, u8 tlbsel);
extern void init_used_tlb_cams(void);
extern int find_free_tlbcam(void);
extern void print_tlbcam(void);
extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg);

3
arch/powerpc/include/asm/mp.h
View File

@ -1,5 +1,5 @@
/*
* Copyright 2009 Freescale Semiconductor, Inc.
* Copyright 2009-2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@ -26,5 +26,6 @@
void setup_mp(void);
void cpu_mp_lmb_reserve(struct lmb *lmb);
u32 determine_mp_bootpg(void);
int is_core_disabled(int nr);
#endif

4
arch/powerpc/include/asm/processor.h
View File

@ -534,9 +534,11 @@
#define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */
#define SPRN_MCSRR1 0x23b /* Machine Check Save and Restore Register 1 */
#define SPRN_BUCSR 0x3f5 /* Branch Control and Status Register */
#define BUCSR_STAC_EN 0x01000000 /* Segment target addr cache enable */
#define BUCSR_LS_EN 0x00400000 /* Link stack enable */
#define BUCSR_BBFI 0x00000200 /* Branch buffer flash invalidate */
#define BUCSR_BPEN 0x00000001 /* Branch prediction enable */
#define BUCSR_ENABLE (BUCSR_BBFI|BUCSR_BPEN)
#define BUCSR_ENABLE (BUCSR_STAC_EN|BUCSR_LS_EN|BUCSR_BBFI|BUCSR_BPEN)
#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
#define SPRN_PID1 0x279 /* Process ID Register 1 */

2
board/atum8548/atum8548.c
View File

@ -47,7 +47,7 @@ int board_early_init_f (void)
int checkboard (void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
if ((uint)&gur->porpllsr != 0xe00e0000) {

2
board/esd/vme8349/vme8349.c
View File

@ -105,7 +105,7 @@ int misc_init_r()
{
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
clrsetbits_be32(&im->lbus.lcrr, LBCR_LDIS, 0);
clrsetbits_be32(&im->im_lbc.lcrr, LBCR_LDIS, 0);
return 0;
}

4
board/freescale/common/Makefile
View File

@ -42,6 +42,10 @@ COBJS-$(CONFIG_MPC8541CDS) += cds_pci_ft.o
COBJS-$(CONFIG_MPC8548CDS) += cds_pci_ft.o
COBJS-$(CONFIG_MPC8555CDS) += cds_pci_ft.o
COBJS-$(CONFIG_MPC8536DS) += ics307_clk.o
COBJS-$(CONFIG_MPC8572DS) += ics307_clk.o
COBJS-$(CONFIG_P1022DS) += ics307_clk.o
COBJS-$(CONFIG_P2020DS) += ics307_clk.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))

88
board/freescale/common/ics307_clk.c Normal file
View File

@ -0,0 +1,88 @@
/*
* Copyright 2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include "ics307_clk.h"
#ifdef CONFIG_FSL_NGPIXIS
#include "ngpixis.h"
#else
#include "pixis.h"
#endif
/* decode S[0-2] to Output Divider (OD) */
static u8 ics307_s_to_od[] = {
10, 2, 8, 4, 5, 7, 3, 6
};
/*
* Calculate frequency being generated by ICS307-02 clock chip based upon
* the control bytes being programmed into it.
*/
static unsigned long ics307_clk_freq(u8 cw0, u8 cw1, u8 cw2)
{
const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ;
unsigned long vdw = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
unsigned long rdw = cw2 & 0x7F;
unsigned long od = ics307_s_to_od[cw0 & 0x7];
unsigned long freq;
/*
* CLK1 Freq = Input Frequency * 2 * (VDW + 8) / ((RDW + 2) * OD)
*
* cw0: C1 C0 TTL F1 F0 S2 S1 S0
* cw1: V8 V7 V6 V5 V4 V3 V2 V1
* cw2: V0 R6 R5 R4 R3 R2 R1 R0
*
* R6:R0 = Reference Divider Word (RDW)
* V8:V0 = VCO Divider Word (VDW)
* S2:S0 = Output Divider Select (OD)
* F1:F0 = Function of CLK2 Output
* TTL = duty cycle
* C1:C0 = internal load capacitance for cyrstal
*
*/
freq = input_freq * 2 * (vdw + 8) / ((rdw + 2) * od);
debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2,
freq);
return freq;
}
unsigned long get_board_sys_clk(void)
{
return ics307_clk_freq(
in_8(&pixis->sclk[0]),
in_8(&pixis->sclk[1]),
in_8(&pixis->sclk[2]));
}
unsigned long get_board_ddr_clk(void)
{
return ics307_clk_freq(
in_8(&pixis->dclk[0]),
in_8(&pixis->dclk[1]),
in_8(&pixis->dclk[2]));
}

30
board/freescale/common/ics307_clk.h Normal file
View File

@ -0,0 +1,30 @@
/*
* Copyright 2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ICS_CLK_H_
#define __ICS_CLK_H_ 1
#ifndef __ASSEMBLY__
extern unsigned long get_board_sys_clk(void);
extern unsigned long get_board_ddr_clk(void);
#endif
#endif /* __ICS_CLK_H_ */

2
board/freescale/common/ngpixis.h
View File

@ -45,7 +45,7 @@ typedef struct ngpixis {
u8 sw;
u8 en;
} s[8];
} ngpixis_t __attribute__ ((aligned(1)));
} __attribute__ ((packed)) ngpixis_t;
/* Pointer to the PIXIS register set */
#define pixis ((ngpixis_t *)PIXIS_BASE)

182
board/freescale/common/pixis.h Normal file
View File

@ -0,0 +1,182 @@
/*
* Copyright 2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __PIXIS_H_
#define __PIXIS_H_ 1
/* PIXIS register set. */
#if defined(CONFIG_MPC8536DS)
typedef struct pixis {
u8 id;
u8 ver;
u8 pver;
u8 csr;
u8 rst;
u8 rst2;
u8 aux1;
u8 spd;
u8 aux2;
u8 csr2;
u8 watch;
u8 led;
u8 pwr;
u8 res[3];
u8 vctl;
u8 vstat;
u8 vcfgen0;
u8 vcfgen1;
u8 vcore0;
u8 res1;
u8 vboot;
u8 vspeed[3];
u8 sclk[3];
u8 dclk[3];
u8 i2cdacr;
u8 vcoreacc[4];
u8 vcorecnt[3];
u8 vcoremax[2];
u8 vplatacc[4];
u8 vplatcnt[3];
u8 vplatmax[2];
u8 vtempacc[4];
u8 vtempcnt[3];
u8 vtempmax[2];
u8 res2[4];
} __attribute__ ((packed)) pixis_t;
#elif defined(CONFIG_MPC8544DS)
typedef struct pixis {
u8 id;
u8 ver;
u8 pver;
u8 csr;
u8 rst;
u8 pwr;
u8 aux1;
u8 spd;
u8 res[8];
u8 vctl;
u8 vstat;
u8 vcfgen0;
u8 vcfgen1;
u8 vcore0;
u8 res1;
u8 vboot;
u8 vspeed[2];
u8 vclkh;
u8 vclkl;
u8 watch;
u8 led;
u8 vspeed2;
u8 res2[34];
} __attribute__ ((packed)) pixis_t;
#elif defined(CONFIG_MPC8572DS)
typedef struct pixis {
u8 id;
u8 ver;
u8 pver;
u8 csr;
u8 rst;
u8 pwr1;
u8 aux1;
u8 spd;
u8 aux2;
u8 res[7];
u8 vctl;
u8 vstat;
u8 vcfgen0;
u8 vcfgen1;
u8 vcore0;
u8 res1;
u8 vboot;
u8 vspeed[3];
u8 res2[2];
u8 sclk[3];
u8 dclk[3];
u8 res3[2];
u8 watch;
u8 led;
u8 res4[25];
} __attribute__ ((packed)) pixis_t;
#elif defined(CONFIG_MPC8610HPCD)
typedef struct pixis {
u8 id;
u8 ver; /* also called arch */
u8 pver;
u8 csr;
u8 rst;
u8 pwr;
u8 aux;
u8 spd;
u8 brdcfg0;
u8 brdcfg1;
u8 res[4];
u8 led;
u8 serno;
u8 vctl;
u8 vstat;
u8 vcfgen0;
u8 vcfgen1;
u8 vcore0;
u8 res1;
u8 vboot;
u8 vspeed[2];
u8 res2;
u8 sclk[3];
u8 res3;
u8 watch;
u8 res4[33];
} __attribute__ ((packed)) pixis_t;
#elif defined(CONFIG_MPC8641HPCN)
typedef struct pixis {
u8 id;
u8 ver;
u8 pver;
u8 csr;
u8 rst;
u8 pwr;
u8 aux;
u8 spd;
u8 res[8];
u8 vctl;
u8 vstat;
u8 vcfgen0;
u8 vcfgen1;
u8 vcore0;
u8 res1;
u8 vboot;
u8 vspeed[2];
u8 vclkh;
u8 vclkl;
u8 watch;
u8 res3[36];
} __attribute__ ((packed)) pixis_t;
#else
#error Need to define pixis_t for this board
#endif
/* Pointer to the PIXIS register set */
#define pixis ((pixis_t *)PIXIS_BASE)
#endif /* __PIXIS_H_ */

2
board/freescale/mpc8313erdb/sdram.c
View File

@ -110,7 +110,7 @@ static long fixed_sdram(void)
phys_size_t initdram(int board_type)
{
volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile fsl_lbus_t *lbc = &im->lbus;
volatile fsl_lbc_t *lbc = &im->im_lbc;
u32 msize;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)

2
board/freescale/mpc8349emds/mpc8349emds.c
View File

@ -192,7 +192,7 @@ int checkboard (void)
void sdram_init(void)
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile fsl_lbus_t *lbc = &immap->lbus;
volatile fsl_lbc_t *lbc = &immap->im_lbc;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
/*

7
board/freescale/mpc8349itx/mpc8349itx.c
View File

@ -221,15 +221,14 @@ int misc_init_f(void)
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
};
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile fsl_lbus_t *lbus = &immap->lbus;
lbus->bank[3].br = CONFIG_SYS_BR3_PRELIM;
lbus->bank[3].or = CONFIG_SYS_OR3_PRELIM;
set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
/* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000,
GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000
*/
lbus->mamr = 0x08404440;
immap->im_lbc.mamr = 0x08404440;
upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));

6
board/freescale/mpc8360emds/mpc8360emds.c
View File

@ -280,7 +280,7 @@ int checkboard(void)
static int sdram_init(unsigned int base)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile fsl_lbus_t *lbc = &immap->lbus;
fsl_lbc_t *lbc = LBC_BASE_ADDR;
const int sdram_size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
int rem = base % sdram_size;
uint *sdram_addr;
@ -293,8 +293,8 @@ static int sdram_init(unsigned int base)
/*
* Setup SDRAM Base and Option Registers
*/
immap->lbus.bank[2].br = base | CONFIG_SYS_BR2;
immap->lbus.bank[2].or = CONFIG_SYS_OR2;
set_lbc_br(2, base | CONFIG_SYS_BR2);
set_lbc_or(2, CONFIG_SYS_OR2);
immap->sysconf.lblaw[2].bar = base;
immap->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2;

6
board/freescale/mpc8360erdk/nand.c
View File

@ -82,9 +82,9 @@ static struct fsl_upm_nand fun = {
int board_nand_init(struct nand_chip *nand)
{
fun.upm.mxmr = &im->lbus.mamr;
fun.upm.mdr = &im->lbus.mdr;
fun.upm.mar = &im->lbus.mar;
fun.upm.mxmr = &im->im_lbc.mamr;
fun.upm.mdr = &im->im_lbc.mdr;
fun.upm.mar = &im->im_lbc.mar;
upm_setup(&fun.upm);

148
board/freescale/mpc8536ds/mpc8536ds.c
View File

@ -350,154 +350,6 @@ int board_early_init_r(void)
return 0;
}
#ifdef CONFIG_GET_CLK_FROM_ICS307
/* decode S[0-2] to Output Divider (OD) */
static unsigned char
ics307_S_to_OD[] = {
10, 2, 8, 4, 5, 7, 3, 6
};
/* Calculate frequency being generated by ICS307-02 clock chip based upon
* the control bytes being programmed into it. */
/* XXX: This function should probably go into a common library */
static unsigned long
ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2)
{
const unsigned long long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
unsigned long RDW = cw2 & 0x7F;
unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
unsigned long freq;
/* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
/* cw0: C1 C0 TTL F1 F0 S2 S1 S0
* cw1: V8 V7 V6 V5 V4 V3 V2 V1
* cw2: V0 R6 R5 R4 R3 R2 R1 R0
*
* R6:R0 = Reference Divider Word (RDW)
* V8:V0 = VCO Divider Word (VDW)
* S2:S0 = Output Divider Select (OD)
* F1:F0 = Function of CLK2 Output
* TTL = duty cycle
* C1:C0 = internal load capacitance for cyrstal
*/
/* Adding 1 to get a "nicely" rounded number, but this needs
* more tweaking to get a "properly" rounded number. */
freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2,
freq);
return freq;
}
unsigned long
get_board_sys_clk(ulong dummy)
{
u8 *pixis_base = (u8 *)PIXIS_BASE;
return ics307_clk_freq (
in_8(pixis_base + PIXIS_VSYSCLK0),
in_8(pixis_base + PIXIS_VSYSCLK1),
in_8(pixis_base + PIXIS_VSYSCLK2)
);
}
unsigned long
get_board_ddr_clk(ulong dummy)
{
u8 *pixis_base = (u8 *)PIXIS_BASE;
return ics307_clk_freq (
in_8(pixis_base + PIXIS_VDDRCLK0),
in_8(pixis_base + PIXIS_VDDRCLK1),
in_8(pixis_base + PIXIS_VDDRCLK2)
);
}
#else
unsigned long
get_board_sys_clk(ulong dummy)
{
u8 i;
ulong val = 0;
u8 *pixis_base = (u8 *)PIXIS_BASE;
i = in_8(pixis_base + PIXIS_SPD);
i &= 0x07;
switch (i) {
case 0:
val = 33333333;
break;
case 1:
val = 40000000;
break;
case 2:
val = 50000000;
break;
case 3:
val = 66666666;
break;
case 4:
val = 83333333;
break;
case 5:
val = 100000000;
break;
case 6:
val = 133333333;
break;
case 7:
val = 166666666;
break;
}
return val;
}
unsigned long
get_board_ddr_clk(ulong dummy)
{
u8 i;
ulong val = 0;
u8 *pixis_base = (u8 *)PIXIS_BASE;
i = in_8(pixis_base + PIXIS_SPD);
i &= 0x38;
i >>= 3;
switch (i) {
case 0:
val = 33333333;
break;
case 1:
val = 40000000;
break;
case 2:
val = 50000000;
break;
case 3:
val = 66666666;
break;
case 4:
val = 83333333;
break;
case 5:
val = 100000000;
break;
case 6:
val = 133333333;
break;
case 7:
val = 166666666;
break;
}
return val;
}
#endif
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_TSEC_ENET

8
board/freescale/mpc8540ads/mpc8540ads.c
View File

@ -117,7 +117,7 @@ void
local_bus_init(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
uint lbc_hz;
@ -176,7 +176,7 @@ local_bus_init(void)
void
sdram_init(void)
{
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
puts(" SDRAM: ");
@ -185,8 +185,8 @@ sdram_init(void)
/*
* Setup SDRAM Base and Option Registers
*/
lbc->or2 = CONFIG_SYS_OR2_PRELIM;
lbc->br2 = CONFIG_SYS_BR2_PRELIM;
set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
lbc->lbcr = CONFIG_SYS_LBC_LBCR;
asm("msync");

13
board/freescale/mpc8541cds/mpc8541cds.c
View File

@ -291,7 +291,7 @@ void
local_bus_init(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
uint lbc_hz;
@ -340,7 +340,7 @@ sdram_init(void)
#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
uint idx;
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
uint cpu_board_rev;
uint lsdmr_common;
@ -352,16 +352,11 @@ sdram_init(void)
/*
* Setup SDRAM Base and Option Registers
*/
lbc->or2 = CONFIG_SYS_OR2_PRELIM;
asm("msync");
lbc->br2 = CONFIG_SYS_BR2_PRELIM;
asm("msync");
set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
lbc->lbcr = CONFIG_SYS_LBC_LBCR;
asm("msync");
lbc->lsrt = CONFIG_SYS_LBC_LSRT;
lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
asm("msync");

2
board/freescale/mpc8544ds/mpc8544ds.c
View File

@ -40,7 +40,7 @@
int checkboard (void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
u8 vboot;
u8 *pixis_base = (u8 *)PIXIS_BASE;

13
board/freescale/mpc8548cds/mpc8548cds.c
View File

@ -118,7 +118,7 @@ void
local_bus_init(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
uint lbc_hz;
@ -154,7 +154,7 @@ sdram_init(void)
#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
uint idx;
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
uint cpu_board_rev;
uint lsdmr_common;
@ -166,16 +166,11 @@ sdram_init(void)
/*
* Setup SDRAM Base and Option Registers
*/
lbc->or2 = CONFIG_SYS_OR2_PRELIM;
asm("msync");
lbc->br2 = CONFIG_SYS_BR2_PRELIM;
asm("msync");
set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
lbc->lbcr = CONFIG_SYS_LBC_LBCR;
asm("msync");
lbc->lsrt = CONFIG_SYS_LBC_LSRT;
lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
asm("msync");

12
board/freescale/mpc8555cds/mpc8555cds.c
View File

@ -291,7 +291,7 @@ void
local_bus_init(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
uint lbc_hz;
@ -340,7 +340,7 @@ sdram_init(void)
#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
uint idx;
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
uint cpu_board_rev;
uint lsdmr_common;
@ -352,12 +352,8 @@ sdram_init(void)
/*
* Setup SDRAM Base and Option Registers
*/
lbc->or2 = CONFIG_SYS_OR2_PRELIM;
asm("msync");
lbc->br2 = CONFIG_SYS_BR2_PRELIM;
asm("msync");
set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
lbc->lbcr = CONFIG_SYS_LBC_LBCR;
asm("msync");

8
board/freescale/mpc8560ads/mpc8560ads.c
View File

@ -322,7 +322,7 @@ void
local_bus_init(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
uint lbc_hz;
@ -381,7 +381,7 @@ local_bus_init(void)
void
sdram_init(void)
{
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
puts(" SDRAM: ");
@ -390,8 +390,8 @@ sdram_init(void)
/*
* Setup SDRAM Base and Option Registers
*/
lbc->or2 = CONFIG_SYS_OR2_PRELIM;
lbc->br2 = CONFIG_SYS_BR2_PRELIM;
set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
lbc->lbcr = CONFIG_SYS_LBC_LBCR;
asm("msync");

11
board/freescale/mpc8568mds/mpc8568mds.c
View File

@ -181,7 +181,7 @@ void
local_bus_init(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
uint lbc_hz;
@ -214,7 +214,7 @@ sdram_init(void)
#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
uint idx;
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
uint lsdmr_common;
@ -225,16 +225,13 @@ sdram_init(void)
/*
* Setup SDRAM Base and Option Registers
*/
lbc->or2 = CONFIG_SYS_OR2_PRELIM;
asm("msync");
lbc->br2 = CONFIG_SYS_BR2_PRELIM;
set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
asm("msync");
lbc->lbcr = CONFIG_SYS_LBC_LBCR;
asm("msync");
lbc->lsrt = CONFIG_SYS_LBC_LSRT;
lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
asm("msync");

2
board/freescale/mpc8569mds/mpc8569mds.c
View File

@ -308,7 +308,7 @@ void
local_bus_init(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
uint lbc_hz;

145
board/freescale/mpc8572ds/mpc8572ds.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2007-2009 Freescale Semiconductor, Inc.
* Copyright 2007-2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -284,149 +284,6 @@ int board_early_init_r(void)
return 0;
}
#ifdef CONFIG_GET_CLK_FROM_ICS307
/* decode S[0-2] to Output Divider (OD) */
static unsigned char ics307_S_to_OD[] = {
10, 2, 8, 4, 5, 7, 3, 6
};
/* Calculate frequency being generated by ICS307-02 clock chip based upon
* the control bytes being programmed into it. */
/* XXX: This function should probably go into a common library */
static unsigned long
ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2)
{
const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
unsigned long RDW = cw2 & 0x7F;
unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
unsigned long freq;
/* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
/* cw0: C1 C0 TTL F1 F0 S2 S1 S0
* cw1: V8 V7 V6 V5 V4 V3 V2 V1
* cw2: V0 R6 R5 R4 R3 R2 R1 R0
*
* R6:R0 = Reference Divider Word (RDW)
* V8:V0 = VCO Divider Word (VDW)
* S2:S0 = Output Divider Select (OD)
* F1:F0 = Function of CLK2 Output
* TTL = duty cycle
* C1:C0 = internal load capacitance for cyrstal
*/
/* Adding 1 to get a "nicely" rounded number, but this needs
* more tweaking to get a "properly" rounded number. */
freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2,
freq);
return freq;
}
unsigned long get_board_sys_clk(ulong dummy)
{
u8 *pixis_base = (u8 *)PIXIS_BASE;
return ics307_clk_freq (
in_8(pixis_base + PIXIS_VSYSCLK0),
in_8(pixis_base + PIXIS_VSYSCLK1),
in_8(pixis_base + PIXIS_VSYSCLK2)
);
}
unsigned long get_board_ddr_clk(ulong dummy)
{
u8 *pixis_base = (u8 *)PIXIS_BASE;
return ics307_clk_freq (
in_8(pixis_base + PIXIS_VDDRCLK0),
in_8(pixis_base + PIXIS_VDDRCLK1),
in_8(pixis_base + PIXIS_VDDRCLK2)
);
}
#else
unsigned long get_board_sys_clk(ulong dummy)
{
u8 i;
ulong val = 0;
u8 *pixis_base = (u8 *)PIXIS_BASE;
i = in_8(pixis_base + PIXIS_SPD);
i &= 0x07;
switch (i) {
case 0:
val = 33333333;
break;
case 1:
val = 40000000;
break;
case 2:
val = 50000000;
break;
case 3:
val = 66666666;
break;
case 4:
val = 83333333;
break;
case 5:
val = 100000000;
break;
case 6:
val = 133333333;
break;
case 7:
val = 166666666;
break;
}
return val;
}
unsigned long get_board_ddr_clk(ulong dummy)
{
u8 i;
ulong val = 0;
u8 *pixis_base = (u8 *)PIXIS_BASE;
i = in_8(pixis_base + PIXIS_SPD);
i &= 0x38;
i >>= 3;
switch (i) {
case 0:
val = 33333333;
break;
case 1:
val = 40000000;
break;
case 2:
val = 50000000;
break;
case 3:
val = 66666666;
break;
case 4:
val = 83333333;
break;
case 5:
val = 100000000;
break;
case 6:
val = 133333333;
break;
case 7:
val = 166666666;
break;
}
return val;
}
#endif
#ifdef CONFIG_TSEC_ENET
int board_eth_init(bd_t *bis)
{

39
board/freescale/p1022ds/Makefile Normal file
View File

@ -0,0 +1,39 @@
#
# Copyright 2010 Freescale Semiconductor, Inc.
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the Free
# Software Foundation; either version 2 of the License, or (at your option)
# any later version.
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS-y += $(BOARD).o
COBJS-y += ddr.o
COBJS-y += law.o
COBJS-y += tlb.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(OBJS) $(SOBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

14
board/freescale/p1022ds/config.mk Normal file
View File

@ -0,0 +1,14 @@
#
# Copyright 2010 Freescale Semiconductor, Inc.
#
# This program is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the Free
# Software Foundation; either version 2 of the License, or (at your option)
# any later version.
#
ifndef TEXT_BASE
TEXT_BASE = 0xeff80000
endif
RESET_VECTOR_ADDRESS = 0xeffffffc

106
board/freescale/p1022ds/ddr.c Normal file
View File

@ -0,0 +1,106 @@
/*
* Copyright 2010 Freescale Semiconductor, Inc.
* Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
* Timur Tabi <timur@freescale.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*/
#include <common.h>
#include <i2c.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
unsigned int fsl_ddr_get_mem_data_rate(void)
{
return get_ddr_freq(0);
}
void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num)
{
int ret;
/*
* The P1022 has only one DDR controller, and the board has only one
* DIMM slot.
*/
ret = i2c_read(SPD_EEPROM_ADDRESS1, 0, 1, (u8 *)ctrl_dimms_spd,
sizeof(ddr3_spd_eeprom_t));
if (ret) {
debug("DDR: failed to read SPD from address %u\n",
SPD_EEPROM_ADDRESS1);
memset(ctrl_dimms_spd, 0, sizeof(ddr3_spd_eeprom_t));
}
}
typedef struct {
u32 datarate_mhz_low;
u32 datarate_mhz_high;
u32 n_ranks;
u32 clk_adjust; /* Range: 0-8 */
u32 cpo; /* Range: 2-31 */
u32 write_data_delay; /* Range: 0-6 */
u32 force_2T;
} board_specific_parameters_t;
static const board_specific_parameters_t bsp[] = {
/*
* lo| hi| num| clk| cpo|wrdata|2T
* mhz| mhz|ranks|adjst| | delay|
*/
{ 0, 333, 1, 5, 31, 3, 0},
{334, 400, 1, 5, 31, 3, 0},
{401, 549, 1, 5, 31, 3, 0},
{550, 680, 1, 5, 31, 5, 0},
{681, 850, 1, 5, 31, 5, 0},
{ 0, 333, 2, 5, 31, 3, 0},
{334, 400, 2, 5, 31, 3, 0},
{401, 549, 2, 5, 31, 3, 0},
{550, 680, 2, 5, 31, 5, 0},
{681, 850, 2, 5, 31, 5, 0},
};
void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm,
unsigned int ctrl_num)
{
unsigned long ddr_freq;
unsigned int i;
/* set odt_rd_cfg and odt_wr_cfg. */
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
popts->cs_local_opts[i].odt_rd_cfg = 0;
popts->cs_local_opts[i].odt_wr_cfg = 1;
}
/*
* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
* freqency and n_banks specified in board_specific_parameters table.
*/
ddr_freq = get_ddr_freq(0) / 1000000;
for (i = 0; i < ARRAY_SIZE(bsp); i++) {
if (ddr_freq >= bsp[i].datarate_mhz_low &&
ddr_freq <= bsp[i].datarate_mhz_high &&
pdimm->n_ranks == bsp[i].n_ranks) {
popts->clk_adjust = bsp[i].clk_adjust;
popts->cpo_override = bsp[i].cpo;
popts->write_data_delay = bsp[i].write_data_delay;
popts->twoT_en = bsp[i].force_2T;
break;
}
}
popts->half_strength_driver_enable = 1;
/* Per AN4039, enable ZQ calibration. */
popts->zq_en = 1;
/*
* For wake-up on ARP, we need auto self refresh enabled
*/
popts->auto_self_refresh_en = 1;
popts->sr_it = 0xb;
}

21
board/freescale/p1022ds/law.c Normal file
View File

@ -0,0 +1,21 @@
/*
* Copyright 2010 Freescale Semiconductor, Inc.
* Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
* Timur Tabi <timur@freescale.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*/
#include <common.h>
#include <asm/fsl_law.h>
#include <asm/mmu.h>
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
};
int num_law_entries = ARRAY_SIZE(law_table);

354
board/freescale/p1022ds/p1022ds.c Normal file
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@ -0,0 +1,354 @@
/*
* Copyright 2010 Freescale Semiconductor, Inc.
* Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
* Timur Tabi <timur@freescale.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*/
#include <common.h>
#include <command.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/io.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <tsec.h>
#include <asm/fsl_law.h>
#include <asm/mp.h>
#include <netdev.h>
#include <i2c.h>
#include "../common/ngpixis.h"
DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void)
{
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
/* Set pmuxcr to allow both i2c1 and i2c2 */
setbits_be32(&gur->pmuxcr, 0x1000);
/* Read back the register to synchronize the write. */
in_be32(&gur->pmuxcr);
/* Set the pin muxing to enable ETSEC2. */
clrbits_be32(&gur->pmuxcr2, 0x001F8000);
return 0;
}
int checkboard(void)
{
u8 sw;
puts("Board: P1022DS ");
printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
switch ((sw & PIXIS_LBMAP_MASK) >> 6) {
case 0:
printf ("vBank: %u\n", ((sw & 0x30) >> 4));
break;
case 1:
printf ("NAND\n");
break;
case 2:
case 3:
puts ("Promjet\n");
break;
}
return 0;
}
phys_size_t initdram(int board_type)
{
phys_size_t dram_size = 0;
puts("Initializing....\n");
dram_size = fsl_ddr_sdram();
dram_size = setup_ddr_tlbs(dram_size / 0x100000) * 0x100000;
puts(" DDR: ");
return dram_size;
}
#define CONFIG_TFP410_I2C_ADDR 0x38
int misc_init_r(void)
{
u8 temp;
/* Enable the TFP410 Encoder */
temp = 0xBF;
if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
return -1;
/* Verify if enabled */
temp = 0;
if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
return -1;
debug("DVI Encoder Read: 0x%02x\n", temp);
temp = 0x10;
if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
return -1;
/* Verify if enabled */
temp = 0;
if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
return -1;
debug("DVI Encoder Read: 0x%02x\n",temp);
return 0;
}
/*
* A list of PCI and SATA slots
*/
enum slot_id {
SLOT_PCIE1 = 1,
SLOT_PCIE2,
SLOT_PCIE3,
SLOT_PCIE4,
SLOT_PCIE5,
SLOT_SATA1,
SLOT_SATA2
};
/*
* This array maps the slot identifiers to their names on the P1022DS board.
*/
static const char *slot_names[] = {
[SLOT_PCIE1] = "Slot 1",
[SLOT_PCIE2] = "Slot 2",
[SLOT_PCIE3] = "Slot 3",
[SLOT_PCIE4] = "Slot 4",
[SLOT_PCIE5] = "Mini-PCIe",
[SLOT_SATA1] = "SATA 1",
[SLOT_SATA2] = "SATA 2",
};
/*
* This array maps a given SERDES configuration and SERDES device to the PCI or
* SATA slot that it connects to. This mapping is hard-coded in the FPGA.
*/
static u8 serdes_dev_slot[][SATA2 + 1] = {
[0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 },
[0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
[0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4,
[PCIE2] = SLOT_PCIE5 },
[0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
[PCIE2] = SLOT_PCIE3,
[SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
[0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
[PCIE2] = SLOT_PCIE3 },
[0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3,
[PCIE2] = SLOT_PCIE3,
[SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
[0x1c] = { [PCIE1] = SLOT_PCIE1,
[SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
[0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 },
[0x1f] = { [PCIE1] = SLOT_PCIE1 },
};
/*
* Returns the name of the slot to which the PCIe or SATA controller is
* connected
*/
const char *serdes_slot_name(enum srds_prtcl device)
{
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
u32 pordevsr = in_be32(&gur->pordevsr);
unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
enum slot_id slot = serdes_dev_slot[srds_cfg][device];
const char *name = slot_names[slot];
if (name)
return name;
else
return "Nothing";
}
static void configure_pcie(struct fsl_pci_info *info,
struct pci_controller *hose,
const char *connected)
{
static int bus_number = 0;
int is_endpoint;
set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law);
set_next_law(info->io_phys, law_size_bits(info->io_size), info->law);
is_endpoint = fsl_setup_hose(hose, info->regs);
printf(" PCIE%u connected to %s as %s (base addr %lx)\n",
info->pci_num, connected,
is_endpoint ? "Endpoint" : "Root Complex", info->regs);
bus_number = fsl_pci_init_port(info, hose, bus_number);
}
#ifdef CONFIG_PCIE1
static struct pci_controller pcie1_hose;
#endif
#ifdef CONFIG_PCIE2
static struct pci_controller pcie2_hose;
#endif
#ifdef CONFIG_PCIE3
static struct pci_controller pcie3_hose;
#endif
#ifdef CONFIG_PCI
void pci_init_board(void)
{
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
struct fsl_pci_info pci_info;
u32 devdisr = in_be32(&gur->devdisr);
#ifdef CONFIG_PCIE1
if (is_serdes_configured(PCIE1) && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
SET_STD_PCIE_INFO(pci_info, 1);
configure_pcie(&pci_info, &pcie1_hose, serdes_slot_name(PCIE1));
} else {
printf(" PCIE1: disabled\n");
}
#else
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
#endif
#ifdef CONFIG_PCIE2
if (is_serdes_configured(PCIE2) && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
SET_STD_PCIE_INFO(pci_info, 2);
configure_pcie(&pci_info, &pcie2_hose, serdes_slot_name(PCIE2));
} else {
printf(" PCIE2: disabled\n");
}
#else
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
#endif
#ifdef CONFIG_PCIE3
if (is_serdes_configured(PCIE3) && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
SET_STD_PCIE_INFO(pci_info, 3);
configure_pcie(&pci_info, &pcie3_hose, serdes_slot_name(PCIE3));
} else {
printf(" PCIE3: disabled\n");
}
#else
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
#endif
}
#endif
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
* so that flash can be erased properly.
*/
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
return 0;
}
/*
* Initialize on-board and/or PCI Ethernet devices
*
* Returns:
* <0, error
* 0, no ethernet devices found
* >0, number of ethernet devices initialized
*/
int board_eth_init(bd_t *bis)
{
struct tsec_info_struct tsec_info[2];
unsigned int num = 0;
#ifdef CONFIG_TSEC1
SET_STD_TSEC_INFO(tsec_info[num], 1);
num++;
#endif
#ifdef CONFIG_TSEC2
SET_STD_TSEC_INFO(tsec_info[num], 2);
num++;
#endif
return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis);
}
#ifdef CONFIG_OF_BOARD_SETUP
void ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
ft_cpu_setup(blob, bd);
base = getenv_bootm_low();
size = getenv_bootm_size();
fdt_fixup_memory(blob, (u64)base, (u64)size);
#ifdef CONFIG_PCIE1
ft_fsl_pci_setup(blob, "pci0", &pcie1_hose);
#else
ft_fsl_pci_setup(blob, "pci0", NULL);
#endif
#ifdef CONFIG_PCIE2
ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
#else
ft_fsl_pci_setup(blob, "pci1", NULL);
#endif
#ifdef CONFIG_PCIE3
ft_fsl_pci_setup(blob, "pci2", &pcie3_hose);
#else
ft_fsl_pci_setup(blob, "pci2", NULL);
#endif
#ifdef CONFIG_FSL_SGMII_RISER
fsl_sgmii_riser_fdt_fixup(blob);
#endif
}
#endif
#ifdef CONFIG_MP
void board_lmb_reserve(struct lmb *lmb)
{
cpu_mp_lmb_reserve(lmb);
}
#endif

76
board/freescale/p1022ds/tlb.c Normal file
View File

@ -0,0 +1,76 @@
/*
* Copyright 2010 Freescale Semiconductor, Inc.
* Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
* Timur Tabi <timur@freescale.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*/
#include <common.h>
#include <asm/mmu.h>
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
/* TLB 1 */
/* *I*** - Covers boot page */
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
0, 0, BOOKE_PAGESZ_4K, 1),
/* *I*G* - CCSRBAR */
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1M, 1),
/* W**G* - Flash/promjet, localbus */
/* This will be changed to *I*G* after relocation to RAM. */
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_1G, 1),
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_256M, 1),
/* *I*G* - PCI I/O */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_256K, 1),
SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_4K, 1),
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);

149
board/freescale/p2020ds/p2020ds.c
View File

@ -313,155 +313,6 @@ int board_early_init_r(void)
return 0;
}
#ifdef CONFIG_GET_CLK_FROM_ICS307
/* decode S[0-2] to Output Divider (OD) */
static unsigned char ics307_S_to_OD[] = {
10, 2, 8, 4, 5, 7, 3, 6
};
/* Calculate frequency being generated by ICS307-02 clock chip based upon
* the control bytes being programmed into it. */
/* XXX: This function should probably go into a common library */
static unsigned long
ics307_clk_freq(unsigned char cw0, unsigned char cw1, unsigned char cw2)
{
const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
unsigned long RDW = cw2 & 0x7F;
unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
unsigned long freq;
/* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
/* cw0: C1 C0 TTL F1 F0 S2 S1 S0
* cw1: V8 V7 V6 V5 V4 V3 V2 V1
* cw2: V0 R6 R5 R4 R3 R2 R1 R0
*
* R6:R0 = Reference Divider Word (RDW)
* V8:V0 = VCO Divider Word (VDW)
* S2:S0 = Output Divider Select (OD)
* F1:F0 = Function of CLK2 Output
* TTL = duty cycle
* C1:C0 = internal load capacitance for cyrstal
*/
/* Adding 1 to get a "nicely" rounded number, but this needs
* more tweaking to get a "properly" rounded number. */
freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2,
freq);
return freq;
}
unsigned long get_board_sys_clk(ulong dummy)
{
return gd->bus_clk;
}
unsigned long get_board_ddr_clk(ulong dummy)
{
return gd->mem_clk;
}
unsigned long calculate_board_sys_clk(ulong dummy)
{
ulong val;
val = ics307_clk_freq(in_8(&pixis->sclk[0]), in_8(&pixis->sclk[1]),
in_8(&pixis->sclk[2]));
debug("sysclk val = %lu\n", val);
return val;
}
unsigned long calculate_board_ddr_clk(ulong dummy)
{
ulong val;
val = ics307_clk_freq(in_8(&pixis->dclk[0]), in_8(&pixis->dclk[1]),
in_8(&pixis->dclk[2]));
debug("ddrclk val = %lu\n", val);
return val;
}
#else
unsigned long get_board_sys_clk(ulong dummy)
{
u8 i;
ulong val = 0;
i = in_8(&pixis->spd);
i &= 0x07;
switch (i) {
case 0:
val = 33333333;
break;
case 1:
val = 40000000;
break;
case 2:
val = 50000000;
break;
case 3:
val = 66666666;
break;
case 4:
val = 83333333;
break;
case 5:
val = 100000000;
break;
case 6:
val = 133333333;
break;
case 7:
val = 166666666;
break;
}
return val;
}
unsigned long get_board_ddr_clk(ulong dummy)
{
u8 i;
ulong val = 0;
i = in_8(&pixis->spd);
i &= 0x38;
i >>= 3;
switch (i) {
case 0:
val = 33333333;
break;
case 1:
val = 40000000;
break;
case 2:
val = 50000000;
break;
case 3:
val = 66666666;
break;
case 4:
val = 83333333;
break;
case 5:
val = 100000000;
break;
case 6:
val = 133333333;
break;
case 7:
val = 166666666;
break;
}
return val;
}
#endif
#ifdef CONFIG_TSEC_ENET
int board_eth_init(bd_t *bis)
{

6
board/mpc8540eval/mpc8540eval.c
View File

@ -69,7 +69,7 @@ phys_size_t initdram (int board_type)
long dram_size = 0;
#if !defined(CONFIG_RAM_AS_FLASH)
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
sys_info_t sysinfo;
uint temp_lbcdll = 0;
#endif
@ -110,8 +110,8 @@ phys_size_t initdram (int board_type)
gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
asm("sync;isync;msync");
}
lbc->or2 = CONFIG_SYS_OR2_PRELIM; /* 64MB SDRAM */
lbc->br2 = CONFIG_SYS_BR2_PRELIM;
set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); /* 64MB SDRAM */
set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
lbc->lbcr = CONFIG_SYS_LBC_LBCR;
lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
asm("sync");

2
board/pm854/pm854.c
View File

@ -134,7 +134,7 @@ void
local_bus_init(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
uint lbc_hz;

2
board/pm856/pm856.c
View File

@ -290,7 +290,7 @@ void
local_bus_init(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
uint lbc_hz;

2
board/sbc8349/sbc8349.c
View File

@ -160,7 +160,7 @@ int checkboard (void)
void sdram_init(void)
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile fsl_lbus_t *lbc = &immap->lbus;
volatile fsl_lbc_t *lbc = &immap->im_lbc;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
puts("\n SDRAM on Local Bus: ");

20
board/sbc8548/sbc8548.c
View File

@ -116,7 +116,7 @@ void
local_bus_init(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
uint lbc_hz;
@ -152,7 +152,7 @@ sdram_init(void)
#if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
uint idx;
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
uint lsdmr_common;
@ -163,22 +163,14 @@ sdram_init(void)
/*
* Setup SDRAM Base and Option Registers
*/
out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM);
asm("msync");
out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM);
asm("msync");
out_be32(&lbc->or4, CONFIG_SYS_OR4_PRELIM);
asm("msync");
out_be32(&lbc->br4, CONFIG_SYS_BR4_PRELIM);
asm("msync");
set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);
out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
asm("msync");
out_be32(&lbc->lsrt, CONFIG_SYS_LBC_LSRT);
out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
asm("msync");

6
board/sbc8560/sbc8560.c
View File

@ -269,7 +269,7 @@ phys_size_t initdram (int board_type)
#if 0
#if !defined(CONFIG_RAM_AS_FLASH)
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
sys_info_t sysinfo;
uint temp_lbcdll = 0;
#endif
@ -310,8 +310,8 @@ phys_size_t initdram (int board_type)
gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
asm("sync;isync;msync");
}
lbc->or2 = CONFIG_SYS_OR2_PRELIM; /* 64MB SDRAM */
lbc->br2 = CONFIG_SYS_BR2_PRELIM;
set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); /* 64MB SDRAM */
set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
lbc->lbcr = CONFIG_SYS_LBC_LBCR;
lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
asm("sync");

2
board/sheldon/simpc8313/sdram.c
View File

@ -129,7 +129,7 @@ void si_read_i2c(u32 lbyte, int count, u8 *buffer)
phys_size_t initdram(int board_type)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile fsl_lbus_t *lbc= &im->lbus;
volatile fsl_lbc_t *lbc = &im->im_lbc;
u32 msize;
if ((__raw_readl(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32) im)

2
board/sheldon/simpc8313/simpc8313.c
View File

@ -93,7 +93,7 @@ int misc_init_r(void)
{
int rc = 0;
immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
fsl_lbus_t *lbus = &immap->lbus;
fsl_lbc_t *lbus = &immap->im_lbc;
u32 *mxmr = &lbus->mamr; /* Pointer to mamr */
/* UPM Table Configuration Code */

31
board/socrates/socrates.c
View File

@ -87,8 +87,6 @@ int checkboard (void)
int misc_init_r (void)
{
volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
/*
* Adjust flash start and offset to detected values
*/
@ -99,8 +97,10 @@ int misc_init_r (void)
* Check if boot FLASH isn't max size
*/
if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) {
memctl->or0 = gd->bd->bi_flashstart | (CONFIG_SYS_OR0_PRELIM & 0x00007fff);
memctl->br0 = gd->bd->bi_flashstart | (CONFIG_SYS_BR0_PRELIM & 0x00007fff);
set_lbc_or(0, gd->bd->bi_flashstart |
(CONFIG_SYS_OR0_PRELIM & 0x00007fff));
set_lbc_br(0, gd->bd->bi_flashstart |
(CONFIG_SYS_BR0_PRELIM & 0x00007fff));
/*
* Re-check to get correct base address
@ -112,8 +112,8 @@ int misc_init_r (void)
* Check if only one FLASH bank is available
*/
if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
memctl->or1 = 0;
memctl->br1 = 0;
set_lbc_or(1, 0);
set_lbc_br(1, 0);
/*
* Re-do flash protection upon new addresses
@ -148,7 +148,7 @@ int misc_init_r (void)
*/
void local_bus_init (void)
{
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
sys_info_t sysinfo;
uint clkdiv;
@ -299,26 +299,25 @@ const gdc_regs *board_get_regs (void)
int lime_probe(void)
{
volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
uint cfg_br2;
uint cfg_or2;
int type;
cfg_br2 = memctl->br2;
cfg_or2 = memctl->or2;
cfg_br2 = get_lbc_br(2);
cfg_or2 = get_lbc_or(2);
/* Configure GPCM for CS2 */
memctl->br2 = 0;
memctl->or2 = 0xfc000410;
memctl->br2 = (CONFIG_SYS_LIME_BASE) | 0x00001901;
set_lbc_br(2, 0);
set_lbc_or(2, 0xfc000410);
set_lbc_br(2, (CONFIG_SYS_LIME_BASE) | 0x00001901);
/* Get controller type */
type = mb862xx_probe(CONFIG_SYS_LIME_BASE);
/* Restore previous CS2 configuration */
memctl->br2 = 0;
memctl->or2 = cfg_or2;
memctl->br2 = cfg_br2;
set_lbc_br(2, 0);
set_lbc_or(2, cfg_or2);
set_lbc_br(2, cfg_br2);
return (type == MB862XX_TYPE_LIME) ? 1 : 0;
}

8
board/tqc/tqm834x/tqm834x.c
View File

@ -253,10 +253,10 @@ static int detect_num_flash_banks(void)
debug("Number of flash banks detected: %d\n", tqm834x_num_flash_banks);
/* set OR0 and BR0 */
im->lbus.bank[0].or = CONFIG_SYS_OR_TIMING_FLASH |
(-(total_size) & OR_GPCM_AM);
im->lbus.bank[0].br = (CONFIG_SYS_FLASH_BASE & BR_BA) |
(BR_MS_GPCM | BR_PS_32 | BR_V);
set_lbc_or(0, CONFIG_SYS_OR_TIMING_FLASH |
(-(total_size) & OR_GPCM_AM));
set_lbc_br(0, (CONFIG_SYS_FLASH_BASE & BR_BA) |
(BR_MS_GPCM | BR_PS_32 | BR_V));
return (0);
}

12
board/tqc/tqm85xx/nand.c
View File

@ -377,7 +377,7 @@ volatile const u32 *nand_upm_patt;
*/
static void upmb_write (u_char addr, ulong val)
{
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
out_be32 (&lbc->mdr, val);
@ -393,14 +393,14 @@ static void upmb_write (u_char addr, ulong val)
/*
* Initialize UPM for NAND flash access.
*/
static void nand_upm_setup (volatile ccsr_lbc_t *lbc)
static void nand_upm_setup (volatile fsl_lbc_t *lbc)
{
uint i, j;
uint or3 = CONFIG_SYS_OR3_PRELIM;
uint clock = get_lbc_clock ();
out_be32 (&lbc->br3, 0); /* disable bank and reset all bits */
out_be32 (&lbc->br3, CONFIG_SYS_BR3_PRELIM);
set_lbc_br(3, 0); /* disable bank and reset all bits */
set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
/*
* Search appropriate UPM table for bus clock.
@ -424,7 +424,7 @@ static void nand_upm_setup (volatile ccsr_lbc_t *lbc)
/* EAD must be set due to TQM8548 timing specification */
or3 |= OR_UPM_EAD;
out_be32 (&lbc->or3, or3);
set_lbc_or(3, or3);
/* Assign address of table */
nand_upm_patt = upm_freq_table[i].upm_patt;
@ -458,7 +458,7 @@ void board_nand_select_device (struct nand_chip *nand, int chip)
int board_nand_init (struct nand_chip *nand)
{
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
if (!nand_upm_patt)
nand_upm_setup (lbc);

35
board/tqc/tqm85xx/tqm85xx.c
View File

@ -269,8 +269,6 @@ int checkboard (void)
int misc_init_r (void)
{
volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
/*
* Adjust flash start and offset to detected values
*/
@ -281,26 +279,27 @@ int misc_init_r (void)
* Recalculate CS configuration if second FLASH bank is available
*/
if (flash_info[0].size > 0) {
memctl->or1 = ((-flash_info[0].size) & 0xffff8000) |
(CONFIG_SYS_OR1_PRELIM & 0x00007fff);
memctl->br1 = gd->bd->bi_flashstart |
(CONFIG_SYS_BR1_PRELIM & 0x00007fff);
set_lbc_or(1, ((-flash_info[0].size) & 0xffff8000) |
(CONFIG_SYS_OR1_PRELIM & 0x00007fff));
set_lbc_br(1, gd->bd->bi_flashstart |
(CONFIG_SYS_BR1_PRELIM & 0x00007fff));
/*
* Re-check to get correct base address for bank 1
*/
flash_get_size (gd->bd->bi_flashstart, 0);
} else {
memctl->or1 = 0;
memctl->br1 = 0;
set_lbc_or(1, 0);
set_lbc_br(1, 0);
}
/*
* If bank 1 is equipped, bank 0 is mapped after bank 1
*/
memctl->or0 = ((-flash_info[1].size) & 0xffff8000) |
(CONFIG_SYS_OR0_PRELIM & 0x00007fff);
memctl->br0 = (gd->bd->bi_flashstart + flash_info[0].size) |
(CONFIG_SYS_BR0_PRELIM & 0x00007fff);
set_lbc_or(0, ((-flash_info[1].size) & 0xffff8000) |
(CONFIG_SYS_OR0_PRELIM & 0x00007fff));
set_lbc_br(0, gd->bd->bi_flashstart |
(CONFIG_SYS_BR0_PRELIM & 0x00007fff));
/*
* Re-check to get correct base address for bank 0
*/
@ -341,7 +340,7 @@ int misc_init_r (void)
*/
static void upmc_write (u_char addr, uint val)
{
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
out_be32 (&lbc->mdr, val);
@ -358,7 +357,7 @@ static void upmc_write (u_char addr, uint val)
uint get_lbc_clock (void)
{
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
sys_info_t sys_info;
ulong clkdiv = lbc->lcrr & LCRR_CLKDIV;
@ -386,7 +385,7 @@ uint get_lbc_clock (void)
void local_bus_init (void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint lbc_mhz = get_lbc_clock () / 1000000;
#ifdef CONFIG_MPC8548
@ -502,10 +501,10 @@ void local_bus_init (void)
* set if Local Bus Clock is > 83 MHz.
*/
if (lbc_mhz > 83)
out_be32 (&lbc->or2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD);
set_lbc_or(2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD);
else
out_be32 (&lbc->or2, CONFIG_SYS_OR2_CAN);
out_be32 (&lbc->br2, CONFIG_SYS_BR2_CAN);
set_lbc_or(2, CONFIG_SYS_OR2_CAN);
set_lbc_br(2, CONFIG_SYS_BR2_CAN);
/* LGPL4 is UPWAIT */
out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X);

10
board/xes/xpedite5170/xpedite5170.c
View File

@ -56,8 +56,6 @@ int checkboard(void)
*/
static void flash_cs_fixup(void)
{
immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
ccsr_lbc_t *lbc = &immap->im_lbc;
int flash_sel;
/*
@ -70,11 +68,11 @@ static void flash_cs_fixup(void)
printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
if (flash_sel) {
out_be32(&lbc->br0, CONFIG_SYS_BR1_PRELIM);
out_be32(&lbc->or0, CONFIG_SYS_OR1_PRELIM);
set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
out_be32(&lbc->br1, CONFIG_SYS_BR0_PRELIM);
out_be32(&lbc->or1, CONFIG_SYS_OR0_PRELIM);
set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
}
}

11
board/xes/xpedite5200/xpedite5200.c
View File

@ -38,7 +38,7 @@ extern void ft_board_pci_setup(void *blob, bd_t *bd);
int checkboard(void)
{
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
char *s;
@ -65,7 +65,6 @@ int checkboard(void)
static void flash_cs_fixup(void)
{
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
int flash_sel;
/*
@ -78,11 +77,11 @@ static void flash_cs_fixup(void)
printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
if (flash_sel) {
out_be32(&lbc->br0, CONFIG_SYS_BR1_PRELIM);
out_be32(&lbc->or0, CONFIG_SYS_OR1_PRELIM);
set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
out_be32(&lbc->br1, CONFIG_SYS_BR0_PRELIM);
out_be32(&lbc->or1, CONFIG_SYS_OR0_PRELIM);
set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
}
}

9
board/xes/xpedite5370/xpedite5370.c
View File

@ -58,7 +58,6 @@ int checkboard(void)
static void flash_cs_fixup(void)
{
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
int flash_sel;
/*
@ -71,11 +70,11 @@ static void flash_cs_fixup(void)
printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
if (flash_sel) {
out_be32(&lbc->br0, CONFIG_SYS_BR1_PRELIM);
out_be32(&lbc->or0, CONFIG_SYS_OR1_PRELIM);
set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
out_be32(&lbc->br1, CONFIG_SYS_BR0_PRELIM);
out_be32(&lbc->or1, CONFIG_SYS_OR0_PRELIM);
set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
}
}

1
boards.cfg
View File

@ -346,6 +346,7 @@ MPC8560ADS powerpc mpc85xx mpc8560ads freescale
MPC8568MDS powerpc mpc85xx mpc8568mds freescale
XPEDITE5200 powerpc mpc85xx xpedite5200 xes
XPEDITE5370 powerpc mpc85xx xpedite5370 xes
P1022DS powerpc mpc85xx p1022ds freescale
sbc8641d powerpc mpc86xx
MPC8610HPCD powerpc mpc86xx mpc8610hpcd freescale
XPEDITE5170 powerpc mpc86xx xpedite5170 xes

5
common/cmd_reginfo.c
View File

@ -33,6 +33,8 @@ extern void ppc4xx_reginfo(void);
#include <mpc5xxx.h>
#elif defined (CONFIG_MPC86xx)
extern void mpc86xx_reginfo(void);
#elif defined(CONFIG_MPC85xx)
extern void mpc85xx_reginfo(void);
#endif
int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
@ -183,6 +185,9 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#elif defined(CONFIG_MPC86xx)
mpc86xx_reginfo();
#elif defined(CONFIG_MPC85xx)
mpc85xx_reginfo();
#elif defined(CONFIG_BLACKFIN)
puts("\nSystem Configuration registers\n");

129
common/fdt_support.c
View File

@ -474,135 +474,6 @@ void fdt_fixup_ethernet(void *fdt)
}
}
#ifdef CONFIG_HAS_FSL_DR_USB
void fdt_fixup_dr_usb(void *blob, bd_t *bd)
{
char *mode;
char *type;
const char *compat = "fsl-usb2-dr";
const char *prop_mode = "dr_mode";
const char *prop_type = "phy_type";
int node_offset;
int err;
mode = getenv("usb_dr_mode");
type = getenv("usb_phy_type");
if (!mode && !type)
return;
node_offset = fdt_node_offset_by_compatible(blob, 0, compat);
if (node_offset < 0) {
printf("WARNING: could not find compatible node %s: %s.\n",
compat, fdt_strerror(node_offset));
return;
}
if (mode) {
err = fdt_setprop(blob, node_offset, prop_mode, mode,
strlen(mode) + 1);
if (err < 0)
printf("WARNING: could not set %s for %s: %s.\n",
prop_mode, compat, fdt_strerror(err));
}
if (type) {
err = fdt_setprop(blob, node_offset, prop_type, type,
strlen(type) + 1);
if (err < 0)
printf("WARNING: could not set %s for %s: %s.\n",
prop_type, compat, fdt_strerror(err));
}
}
#endif /* CONFIG_HAS_FSL_DR_USB */
#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx)
/*
* update crypto node properties to a specified revision of the SEC
* called with sec_rev == 0 if not on an mpc8xxxE processor
*/
void fdt_fixup_crypto_node(void *blob, int sec_rev)
{
const struct sec_rev_prop {
u32 sec_rev;
u32 num_channels;
u32 channel_fifo_len;
u32 exec_units_mask;
u32 descriptor_types_mask;
} sec_rev_prop_list [] = {
{ 0x0200, 4, 24, 0x07e, 0x01010ebf }, /* SEC 2.0 */
{ 0x0201, 4, 24, 0x0fe, 0x012b0ebf }, /* SEC 2.1 */
{ 0x0202, 1, 24, 0x04c, 0x0122003f }, /* SEC 2.2 */
{ 0x0204, 4, 24, 0x07e, 0x012b0ebf }, /* SEC 2.4 */
{ 0x0300, 4, 24, 0x9fe, 0x03ab0ebf }, /* SEC 3.0 */
{ 0x0301, 4, 24, 0xbfe, 0x03ab0ebf }, /* SEC 3.1 */
{ 0x0303, 4, 24, 0x97c, 0x03a30abf }, /* SEC 3.3 */
};
char compat_strlist[ARRAY_SIZE(sec_rev_prop_list) *
sizeof("fsl,secX.Y")];
int crypto_node, sec_idx, err;
char *p;
u32 val;
/* locate crypto node based on lowest common compatible */
crypto_node = fdt_node_offset_by_compatible(blob, -1, "fsl,sec2.0");
if (crypto_node == -FDT_ERR_NOTFOUND)
return;
/* delete it if not on an E-processor */
if (crypto_node > 0 && !sec_rev) {
fdt_del_node(blob, crypto_node);
return;
}
/* else we got called for possible uprev */
for (sec_idx = 0; sec_idx < ARRAY_SIZE(sec_rev_prop_list); sec_idx++)
if (sec_rev_prop_list[sec_idx].sec_rev == sec_rev)
break;
if (sec_idx == ARRAY_SIZE(sec_rev_prop_list)) {
puts("warning: unknown SEC revision number\n");
return;
}
val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].num_channels);
err = fdt_setprop(blob, crypto_node, "fsl,num-channels", &val, 4);
if (err < 0)
printf("WARNING: could not set crypto property: %s\n",
fdt_strerror(err));
val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].descriptor_types_mask);
err = fdt_setprop(blob, crypto_node, "fsl,descriptor-types-mask", &val, 4);
if (err < 0)
printf("WARNING: could not set crypto property: %s\n",
fdt_strerror(err));
val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].exec_units_mask);
err = fdt_setprop(blob, crypto_node, "fsl,exec-units-mask", &val, 4);
if (err < 0)
printf("WARNING: could not set crypto property: %s\n",
fdt_strerror(err));
val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].channel_fifo_len);
err = fdt_setprop(blob, crypto_node, "fsl,channel-fifo-len", &val, 4);
if (err < 0)
printf("WARNING: could not set crypto property: %s\n",
fdt_strerror(err));
val = 0;
while (sec_idx >= 0) {
p = compat_strlist + val;
val += sprintf(p, "fsl,sec%d.%d",
(sec_rev_prop_list[sec_idx].sec_rev & 0xff00) >> 8,
sec_rev_prop_list[sec_idx].sec_rev & 0x00ff) + 1;
sec_idx--;
}
err = fdt_setprop(blob, crypto_node, "compatible", &compat_strlist, val);
if (err < 0)
printf("WARNING: could not set crypto property: %s\n",
fdt_strerror(err));
}
#endif /* defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) */
/* Resize the fdt to its actual size + a bit of padding */
int fdt_resize(void *blob)
{

137
drivers/misc/fsl_law.c
View File

@ -50,33 +50,61 @@ DECLARE_GLOBAL_DATA_PTR;
#endif
#ifdef CONFIG_FSL_CORENET
#define LAW_BASE (CONFIG_SYS_FSL_CORENET_CCM_ADDR)
#define LAWAR_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawar)
#define LAWBARH_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarh)
#define LAWBARL_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarl)
#define LAWBAR_SHIFT 0
#else
#define LAW_BASE (CONFIG_SYS_IMMR + 0xc08)
#define LAWAR_ADDR(x) ((u32 *)LAW_BASE + 8 * x + 2)
#define LAWBAR_ADDR(x) ((u32 *)LAW_BASE + 8 * x)
#define LAWBAR_SHIFT 12
#endif
static inline phys_addr_t get_law_base_addr(int idx)
{
#ifdef CONFIG_FSL_CORENET
return (phys_addr_t)
((u64)in_be32(LAWBARH_ADDR(idx)) << 32) |
in_be32(LAWBARL_ADDR(idx));
#else
return (phys_addr_t)in_be32(LAWBAR_ADDR(idx)) << LAWBAR_SHIFT;
#endif
}
static inline void set_law_base_addr(int idx, phys_addr_t addr)
{
#ifdef CONFIG_FSL_CORENET
out_be32(LAWBARL_ADDR(idx), addr & 0xffffffff);
out_be32(LAWBARH_ADDR(idx), (u64)addr >> 32);
#else
out_be32(LAWBAR_ADDR(idx), addr >> LAWBAR_SHIFT);
#endif
}
void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
{
volatile ccsr_local_t *ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
gd->used_laws |= (1 << idx);
out_be32(&ccm->law[idx].lawar, 0);
out_be32(&ccm->law[idx].lawbarh, ((u64)addr >> 32));
out_be32(&ccm->law[idx].lawbarl, addr & 0xffffffff);
out_be32(&ccm->law[idx].lawar, LAW_EN | ((u32)id << 20) | (u32)sz);
out_be32(LAWAR_ADDR(idx), 0);
set_law_base_addr(idx, addr);
out_be32(LAWAR_ADDR(idx), LAW_EN | ((u32)id << 20) | (u32)sz);
/* Read back so that we sync the writes */
in_be32(&ccm->law[idx].lawar);
in_be32(LAWAR_ADDR(idx));
}
void disable_law(u8 idx)
{
volatile ccsr_local_t *ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
gd->used_laws &= ~(1 << idx);
out_be32(&ccm->law[idx].lawar, 0);
out_be32(&ccm->law[idx].lawbarh, 0);
out_be32(&ccm->law[idx].lawbarl, 0);
out_be32(LAWAR_ADDR(idx), 0);
set_law_base_addr(idx, 0);
/* Read back so that we sync the writes */
in_be32(&ccm->law[idx].lawar);
in_be32(LAWAR_ADDR(idx));
return;
}
@ -84,77 +112,20 @@ void disable_law(u8 idx)
#ifndef CONFIG_NAND_SPL
static int get_law_entry(u8 i, struct law_entry *e)
{
volatile ccsr_local_t *ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
u32 lawar;
lawar = in_be32(&ccm->law[i].lawar);
lawar = in_be32(LAWAR_ADDR(i));
if (!(lawar & LAW_EN))
return 0;
e->addr = ((u64)in_be32(&ccm->law[i].lawbarh) << 32) |
in_be32(&ccm->law[i].lawbarl);
e->addr = get_law_base_addr(i);
e->size = lawar & 0x3f;
e->trgt_id = (lawar >> 20) & 0xff;
return 1;
}
#endif
#else
void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
{
volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08);
volatile u32 *lawbar = base + 8 * idx;
volatile u32 *lawar = base + 8 * idx + 2;
gd->used_laws |= (1 << idx);
out_be32(lawar, 0);
out_be32(lawbar, addr >> 12);
out_be32(lawar, LAW_EN | ((u32)id << 20) | (u32)sz);
/* Read back so that we sync the writes */
in_be32(lawar);
}
void disable_law(u8 idx)
{
volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08);
volatile u32 *lawbar = base + 8 * idx;
volatile u32 *lawar = base + 8 * idx + 2;
gd->used_laws &= ~(1 << idx);
out_be32(lawar, 0);
out_be32(lawbar, 0);
/* Read back so that we sync the writes */
in_be32(lawar);
return;
}
#ifndef CONFIG_NAND_SPL
static int get_law_entry(u8 i, struct law_entry *e)
{
volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08);
volatile u32 *lawbar = base + 8 * i;
volatile u32 *lawar = base + 8 * i + 2;
u32 temp;
temp = in_be32(lawar);
if (!(temp & LAW_EN))
return 0;
e->addr = (u64)in_be32(lawbar) << 12;
e->size = temp & 0x3f;
e->trgt_id = (temp >> 20) & 0xff;
return 1;
}
#endif
#endif
int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
{
@ -216,17 +187,23 @@ struct law_entry find_law(phys_addr_t addr)
void print_laws(void)
{
volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08);
volatile u32 *lawbar = base;
volatile u32 *lawar = base + 2;
int i;
u32 lawar;
printf("\nLocal Access Window Configuration\n");
for(i = 0; i < FSL_HW_NUM_LAWS; i++) {
printf("\tLAWBAR%d : 0x%08x, LAWAR%d : 0x%08x\n",
i, in_be32(lawbar), i, in_be32(lawar));
lawbar += 8;
lawar += 8;
for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
lawar = in_be32(LAWAR_ADDR(i));
#ifdef CONFIG_FSL_CORENET
printf("LAWBARH%02d: 0x%08x LAWBARL%02d: 0x%08x",
i, in_be32(LAWBARH_ADDR(i)),
i, in_be32(LAWBARL_ADDR(i)));
#else
printf("LAWBAR%02d: 0x%08x", i, in_be32(LAWBAR_ADDR(i)));
#endif
printf(" LAWAR0x%02d: 0x%08x\n", i, lawar);
printf("\t(EN: %d TGT: 0x%02x SIZE: ",
(lawar & LAW_EN) ? 1 : 0, (lawar >> 20) & 0xff);
print_size(lawar_size(lawar), ")\n");
}
return;

18
drivers/mtd/nand/fsl_elbc_nand.c
View File

@ -75,7 +75,7 @@ struct fsl_elbc_ctrl {
struct fsl_elbc_mtd *chips[MAX_BANKS];
/* device info */
fsl_lbus_t *regs;
fsl_lbc_t *regs;
u8 __iomem *addr; /* Address of assigned FCM buffer */
unsigned int page; /* Last page written to / read from */
unsigned int read_bytes; /* Number of bytes read during command */
@ -171,7 +171,7 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
struct nand_chip *chip = mtd->priv;
struct fsl_elbc_mtd *priv = chip->priv;
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
fsl_lbus_t *lbc = ctrl->regs;
fsl_lbc_t *lbc = ctrl->regs;
int buf_num;
ctrl->page = page_addr;
@ -211,7 +211,7 @@ static int fsl_elbc_run_command(struct mtd_info *mtd)
struct nand_chip *chip = mtd->priv;
struct fsl_elbc_mtd *priv = chip->priv;
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
fsl_lbus_t *lbc = ctrl->regs;
fsl_lbc_t *lbc = ctrl->regs;
long long end_tick;
u32 ltesr;
@ -261,7 +261,7 @@ static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
{
struct fsl_elbc_mtd *priv = chip->priv;
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
fsl_lbus_t *lbc = ctrl->regs;
fsl_lbc_t *lbc = ctrl->regs;
if (priv->page_size) {
out_be32(&lbc->fir,
@ -295,7 +295,7 @@ static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
struct nand_chip *chip = mtd->priv;
struct fsl_elbc_mtd *priv = chip->priv;
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
fsl_lbus_t *lbc = ctrl->regs;
fsl_lbc_t *lbc = ctrl->regs;
ctrl->use_mdr = 0;
@ -633,7 +633,7 @@ static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
{
struct fsl_elbc_mtd *priv = chip->priv;
struct fsl_elbc_ctrl *ctrl = priv->ctrl;
fsl_lbus_t *lbc = ctrl->regs;
fsl_lbc_t *lbc = ctrl->regs;
if (ctrl->status != LTESR_CC)
return NAND_STATUS_FAIL;
@ -697,11 +697,7 @@ static void fsl_elbc_ctrl_init(void)
if (!elbc_ctrl)
return;
#ifdef CONFIG_MPC85xx
elbc_ctrl->regs = (void *)CONFIG_SYS_MPC85xx_LBC_ADDR;
#else
elbc_ctrl->regs = &((immap_t *)CONFIG_SYS_IMMR)->lbus;
#endif
elbc_ctrl->regs = LBC_BASE_ADDR;
/* clear event registers */
out_be32(&elbc_ctrl->regs->ltesr, LTESR_NAND_MASK);

1
include/configs/MPC8313ERDB.h
View File

@ -36,6 +36,7 @@
#define CONFIG_MPC8313ERDB 1
#define CONFIG_PCI
#define CONFIG_FSL_ELBC 1
#define CONFIG_MISC_INIT_R

1
include/configs/MPC8315ERDB.h
View File

@ -197,6 +197,7 @@
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
#define CONFIG_SYS_LBC_LBCR 0x00040000
#define CONFIG_FSL_ELBC 1
/*
* FLASH on the Local Bus

1
include/configs/MPC837XEMDS.h
View File

@ -223,6 +223,7 @@
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
#define CONFIG_SYS_LBC_LBCR 0x00000000
#define CONFIG_FSL_ELBC 1
/*
* FLASH on the Local Bus

1
include/configs/MPC837XERDB.h
View File

@ -246,6 +246,7 @@
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
#define CONFIG_SYS_LBC_LBCR 0x00000000
#define CONFIG_FSL_ELBC 1
/*
* FLASH on the Local Bus

15
include/configs/MPC8536DS.h
View File

@ -1,5 +1,5 @@
/*
* Copyright 2008-2009 Freescale Semiconductor, Inc.
* Copyright 2007-2009,2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -27,6 +27,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#include "../board/freescale/common/ics307_clk.h"
#ifdef CONFIG_MK_36BIT
#define CONFIG_PHYS_64BIT 1
#endif
@ -70,15 +72,9 @@
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#ifndef __ASSEMBLY__
extern unsigned long get_board_sys_clk(unsigned long dummy);
extern unsigned long get_board_ddr_clk(unsigned long dummy);
#endif
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0)
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
#define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq
from ICS307 instead of switches */
/*
* These can be toggled for performance analysis, otherwise use default.
@ -669,6 +665,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI

1
include/configs/MPC8540EVAL.h
View File

@ -294,6 +294,7 @@
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI

1
include/configs/MPC8541CDS.h
View File

@ -403,6 +403,7 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI

1
include/configs/MPC8544DS.h
View File

@ -420,6 +420,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI

1
include/configs/MPC8548CDS.h
View File

@ -462,6 +462,7 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI

1
include/configs/MPC8555CDS.h
View File

@ -401,6 +401,7 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI

1
include/configs/MPC8560ADS.h
View File

@ -416,6 +416,7 @@
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI

1
include/configs/MPC8568MDS.h
View File

@ -421,6 +421,7 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI

1
include/configs/MPC8569MDS.h
View File

@ -539,6 +539,7 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI

15
include/configs/MPC8572DS.h
View File

@ -1,5 +1,5 @@
/*
* Copyright 2007-2008 Freescale Semiconductor, Inc.
* Copyright 2007-2008,2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -27,6 +27,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#include "../board/freescale/common/ics307_clk.h"
#ifdef CONFIG_MK_36BIT
#define CONFIG_PHYS_64BIT
#endif
@ -53,15 +55,9 @@
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#ifndef __ASSEMBLY__
extern unsigned long get_board_sys_clk(unsigned long dummy);
extern unsigned long get_board_ddr_clk(unsigned long dummy);
#endif
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */
#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
#define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq
from ICS307 instead of switches */
/*
* These can be toggled for performance analysis, otherwise use default.
@ -574,6 +570,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI

470
include/configs/P1022DS.h Normal file
View File

@ -0,0 +1,470 @@
/*
* Copyright 2010 Freescale Semiconductor, Inc.
* Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
* Timur Tabi <timur@freescale.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include "../board/freescale/common/ics307_clk.h"
/* High Level Configuration Options */
#define CONFIG_BOOKE /* BOOKE */
#define CONFIG_E500 /* BOOKE e500 family */
#define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */
#define CONFIG_P1022
#define CONFIG_P1022DS
#define CONFIG_MP /* support multiple processors */
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
#define CONFIG_PCI /* Enable PCI/PCIE */
#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
#define CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_PHYS_64BIT
#define CONFIG_ENABLE_36BIT_PHYS
#define CONFIG_ADDR_MAP
#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_L2_CACHE
#define CONFIG_BTB
#define CONFIG_SYS_MEMTEST_START 0x00000000
#define CONFIG_SYS_MEMTEST_END 0x7fffffff
/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0x9000) /* pci0 */
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0xa000) /* pci1 */
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR + 0xb000) /* pci2 */
/* DDR Setup */
#define CONFIG_DDR_SPD
#define CONFIG_VERY_BIG_RAM
#define CONFIG_FSL_DDR3
#ifdef CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
/* I2C addresses of SPD EEPROMs */
#define CONFIG_SYS_SPD_BUS_NUM 1
#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
/*
* Memory map
*
* 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
* 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable
* 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
*
* Localbus cacheable (TBD)
* 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
*
* Localbus non-cacheable
* 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
* 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
* 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
* 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
* 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
*/
/*
* Local Bus Definitions
*/
#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
#define CONFIG_FLASH_BR_PRELIM \
(BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
#define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7)
#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
#define CONFIG_SYS_BR1_PRELIM \
(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM
#define CONFIG_SYS_FLASH_BANKS_LIST \
{CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
#define CONFIG_SYS_MAX_FLASH_BANKS 2
#define CONFIG_SYS_MAX_FLASH_SECT 1024
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_MISC_INIT_R
#define CONFIG_FSL_NGPIXIS
#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
#define PIXIS_BASE_PHYS 0xfffdf0000ull
#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7)
#define PIXIS_LBMAP_SWITCH 7
#define PIXIS_LBMAP_MASK 0xE0
#define PIXIS_LBMAP_ALTBANK 0x20
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET \
(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024)
/*
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_FSL_DIU_FB
#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
/* Video */
/* #define CONFIG_VIDEO */
#ifdef CONFIG_VIDEO
#define CONFIG_CFB_CONSOLE
#define CONFIG_VGA_AS_SINGLE_DEVICE
#endif
/*
* Pass open firmware flat tree
*/
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP
#define CONFIG_OF_STDOUT_VIA_ALIAS
/* new uImage format support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE
/* I2C */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_I2C_SPEED 400000
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}
#define CONFIG_SYS_I2C_OFFSET 0x3000
#define CONFIG_SYS_I2C2_OFFSET 0x3100
/*
* I2C2 EEPROM
*/
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_BUS_NUM 1
/*
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
/* controller 1, Slot 2, tgtid 1, Base address a000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
/* controller 2, direct to uli, tgtid 2, Base address 9000 */
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
/* controller 3, Slot 1, tgtid 3, Base address b000 */
#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
#ifdef CONFIG_PCI
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif
/* SATA */
#define CONFIG_LIBATA
#define CONFIG_FSL_SATA
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
#define CONFIG_SATA2
#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
#ifdef CONFIG_FSL_SATA
#define CONFIG_LBA48
#define CONFIG_CMD_SATA
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_EXT2
#endif
#define CONFIG_MMC
#ifdef CONFIG_MMC
#define CONFIG_CMD_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_GENERIC_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#endif
#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
#endif
#define CONFIG_TSEC_ENET
#ifdef CONFIG_TSEC_ENET
#define CONFIG_TSECV2
#define CONFIG_NET_MULTI
#define CONFIG_MII /* MII PHY management */
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "eTSEC1"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "eTSEC2"
#define TSEC1_PHY_ADDR 1
#define TSEC2_PHY_ADDR 2
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define CONFIG_ETHPRIME "eTSEC1"
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
#endif
/*
* Environment
*/
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OVERWRITE
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_LOADS_ECHO
#define CONFIG_SYS_LOADS_BAUD_CHANGE
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ELF
#define CONFIG_CMD_ERRATA
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_SETEXPR
#ifdef CONFIG_PCI
#define CONFIG_CMD_PCI
#define CONFIG_CMD_NET
#endif
/*
* USB
*/
#define CONFIG_USB_EHCI
#ifdef CONFIG_USB_EHCI
#define CONFIG_CMD_USB
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_EHCI_FSL
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_FAT
#endif
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#ifdef CONFIG_CMD_KGDB
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_HZ 1000
/*
* For booting Linux, the board info and command line data
* have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#ifdef CONFIG_CMD_KGDB
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/*
* Environment Configuration
*/
#define CONFIG_HOSTNAME p1022ds
#define CONFIG_ROOTPATH /opt/nfsroot
#define CONFIG_BOOTFILE uImage
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
#define CONFIG_LOADADDR 1000000
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
#define CONFIG_BOOTARGS
#define CONFIG_BAUDRATE 115200
#define CONFIG_EXTRA_ENV_SETTINGS \
"perf_mode=stable\0" \
"memctl_intlv_ctl=2\0" \
"netdev=eth0\0" \
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
"protect off " MK_STR(TEXT_BASE) " +$filesize; " \
"erase " MK_STR(TEXT_BASE) " +$filesize; " \
"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
"protect on " MK_STR(TEXT_BASE) " +$filesize; " \
"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=uramdisk\0" \
"fdtaddr=c00000\0" \
"fdtfile=p1022ds.dtb\0" \
"bdev=sda3\0" \
"diuregs=md e002c000 1d\0" \
"dium=mw e002c01c\0" \
"diuerr=md e002c014 1\0" \
"othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0 tty0\0" \
"monitor=0-DVI\0"
#define CONFIG_HDBOOT \
"setenv bootargs root=/dev/$bdev rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
#endif

4
include/configs/P1_P2_RDB.h
View File

@ -74,6 +74,7 @@
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_E1000 1 /* E1000 pci Ethernet card*/
#ifndef __ASSEMBLY__
extern unsigned long get_board_sys_clk(unsigned long dummy);
#endif
@ -84,6 +85,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_MP
#endif
#define CONFIG_HWCONFIG
/*
* These can be toggled for performance analysis, otherwise use default.
*/
@ -475,6 +478,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define CONFIG_CMD_NET

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