ColdFire: MCF5329 Update and cleanup
Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
This commit is contained in:
TsiChungLiew
John Rigby
parent
81735b2568
commit
ab77bc547b
2
Makefile
2
Makefile
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@ -1682,7 +1682,7 @@ M5329BFEE_config : unconfig
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esac; \
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>include/config.h ; \
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if [ "$${NAND}" != "0" ] ; then \
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echo "#define NANDFLASH_SIZE $${NAND}" >> include/config.h ; \
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echo "#define NANDFLASH_SIZE $${NAND}" > $(obj)include/config.h ; \
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fi
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@$(MKCONFIG) -a M5329EVB m68k mcf532x m5329evb freescale
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@ -30,7 +30,7 @@
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DECLARE_GLOBAL_DATA_PTR;
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#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI)
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#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
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#undef MII_DEBUG
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#undef ET_DEBUG
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@ -50,7 +50,7 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
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return 0;
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}
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#if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII)
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#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
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#include <miiphy.h>
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/* Make MII read/write commands for the FEC. */
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@ -134,7 +134,7 @@ uint mii_send(uint mii_cmd)
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return (mii_reply & 0xffff); /* data read from phy */
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}
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#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */
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#endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
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#if defined(CFG_DISCOVER_PHY)
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int mii_discover_phy(struct eth_device *dev)
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@ -303,4 +303,4 @@ int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg,
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return 0;
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}
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#endif /* CFG_CMD_NET, FEC_ENET & NET_MULTI */
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#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
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@ -31,7 +31,7 @@
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DECLARE_GLOBAL_DATA_PTR;
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#if (CONFIG_COMMANDS & CFG_CMD_NAND)
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#if defined(CONFIG_CMD_NAND)
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#include <nand.h>
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#include <linux/mtd/mtd.h>
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@ -225,7 +225,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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#if defined(CFG_MBAR)
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print_num ("mbar", bd->bi_mbar_base );
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#endif
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#if defined(CFG_CMD_NET)
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#if defined(CONFIG_CMD_NET)
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puts ("ethaddr =");
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for (i=0; i<6; ++i) {
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printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
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@ -239,22 +239,22 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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#endif
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#if defined(CONFIG_HAS_ETH2)
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puts ("\neth2addr =");
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for (i=0; i<6; ++i) {
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puts ("\neth2addr =");
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for (i=0; i<6; ++i) {
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printf ("%c%02X", i ? ':' : ' ', bd->bi_enet2addr[i]);
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}
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#endif
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#if defined(CONFIG_HAS_ETH3)
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puts ("\neth3addr =");
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for (i=0; i<6; ++i) {
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puts ("\neth3addr =");
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for (i=0; i<6; ++i) {
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printf ("%c%02X", i ? ':' : ' ', bd->bi_enet3addr[i]);
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}
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#endif
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puts ("\nip_addr = ");
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print_IPaddr (bd->bi_ip_addr);
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#endif /* CFG_CMD_NET */
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#endif /* CONFIG_CMD_NET */
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printf ("\nbaudrate = %d bps\n", bd->bi_baudrate);
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return 0;
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@ -51,7 +51,7 @@
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DECLARE_GLOBAL_DATA_PTR;
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#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI)
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#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
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struct fec_info_s fec_info[] = {
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#ifdef CFG_FEC0_IOBASE
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@ -410,7 +410,7 @@ int fec_init(struct eth_device *dev, bd_t * bd)
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fec_reset(dev);
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#if (CONFIG_COMMANDS & CFG_CMD_MII) || defined (CONFIG_MII) || \
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#if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
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defined (CFG_DISCOVER_PHY)
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mii_init();
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@ -420,7 +420,7 @@ int fec_init(struct eth_device *dev, bd_t * bd)
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#ifndef CFG_DISCOVER_PHY
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setFecDuplexSpeed(fecp, bd, (FECDUPLEX << 16) | FECSPEED);
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#endif /* ifndef CFG_DISCOVER_PHY */
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#endif /* CFG_CMD_MII || CONFIG_MII */
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#endif /* CONFIG_CMD_MII || CONFIG_MII */
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/* We use strictly polling mode only */
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fecp->eimr = 0;
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@ -568,7 +568,7 @@ int mcffec_initialize(bd_t * bis)
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eth_register(dev);
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#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
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#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
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miiphy_register(dev->name,
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mcffec_miiphy_read, mcffec_miiphy_write);
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#endif
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@ -580,5 +580,5 @@ int mcffec_initialize(bd_t * bis)
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return 1;
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}
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#endif /* CFG_CMD_NET, FEC_ENET & NET_MULTI */
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#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
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#endif /* CONFIG_MCFFEC */
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@ -38,8 +38,10 @@
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#ifdef CONFIG_MCFTMR
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#define CFG_UDELAY_BASE (MMAP_DTMR0)
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#define CFG_TMR_BASE (MMAP_DTMR1)
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#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
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#define CFG_TMRINTR_NO (INT0_HI_DTMR1)
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#define CFG_TMRINTR_MASK (INTC_IPRH_INT33)
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#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
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#define CFG_TMRINTR_PRI (6)
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#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
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#endif
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@ -28,18 +28,18 @@
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#include <asm/byteorder.h>
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#define readb(addr) in_8((volatile u8 *)(addr))
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#define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
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#define readb(addr) in_8((volatile u8 *)(addr))
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#define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
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#if !defined(__BIG_ENDIAN)
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#define readw(addr) (*(volatile u16 *) (addr))
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#define readl(addr) (*(volatile u32 *) (addr))
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#define writew(b,addr) ((*(volatile u16 *) (addr)) = (b))
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#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
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#define readw(addr) (*(volatile u16 *) (addr))
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#define readl(addr) (*(volatile u32 *) (addr))
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#define writew(b,addr) ((*(volatile u16 *) (addr)) = (b))
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#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
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#else
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#define readw(addr) in_le16((volatile u16 *)(addr))
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#define readl(addr) in_le32((volatile u32 *)(addr))
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#define writew(b,addr) out_le16((volatile u16 *)(addr),(b))
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#define writel(b,addr) out_le32((volatile u32 *)(addr),(b))
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#define readw(addr) in_le16((volatile u16 *)(addr))
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#define readl(addr) in_le32((volatile u32 *)(addr))
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#define writew(b,addr) out_le16((volatile u16 *)(addr),(b))
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#define writel(b,addr) out_le32((volatile u32 *)(addr),(b))
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#endif
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/*
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@ -48,25 +48,25 @@
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* are arrays of bytes, and byte-swapping is not appropriate in
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* that case. - paulus
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*/
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#define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns))
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#define outsb(port, buf, ns) _outsb((u8 *)((port)+_IO_BASE), (buf), (ns))
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#define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
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#define outsw(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
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#define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
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#define outsl(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
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#define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns))
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#define outsb(port, buf, ns) _outsb((u8 *)((port)+_IO_BASE), (buf), (ns))
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#define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
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#define outsw(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
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#define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
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#define outsl(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
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#define inb(port) in_8((u8 *)((port)+_IO_BASE))
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#define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val))
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#define inb(port) in_8((u8 *)((port)+_IO_BASE))
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#define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val))
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#if !defined(__BIG_ENDIAN)
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#define inw(port) in_be16((u16 *)((port)+_IO_BASE))
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#define outw(val, port) out_be16((u16 *)((port)+_IO_BASE), (val))
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#define inl(port) in_be32((u32 *)((port)+_IO_BASE))
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#define outl(val, port) out_be32((u32 *)((port)+_IO_BASE), (val))
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#define inw(port) in_be16((u16 *)((port)+_IO_BASE))
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#define outw(val, port) out_be16((u16 *)((port)+_IO_BASE), (val))
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#define inl(port) in_be32((u32 *)((port)+_IO_BASE))
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#define outl(val, port) out_be32((u32 *)((port)+_IO_BASE), (val))
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#else
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#define inw(port) in_le16((u16 *)((port)+_IO_BASE))
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#define outw(val, port) out_le16((u16 *)((port)+_IO_BASE), (val))
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#define inl(port) in_le32((u32 *)((port)+_IO_BASE))
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#define outl(val, port) out_le32((u32 *)((port)+_IO_BASE), (val))
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#define inw(port) in_le16((u16 *)((port)+_IO_BASE))
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#define outw(val, port) out_le16((u16 *)((port)+_IO_BASE), (val))
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#define inl(port) in_le32((u32 *)((port)+_IO_BASE))
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#define outl(val, port) out_le32((u32 *)((port)+_IO_BASE), (val))
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#endif
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extern inline void _insb(volatile u8 * port, void *buf, int ns)
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@ -151,10 +151,10 @@ extern inline void _outsl_ns(volatile u32 * port, const void *buf, int nl)
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* Neither do the standard versions now, these are just here
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* for older code.
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*/
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#define insw_ns(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
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#define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
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#define insl_ns(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
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#define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
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#define insw_ns(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
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#define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
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#define insl_ns(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
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#define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
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#define IO_SPACE_LIMIT ~0
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@ -33,12 +33,26 @@
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/****************************************************************************/
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/* DMA Timer module registers */
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typedef struct dtimer_ctrl {
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#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
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u16 tmr; /* 0x00 Mode register */
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u16 res1; /* 0x02 */
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u16 trr; /* 0x04 Reference register */
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u16 res2; /* 0x06 */
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u16 tcr; /* 0x08 Capture register */
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u16 res3; /* 0x0A */
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u16 tcn; /* 0x0C Counter register */
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u16 res4; /* 0x0E */
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u8 res6; /* 0x10 */
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u8 ter; /* 0x11 Event register */
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u16 res7; /* 0x12 */
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#else
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u16 tmr; /* 0x00 Mode register */
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u8 txmr; /* 0x02 Extended Mode register */
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u8 ter; /* 0x03 Event register */
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u32 trr; /* 0x04 Reference register */
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u32 tcr; /* 0x08 Capture register */
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u32 tcn; /* 0x0C Counter register */
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#endif
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} dtmr_t;
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/*Programmable Interrupt Timer */
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@ -47,25 +47,23 @@
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#undef CONFIG_WATCHDOG
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#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
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#define DEFAULT_COMMANDS ( CONFIG_CMD_DFL | \
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CFG_CMD_CACHE | \
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CFG_CMD_DATE | \
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CFG_CMD_ELF | \
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CFG_CMD_FLASH | \
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CFG_CMD_I2C | \
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(CFG_CMD_LOADB | CFG_CMD_LOADS) | \
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CFG_CMD_MEMORY | \
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CFG_CMD_MISC | \
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CFG_CMD_MII | \
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CFG_CMD_NET | \
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CFG_CMD_PING | \
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CFG_CMD_REGINFO \
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)
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/* Command line configuration */
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#include <config_cmd_default.h>
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_FLASH
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_MEMORY
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#define CONFIG_CMD_MISC
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_REGINFO
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#ifdef NANDFLASH_SIZE
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# define CONFIG_COMMANDS (DEFAULT_COMMANDS | CFG_CMD_NAND)
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#else
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# define CONFIG_COMMANDS (DEFAULT_COMMANDS)
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# define CONFIG_CMD_NAND
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#endif
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#define CFG_UNIFY_CACHE
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@ -108,9 +106,9 @@
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#define CFG_I2C_OFFSET 0x58000
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#define CFG_IMMR CFG_MBAR
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
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#define CONFIG_UDP_CHECKSUM
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#ifdef CONFIG_MCFFEC
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# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
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# define CONFIG_IPADDR 192.162.1.2
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@ -137,7 +135,7 @@
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#define CFG_PROMPT "-> "
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#define CFG_LONGHELP /* undef to save memory */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#ifdef CONFIG_CMD_KGDB
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# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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@ -154,7 +152,7 @@
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#define CFG_MBAR 0xFC000000
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#define CFG_LATCH_ADDR (CFG_CS1_BASE + 0x80000)
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#define CFG_LATCH_ADDR (CFG_CS1_BASE + 0x80000)
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/*
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* Low Level Configuration Settings
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@ -168,7 +166,7 @@
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#define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
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#define CFG_INIT_RAM_CTRL 0x221
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 0x10)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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@ -198,7 +196,7 @@
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization ??
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
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/*-----------------------------------------------------------------------
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* FLASH organization
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@ -214,20 +212,19 @@
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#endif
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#ifdef NANDFLASH_SIZE
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# define CFG_MAX_NAND_DEVICE 1
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# define CFG_NAND_BASE (CFG_CS2_BASE << 16)
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# define CFG_NAND_SIZE 1
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# define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
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# define NAND_MAX_CHIPS 1
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# define NAND_ALLOW_ERASE_ALL 1
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# define CONFIG_JFFS2_NAND 1
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# define CONFIG_JFFS2_DEV "nand0"
|
||||
# define CONFIG_JFFS2_PART_SIZE (CFG_CS2_MASK & ~1)
|
||||
# define CONFIG_JFFS2_PART_OFFSET 0x00000000
|
||||
# define CFG_MAX_NAND_DEVICE 1
|
||||
# define CFG_NAND_BASE (CFG_CS2_BASE << 16)
|
||||
# define CFG_NAND_SIZE 1
|
||||
# define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
|
||||
# define NAND_MAX_CHIPS 1
|
||||
# define NAND_ALLOW_ERASE_ALL 1
|
||||
# define CONFIG_JFFS2_NAND 1
|
||||
# define CONFIG_JFFS2_DEV "nand0"
|
||||
# define CONFIG_JFFS2_PART_SIZE (CFG_CS2_MASK & ~1)
|
||||
# define CONFIG_JFFS2_PART_OFFSET 0x00000000
|
||||
#endif
|
||||
|
||||
#define CFG_FLASH_BASE 0
|
||||
#define CFG_FLASH0_BASE (CFG_CS0_BASE << 16)
|
||||
#define CFG_FLASH_BASE (CFG_CS0_BASE << 16)
|
||||
|
||||
/* Configuration for environment
|
||||
* Environment is embedded in u-boot in the second sector of the flash
|
||||
|
|
@ -267,6 +264,4 @@
|
|||
#define CFG_CS2_CTRL 0x00001f60
|
||||
#endif
|
||||
|
||||
#define CONFIG_UDP_CHECKSUM
|
||||
|
||||
#endif /* _M5329EVB_H */
|
||||
|
|
|
|||
|
|
@ -692,7 +692,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
|
|||
#endif
|
||||
#if defined(CONFIG_NET_MULTI)
|
||||
puts ("Net: ");
|
||||
eth_initialize (bd);
|
||||
eth_initialize (bd);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -347,10 +347,9 @@ void udelay(unsigned long usec)
|
|||
void dtimer_interrupt(void *not_used)
|
||||
{
|
||||
volatile dtmr_t *timerp = (dtmr_t *) (CFG_TMR_BASE);
|
||||
volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
|
||||
|
||||
/* check for timer interrupt asserted */
|
||||
if ((intp->iprh0 & CFG_TMRINTR_MASK) == CFG_TMRINTR_MASK) {
|
||||
if ((CFG_TMRPND_REG & CFG_TMRINTR_MASK) == CFG_TMRINTR_PEND) {
|
||||
timerp->ter = (DTIM_DTER_CAP | DTIM_DTER_REF);
|
||||
timestamp++;
|
||||
return;
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@
|
|||
#include <asm/immap.h>
|
||||
#include <asm/rtc.h>
|
||||
|
||||
#if defined(CONFIG_MCFRTC) && (CONFIG_COMMANDS & CFG_CMD_DATE)
|
||||
#if defined(CONFIG_MCFRTC) && defined(CONFIG_CMD_DATE)
|
||||
|
||||
#undef RTC_DEBUG
|
||||
|
||||
|
|
@ -118,4 +118,4 @@ void rtc_reset(void)
|
|||
rtc->cr |= RTC_CR_SWR;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_MCFRTC && CFG_CMD_DATE */
|
||||
#endif /* CONFIG_MCFRTC && CONFIG_CMD_DATE */
|
||||
|
|
|
|||
Loading…
Reference in New Issue