sciphone_g2: Support for NAND with HW ECC
Implementation of MT62xx NAND controller (NFI) which supports large page devices and small page devices. It also enables hardware ECC control. Signed-off-by: Marcin Mielczarczyk <marcin.mielczarczyk@tieto.com>
This commit is contained in:
Marcin Mielczarczyk
parent
254b41cd0c
commit
a025f73fd7
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@ -38,6 +38,62 @@
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#define MTK_NFI_PSTA (MTK_NFI_BASE + 0x40)
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#define MTK_NFI_FIFOSTA (MTK_NFI_BASE + 0x44)
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#define MTK_NFI_CON (MTK_NFI_BASE + 0x60)
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#define MTK_NFI_INTR_EN (MTK_NFI_BASE + 0x68)
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#define MTK_NFI_PAGECNTR (MTK_NFI_BASE + 0x70)
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#define MTK_NFI_ADDRCNTR (MTK_NFI_BASE + 0x74)
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#define MTK_NFI_SYM0_ADDR (MTK_NFI_BASE + 0x80)
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#define MTK_NFI_SYM1_ADDR (MTK_NFI_BASE + 0x84)
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#define MTK_NFI_SYM2_ADDR (MTK_NFI_BASE + 0x88)
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#define MTK_NFI_SYM3_ADDR (MTK_NFI_BASE + 0x8C)
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#define MTK_NFI_SYM4_ADDR (MTK_NFI_BASE + 0x90)
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#define MTK_NFI_SYM5_ADDR (MTK_NFI_BASE + 0x94)
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#define MTK_NFI_SYM6_ADDR (MTK_NFI_BASE + 0x98)
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#define MTK_NFI_SYM7_ADDR (MTK_NFI_BASE + 0x9C)
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#define MTK_NFI_SYMS0_ADDR (MTK_NFI_BASE + 0xA0)
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#define MTK_NFI_SYMS1_ADDR (MTK_NFI_BASE + 0xA4)
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#define MTK_NFI_SYMS2_ADDR (MTK_NFI_BASE + 0xA8)
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#define MTK_NFI_SYMS3_ADDR (MTK_NFI_BASE + 0xAC)
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#define MTK_NFI_SYM0_DATA (MTK_NFI_BASE + 0xB0)
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#define MTK_NFI_SYM1_DATA (MTK_NFI_BASE + 0xB4)
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#define MTK_NFI_SYM2_DATA (MTK_NFI_BASE + 0xB8)
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#define MTK_NFI_SYM3_DATA (MTK_NFI_BASE + 0xBC)
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#define MTK_NFI_SYM4_DATA (MTK_NFI_BASE + 0xC0)
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#define MTK_NFI_SYM5_DATA (MTK_NFI_BASE + 0xC4)
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#define MTK_NFI_SYM6_DATA (MTK_NFI_BASE + 0xC8)
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#define MTK_NFI_SYM7_DATA (MTK_NFI_BASE + 0xCC)
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#define MTK_NFI_SYMS0_DATA (MTK_NFI_BASE + 0xD0)
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#define MTK_NFI_SYMS1_DATA (MTK_NFI_BASE + 0xD4)
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#define MTK_NFI_SYMS2_DATA (MTK_NFI_BASE + 0xD8)
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#define MTK_NFI_SYMS3_DATA (MTK_NFI_BASE + 0xDC)
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#define MTK_NFI_PAR_0P (MTK_NFI_BASE + 0xE0)
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#define MTK_NFI_PAR_0C (MTK_NFI_BASE + 0xE4)
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#define MTK_NFI_PAR_1P (MTK_NFI_BASE + 0xE8)
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#define MTK_NFI_PAR_1C (MTK_NFI_BASE + 0xEC)
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#define MTK_NFI_PAR_2P (MTK_NFI_BASE + 0xF0)
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#define MTK_NFI_PAR_2C (MTK_NFI_BASE + 0xF4)
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#define MTK_NFI_PAR_3P (MTK_NFI_BASE + 0xF8)
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#define MTK_NFI_PAR_3C (MTK_NFI_BASE + 0xFC)
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#define MTK_NFI_PAR_4P (MTK_NFI_BASE + 0x100)
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#define MTK_NFI_PAR_4C (MTK_NFI_BASE + 0x104)
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#define MTK_NFI_PAR_5P (MTK_NFI_BASE + 0x108)
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#define MTK_NFI_PAR_5C (MTK_NFI_BASE + 0x10C)
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#define MTK_NFI_PAR_6P (MTK_NFI_BASE + 0x110)
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#define MTK_NFI_PAR_6C (MTK_NFI_BASE + 0x114)
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#define MTK_NFI_PAR_7P (MTK_NFI_BASE + 0x118)
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#define MTK_NFI_PAR_7C (MTK_NFI_BASE + 0x11C)
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#define MTK_NFI_PARS_0P (MTK_NFI_BASE + 0x120)
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#define MTK_NFI_PARS_0C (MTK_NFI_BASE + 0x124)
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#define MTK_NFI_PARS_1P (MTK_NFI_BASE + 0x128)
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#define MTK_NFI_PARS_1C (MTK_NFI_BASE + 0x12C)
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#define MTK_NFI_PARS_2P (MTK_NFI_BASE + 0x130)
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#define MTK_NFI_PARS_2C (MTK_NFI_BASE + 0x134)
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#define MTK_NFI_PARS_3P (MTK_NFI_BASE + 0x138)
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#define MTK_NFI_PARS_3C (MTK_NFI_BASE + 0x13C)
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#define MTK_NFI_ERRDET (MTK_NFI_BASE + 0x140)
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#define MTK_NFI_PARERR (MTK_NFI_BASE + 0x144)
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#define MTK_NFI_SCON (MTK_NFI_BASE + 0x148)
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#define MTK_NFI_CSEL (MTK_NFI_BASE + 0x200)
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#define MTK_NFI_IOCON (MTK_NFI_BASE + 0x204)
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/* NFI_ACCCON bit fields definitions */
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#define NFI_ACCCON_RLT_SHIFT (0)
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@ -84,8 +140,8 @@
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/* NFI_CON bit fields definitions */
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#define NFI_CON_DMA_RD_EN (1 << 0)
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#define NFI_CON_DMA_WR_EN (1 << 1)
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#define NFI_CON_AUTO_ECC_DEC_EN (1 << 2)
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#define NFI_CON_AUTO_ECC_ENC_EN (1 << 3)
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#define NFI_CON_AUTOECC_DEC_EN (1 << 2)
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#define NFI_CON_AUTOECC_ENC_EN (1 << 3)
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#define NFI_CON_MULTI_PAGE_RD_EN (1 << 4)
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#define NFI_CON_SPARE_EN (1 << 5)
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#define NFI_CON_DMA_PAUSE_EN (1 << 6)
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@ -25,57 +25,339 @@
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#include <asm/io.h>
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#include <asm/arch-mtk/nfi.h>
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#include <asm/arch-mtk/system.h>
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#include <linux/err.h>
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static void mtk_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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{
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struct nand_chip *chip = mtd->priv;
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static int addr_bit = 0;
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static int address = 0;
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static int command = 0;
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if (ctrl == (NAND_CTRL_CHANGE | NAND_NCE)) {
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chip->IO_ADDR_R = (void *)MTK_NFI_DATARB;
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if (addr_bit) {
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/*
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while(!((readw(MTK_NFI_FIFOSTA) & 0xFF) == NFI_FIFOSTA_RD_EMPTY))
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readb(MTK_NFI_DATARB);*/
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writel(address, MTK_NFI_ADDRL);
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if (command == NAND_CMD_READID ||
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command == NAND_CMD_STATUS) {
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writeb(1, MTK_NFI_ADDRNOB);
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while(readl(MTK_NFI_PSTA) & NFI_PSTA_ADDR)
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;
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writel(NFI_OPCON_SRD, MTK_NFI_OPCON);
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} else {
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writeb(addr_bit >> 3, MTK_NFI_ADDRNOB);
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while(readl(MTK_NFI_PSTA) & NFI_PSTA_ADDR)
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;
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writel(NFI_OPCON_BRD, MTK_NFI_OPCON);
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}
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addr_bit = 0;
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}
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} else if ((ctrl & NAND_CLE) && (cmd != NAND_CMD_NONE)) {
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command = cmd;
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writel(cmd, MTK_NFI_CMD);
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while(readl(MTK_NFI_PSTA) & NFI_PSTA_CMD)
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;
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} else if (ctrl & NAND_ALE) {
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if (!addr_bit)
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address = cmd;
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else
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address |= cmd << addr_bit;
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* MT62XX NAND controller (NFI) can suppport small page (512B) and
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* large page (2048B) NAND devices. It also supports hardware ECC control.
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* ECC is calculated by hardware for given block of bytes (128, 256, 512, 1024).
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* NFI controller can acutomatically detect if read page has no errors -
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* comparing calculated ECC with ECC bytes written in spare area.
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* Problem with hardware ECC is that ECC calculation is available after
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* addtional cycle of read/write (after reading of whole page).
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* I.e. page size is 512, so after reading whole page addtional read/write cycle
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* has to be issued to get ECC calculation (NFI_ADDRCNTR has to show more than
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* 512).
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*
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* In case of reading it's not a problem as NFI controller has 16 bytes FIFO and
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* in burst mode it'll issue 16 reads in advance, so after reading whole page
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* from FIFO, ECC calculation will be already available (as 16 addtional bytes
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* are already placed in FIFO). To have ECC calculations working, SPARE_EN bit
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* has to be enabled, otherwise there will be no additional read cycle. In this
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* case AUTO_ECC_DEC_EN mode works (automatic ECC errors detection).
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*
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* Problem is with writing mode, as additional byte has to be written to spare
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* area and only after that ECC calculation will be available. It means that
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* when using HW ECC it's not possible to place calculation at first byte of
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* spare area. There is AUTO_ECC_ENC_EN mode which doesn't seem to work.
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* In this mode NFI controller should automatically write calculated ECC bytes
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* in spare area. To have it working SPARE_EN bit should be disabled, which
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* indicates that NFI controller has control over spare area, not the user.
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* Unfortunatelly even after disabling SPARE_EN bit, NFI controller doesn't
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* write ECC calculations in spare automatically.
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* Because of these NFI controller issues, driver has to have some hacks.
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*
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* Sciphone G2 specific informations:
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*
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* Sciphone G2 comes with small page and large page NAND devices.
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* For both configurations ecc block size is the same:
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*
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* ecc_block_size = 256
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*
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* Placement of ecc bytes in spare area is as follows:
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*
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* --------------------------------------------------------------
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* | SPARE |
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* --------------------------------------------------------------
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* | | ECC0 | | ECC1 | | ECC2 | | ECC3 |
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* --------------------------------------------------------------
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* 0 8 16 24 32 40 48 56 64
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*
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* ECC0 = 12 bits (from 1st ECC block) + 12 bits (from 2nd ECC block)
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* ECC1 = 12 bits (from 3rd ECC block) + 12 bits (from 4th ECC block)
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* ECC2 = 12 bits (from 5th ECC block) + 12 bits (from 6th ECC block)
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* ECC2 = 12 bits (from 7th ECC block) + 12 bits (from 8th ECC block)
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*
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* This information is pretty important as built-in bootloader in MT62xx chips
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* has hardware ECC enabled and it won't load code from NAND if ECC layout will
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* not match.
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*/
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addr_bit += 8;
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/* MT62XX NFI controller has 2 chipselects */
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#define NAND_CHIPS_MAX 2
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/*
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* Configure which byte in spare area will store ECC calculations.
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* This value should be dword (4 bytes) aligned.
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*/
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#define ECC_SPARE_BYTE_POS 8
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static void nand_ctrl_change(int cmd, int address, int *addr_cycle,
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int write_size)
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{
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int burst_read = 0;
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if (write_size > 512) {
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/* Large page device - set burst read on READSTART command */
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if (cmd == NAND_CMD_READSTART)
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burst_read = 1;
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} else {
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/* Small page device - set burst read on all read commands */
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if ((cmd == NAND_CMD_READ0) |
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(cmd == NAND_CMD_READ1) |
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(cmd == NAND_CMD_READOOB))
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burst_read = 1;
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}
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/* Any address to write? */
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if (*addr_cycle) {
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writel(address, MTK_NFI_ADDRL);
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if (cmd == NAND_CMD_READID) {
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/* For READID command just one address byte is used */
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writel(1, MTK_NFI_ADDRNOB);
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while(readl(MTK_NFI_PSTA) & NFI_PSTA_ADDR)
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;
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/* Set single read mode */
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writel(NFI_OPCON_SRD, MTK_NFI_OPCON);
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while(readl(MTK_NFI_PSTA) & NFI_PSTA_DATAR)
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;
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} else {
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/* Write calculated number of address bytes */
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writel(*addr_cycle, MTK_NFI_ADDRNOB);
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while(readl(MTK_NFI_PSTA) & NFI_PSTA_ADDR)
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;
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}
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*addr_cycle = 0;
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}
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if (burst_read) {
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/* Set burst read mode */
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writel(NFI_OPCON_BRD, MTK_NFI_OPCON);
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while(readl(MTK_NFI_PSTA) & NFI_PSTA_DATAR)
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;
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} else if (cmd == NAND_CMD_STATUS) {
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/* Set single read mode */
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writel(NFI_OPCON_SRD, MTK_NFI_OPCON);
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while(readl(MTK_NFI_PSTA) & NFI_PSTA_DATAR)
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;
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}
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}
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static int mtk_dev_ready(struct mtd_info *mtd)
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static void nand_write_command(int cmd)
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{
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/*
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* Clear BRD and SRD bits before issuing command,
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* otherwise there can be some zeroes at the beggining of read.
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*/
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writew(readl(MTK_NFI_OPCON) & ~(NFI_OPCON_BRD | NFI_OPCON_SRD),
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MTK_NFI_OPCON);
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writel(cmd, MTK_NFI_CMD);
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while(readl(MTK_NFI_PSTA) & NFI_PSTA_CMD)
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;
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}
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static void mt62xx_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
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unsigned int ctrl)
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{
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static int addr_cycle = 0;
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static int address = 0;
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static int command = 0;
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if (ctrl == (NAND_CTRL_CHANGE | NAND_NCE))
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nand_ctrl_change(command, address, &addr_cycle, mtd->writesize);
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else if ((ctrl & NAND_CLE) && (cmd != NAND_CMD_NONE)) {
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command = cmd;
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nand_write_command(cmd);
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} else if (ctrl & NAND_ALE) {
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/*
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* Calculate address and address bytes which will be written
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* in nand_ctrl_change() function.
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*/
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if (!addr_cycle)
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address = cmd;
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else
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address |= cmd << (addr_cycle*8);
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addr_cycle++;
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}
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}
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static int mt62xx_nand_dev_ready(struct mtd_info *mtd)
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{
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return !(readl(MTK_NFI_PSTA) & NFI_PSTA_NAND_BUSY);
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}
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int board_nand_init(struct nand_chip *nand)
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static void mt62xx_nand_select_chip(struct mtd_info *mtd, int chip)
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{
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if (chip > NAND_CHIPS_MAX) {
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printk(KERN_ERR "Wrong NAND chip number!\n");
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return;
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}
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writel(chip, MTK_NFI_CSEL);
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}
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static void mt62xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
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{
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uint32_t *buf_32 = (uint32_t *)buf;
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struct nand_chip *chip = mtd->priv;
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int i;
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if (len % 4)
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printk(KERN_ERR "Length parameter is not aligned\n");
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for (i = 0; i < len/4; ++i)
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buf_32[i] = readl(chip->IO_ADDR_R);
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}
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static uint8_t mt62xx_nand_read_byte(struct mtd_info *mtd)
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{
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struct nand_chip *chip = mtd->priv;
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uint16_t nfi_con = readl(MTK_NFI_CON);
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uint8_t byte;
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/* Enable byte mode reading */
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writel(nfi_con | NFI_CON_BYTE_RW, MTK_NFI_CON);
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byte = readb(chip->IO_ADDR_R);
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/* Disable byte mode reading */
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writel(nfi_con & ~NFI_CON_BYTE_RW, MTK_NFI_CON);
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return byte;
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}
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static void mt62xx_nand_write_ecc(struct mtd_info *mtd, int len)
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{
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int i, ecc_nr, ecc_blocks;
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struct nand_chip *chip = mtd->priv;
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uint8_t ecc[8];
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/*
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* Two ECC blocks are combined in Sciphone G2 format,
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* that's why there is division by 2.
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*/
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ecc_blocks = mtd->writesize/chip->ecc.size/2;
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for (ecc_nr = 0; ecc_nr < ecc_blocks; ++ecc_nr) {
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int ecc_p, ecc_c, pos = 0;
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/*
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* After first write in this loop, ECC calculations will
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* be available in NFI_PAR_P and NFI_PAR_C registers.
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*/
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for (i = 0; i < ECC_SPARE_BYTE_POS/4; ++i)
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writel(~0, chip->IO_ADDR_W);
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/*
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* Read calculated ECC bytes and write them
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* to buffer in proper format (as Sciphone G2 expects).
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*/
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for (i = 0; i < 2; ++i) {
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ecc_p = readw((uint32_t *)MTK_NFI_PAR_0P + ecc_nr*2 + i*2);
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ecc_c = readw((uint32_t *)MTK_NFI_PAR_0C + ecc_nr*2 + i*2);
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ecc[pos++] = ecc_p >> 4;
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ecc[pos++] = ((ecc_p & 0x0F) << 4) | (ecc_c >> 8);
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ecc[pos++] = ecc_c & 0xFF;
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}
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/* Fill rest of buffer with 0xFF */
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while (pos < sizeof(ecc))
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ecc[pos++] = 0xFF;
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/* Write calculated ECC bytes */
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for (i = 0; i < sizeof(ecc)/4; ++i)
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writel(((uint32_t *)ecc)[i], chip->IO_ADDR_W);
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}
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}
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static void mt62xx_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
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int len)
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{
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uint32_t *buf_32 = (uint32_t *)buf;
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struct nand_chip *chip = mtd->priv;
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int i;
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/* Writing in spare area? */
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if (readw(MTK_NFI_ADDRCNTR) >= mtd->writesize) {
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/*
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* Due to issue that ECC calculations are available after
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||||
* additional read/write cycle, ECC calculations
|
||||
* are handled here.
|
||||
*/
|
||||
mt62xx_nand_write_ecc(mtd, len);
|
||||
} else {
|
||||
if (len % 4)
|
||||
printk(KERN_ERR "Length parameter is not aligned\n");
|
||||
|
||||
for (i = 0; i < len/4; ++i)
|
||||
writel(buf_32[i], chip->IO_ADDR_W);
|
||||
}
|
||||
}
|
||||
|
||||
static int mt62xx_nand_ecc_calculate(struct mtd_info *mtd, const uint8_t *dat,
|
||||
uint8_t *ecc_code)
|
||||
{
|
||||
struct nand_chip *chip = mtd->priv;
|
||||
|
||||
/*
|
||||
* Calculations are done automatically and there is no need for
|
||||
* additional operations.
|
||||
* This function is used to pass ECC block number to ecc_correct()
|
||||
* function to be able to correct proper ECC block.
|
||||
* MT62XX chips have address counter which points to address in page
|
||||
* which is currently read. We can use it to calculate which ECC block
|
||||
* has been already read.
|
||||
*/
|
||||
*ecc_code = readw(MTK_NFI_ADDRCNTR)/chip->ecc.size;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mt62xx_nand_ecc_correct(struct mtd_info *mtd, uint8_t *dat,
|
||||
uint8_t *read_ecc, uint8_t *ecc_block_nr)
|
||||
{
|
||||
int ecc_block_mask, ecc_status, ret;
|
||||
|
||||
/* ECC block number is calculated in ecc_calculate() function */
|
||||
if (*ecc_block_nr == 0)
|
||||
/* Should neve happen */
|
||||
return -1;
|
||||
|
||||
/* Decrease value to get proper index */
|
||||
(*ecc_block_nr)--;
|
||||
ecc_block_mask = 1 << *ecc_block_nr;
|
||||
ecc_block_mask |= ecc_block_mask << 16;
|
||||
|
||||
ecc_status = readl(MTK_NFI_ERRDET) & ecc_block_mask;
|
||||
if (ecc_status & 0xFF)
|
||||
/* Uncorrectable error detected */
|
||||
ret = -1;
|
||||
else if(ecc_status >> 16) {
|
||||
/* Correctable error detected */
|
||||
int address;
|
||||
uint32_t *buffer = (uint32_t *)dat;
|
||||
|
||||
/* Read address (for given block) where error occured */
|
||||
address = readw((uint32_t *)MTK_NFI_SYM0_ADDR + *ecc_block_nr);
|
||||
/* Correct error using syndrome word for given block */
|
||||
buffer[address >> 2] ^=
|
||||
readw((uint32_t *)MTK_NFI_SYM0_DATA + *ecc_block_nr);
|
||||
ret = 1;
|
||||
} else
|
||||
/* Data read without errors */
|
||||
ret = 0;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void mt62xx_nand_ecc_hwctl(struct mtd_info *mtd, int mode)
|
||||
{
|
||||
/* HW ECC doesn't need to be controlled, it's turned on during init */
|
||||
}
|
||||
|
||||
int board_nand_init(struct nand_chip *chip)
|
||||
{
|
||||
static int chip_nr = 0;
|
||||
struct mtd_info *mtd;
|
||||
|
||||
/* Power on NFI controller */
|
||||
writel(PDN_CON1_NFI, MTK_CONFG_PDN_CLR1);
|
||||
|
||||
|
|
@ -92,16 +374,47 @@ int board_nand_init(struct nand_chip *nand)
|
|||
writel(NFI_OPCON_FIFO_FLUSH | NFI_OPCON_FIFO_RST, MTK_NFI_OPCON);
|
||||
while(readl(MTK_NFI_OPCON))
|
||||
;
|
||||
writel(NFI_PAGEFMT_PSIZE_2048 |
|
||||
NFI_PAGEFMT_ADRMODE_LARGE_8IO |
|
||||
NFI_PAGEFMT_ECCBLKSIZE_1024,
|
||||
MTK_NFI_PAGEFMT);
|
||||
|
||||
writel(NFI_CON_SPARE_EN, MTK_NFI_CON);
|
||||
/* Enable spare area and ECC decoding for main */
|
||||
writel(NFI_CON_AUTOECC_DEC_EN |
|
||||
NFI_CON_MAIN_ECC_EN |
|
||||
NFI_CON_SPARE_EN,
|
||||
MTK_NFI_CON);
|
||||
/* Setup byte number in spare for ECC */
|
||||
writel(ECC_SPARE_BYTE_POS, MTK_NFI_SCON);
|
||||
|
||||
nand->cmd_ctrl = mtk_cmd_ctrl;
|
||||
nand->dev_ready = mtk_dev_ready;
|
||||
nand->ecc.mode = NAND_ECC_SOFT;
|
||||
chip->IO_ADDR_R = (uint32_t *)MTK_NFI_DATAR;
|
||||
chip->IO_ADDR_W = (uint32_t *)MTK_NFI_DATAW;
|
||||
chip->cmd_ctrl = mt62xx_nand_cmd_ctrl;
|
||||
chip->dev_ready = mt62xx_nand_dev_ready;
|
||||
chip->read_buf = mt62xx_nand_read_buf;
|
||||
chip->read_byte = mt62xx_nand_read_byte;
|
||||
chip->write_buf = mt62xx_nand_write_buf;
|
||||
chip->select_chip = mt62xx_nand_select_chip;
|
||||
|
||||
/* ECC settings */
|
||||
chip->ecc.mode = NAND_ECC_HW;
|
||||
chip->ecc.calculate = mt62xx_nand_ecc_calculate;
|
||||
chip->ecc.correct = mt62xx_nand_ecc_correct;
|
||||
chip->ecc.hwctl = mt62xx_nand_ecc_hwctl;
|
||||
chip->ecc.size = 256;
|
||||
|
||||
mtd = &nand_info[chip_nr++];
|
||||
|
||||
/* Detect NAND chip */
|
||||
if (nand_scan_ident(mtd, 1, NULL))
|
||||
return -ENXIO;
|
||||
|
||||
if (mtd->writesize > 512)
|
||||
/* Large page NAND detected */
|
||||
writel(NFI_PAGEFMT_PSIZE_2048 |
|
||||
NFI_PAGEFMT_ADRMODE_LARGE_8IO |
|
||||
NFI_PAGEFMT_ECCBLKSIZE_256,
|
||||
MTK_NFI_PAGEFMT);
|
||||
else
|
||||
/* Small page NAND detected */
|
||||
writel(NFI_PAGEFMT_ECCBLKSIZE_256,
|
||||
MTK_NFI_PAGEFMT);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue