Add support for EmbeddedPlanet EP88x boards
Patch by Yuli Barcohen, 13 Jul 2005
This commit is contained in:
Wolfgang Denk
parent
763b5f34c3
commit
84c960ce6d
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@ -2,6 +2,9 @@
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Changes since U-Boot 1.1.4:
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Changes since U-Boot 1.1.4:
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======================================================================
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======================================================================
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* Add support for EmbeddedPlanet EP88x boards
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Patch by Yuli Barcohen, 13 Jul 2005
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* Remove board specific configuration includes from the common xilinx
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* Remove board specific configuration includes from the common xilinx
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ethernet and iic adapter code.
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ethernet and iic adapter code.
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Patch by Michael Libeskind, 12 Jul 2005
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Patch by Michael Libeskind, 12 Jul 2005
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20
MAKEALL
20
MAKEALL
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@ -43,16 +43,16 @@ LIST_8xx=" \
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CCM IP860 NETPHONE RPXlite_DW \
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CCM IP860 NETPHONE RPXlite_DW \
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cogent_mpc8xx IVML24 NETTA RRvision \
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cogent_mpc8xx IVML24 NETTA RRvision \
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ELPT860 IVML24_128 NETTA2 SM850 \
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ELPT860 IVML24_128 NETTA2 SM850 \
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ESTEEM192E IVML24_256 NETTA_ISDN SPD823TS \
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EP88x IVML24_256 NETTA_ISDN SPD823TS \
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ETX094 IVMS8 NETVIA svm_sc8xx \
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ESTEEM192E IVMS8 NETVIA svm_sc8xx \
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FADS823 IVMS8_128 NETVIA_V2 SXNI855T \
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ETX094 IVMS8_128 NETVIA_V2 SXNI855T \
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FADS850SAR IVMS8_256 NX823 TOP860 \
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FADS823 IVMS8_256 NX823 TOP860 \
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FADS860T KUP4K pcu_e TQM823L \
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FADS850SAR KUP4K pcu_e TQM823L \
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FLAGADM KUP4X QS823 TQM823L_LCD \
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FADS860T KUP4X QS823 TQM823L_LCD \
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FPS850L LANTEC QS850 TQM850L \
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FLAGADM LANTEC QS850 TQM850L \
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GEN860T lwmon QS860T TQM855L \
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FPS850L lwmon QS860T TQM855L \
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GEN860T_SC MBX quantum TQM860L \
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GEN860T MBX quantum TQM860L \
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uc100 \
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GEN860T_SC uc100 \
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v37 \
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v37 \
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"
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"
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3
Makefile
3
Makefile
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@ -441,6 +441,9 @@ cogent_mpc8xx_config: unconfig
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ELPT860_config: unconfig
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ELPT860_config: unconfig
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@./mkconfig $(@:_config=) ppc mpc8xx elpt860 LEOX
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@./mkconfig $(@:_config=) ppc mpc8xx elpt860 LEOX
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EP88x_config: unconfig
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@./mkconfig $(@:_config=) ppc mpc8xx ep88x
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ESTEEM192E_config: unconfig
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ESTEEM192E_config: unconfig
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@./mkconfig $(@:_config=) ppc mpc8xx esteem192e
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@./mkconfig $(@:_config=) ppc mpc8xx esteem192e
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@ -0,0 +1,46 @@
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#
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# Copyright (C) 2004 Arabella Software Ltd.
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# Yuli Barcohen <yuli@arabellasw.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = lib$(BOARD).a
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OBJS := $(BOARD).o
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$(LIB): $(OBJS) $(SOBJS)
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$(AR) crv $@ $(OBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
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$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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-include .depend
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#########################################################################
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@ -0,0 +1,27 @@
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#
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# Copyright (C) 2005 Arabella Software Ltd.
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# Yuli Barcohen <yuli@arabellasw.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# Embedded Planet EP88x boards
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#
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TEXT_BASE = 0xFC000000
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@ -0,0 +1,133 @@
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/*
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* Copyright (C) 2005 Arabella Software Ltd.
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* Yuli Barcohen <yuli@arabellasw.com>
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*
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* Support for Embedded Planet EP88x boards.
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* Tested on EP88xC with MPC885 CPU, 64MB SDRAM and 16MB flash.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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||||||
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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||||||
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*
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* This program is distributed in the hope that it will be useful,
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||||||
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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||||||
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc8xx.h>
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/*
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* SDRAM uses two Micron chips.
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* Minimal CPU frequency is 40MHz.
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*/
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static uint sdram_table[] = {
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/* Single read (offset 0x00 in UPM RAM) */
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0xEFCBCC04, 0x0F37C804, 0x0EEEC004, 0x01B98404,
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0x1FF74C00, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
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/* Burst read (offset 0x08 in UPM RAM) */
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0xEFCBCC04, 0x0F37C804, 0x0EEEC004, 0x00BDC404,
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0x00FFCC00, 0x00FFCC00, 0x01FB8C00, 0x1FF74C00,
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0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
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0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
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/* Single write (offset 0x18 in UPM RAM) */
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0xEFCBCC04, 0x0F37C804, 0x0EEE8002, 0x01B90404,
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0x1FF74C05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
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/* Burst write (offset 0x20 in UPM RAM) */
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0xEFCBCC04, 0x0F37C804, 0x0EEE8000, 0x00BD4400,
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0x00FFCC00, 0x00FFCC02, 0x01FB8C04, 0x1FF74C05,
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0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
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0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05, 0xFFFFCC05,
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/* Refresh (offset 0x30 in UPM RAM) */
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0xEFFACC04, 0x0FF5CC04, 0x0FFFCC04, 0x1FFFCC04,
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0xFFFFCC05, 0xFFFFCC05, 0xEFFB8C34, 0x0FF74C34,
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0x0FFACCB4, 0x0FF5CC34, 0x0FFFC034, 0x0FFFC0B4,
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/* Exception (offset 0x3C in UPM RAM) */
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0x0FEA8034, 0x1FB54034, 0xFFFFCC34, 0xFFFFCC05
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};
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int board_early_init_f (void)
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{
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vu_char *bcsr = (vu_char *)CFG_BCSR;
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bcsr[0] |= 0x0C; /* Turn the LEDs off */
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bcsr[2] |= 0x08; /* Enable flash WE# line - necessary for
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flash detection by CFI driver
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*/
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#if defined(CONFIG_8xx_CONS_SMC1)
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bcsr[6] |= 0x10; /* Enables RS-232 transceiver */
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#endif
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#if defined(CONFIG_8xx_CONS_SCC2)
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bcsr[7] |= 0x10; /* Enables RS-232 transceiver */
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#endif
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#ifdef CONFIG_ETHER_ON_FEC1
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bcsr[8] |= 0xC0; /* Enable Ethernet 1 PHY */
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#endif
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#ifdef CONFIG_ETHER_ON_FEC2
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bcsr[8] |= 0x30; /* Enable Ethernet 2 PHY */
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#endif
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return 0;
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}
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long int initdram (int board_type)
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{
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long int msize;
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volatile immap_t *immap = (volatile immap_t *)CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint));
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/* Configure SDRAM refresh */
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memctl->memc_mptpr = MPTPR_PTP_DIV2; /* BRGCLK/2 */
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memctl->memc_mamr = (65 << 24) | CFG_MAMR; /* No refresh */
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udelay(100);
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/* Run MRS pattern from location 0x36 */
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memctl->memc_mar = 0x88;
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memctl->memc_mcr = 0x80002236;
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udelay(100);
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memctl->memc_mamr |= MAMR_PTAE; /* Enable refresh */
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memctl->memc_or1 = ~(CFG_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM;
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memctl->memc_br1 = CFG_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V;
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msize = get_ram_size(CFG_SDRAM_BASE, CFG_SDRAM_MAX_SIZE);
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memctl->memc_or1 |= ~(msize - 1);
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return msize;
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}
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int checkboard( void )
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{
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vu_char *bcsr = (vu_char *)CFG_BCSR;
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puts("Board: ");
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switch (bcsr[15]) {
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case 0xE7:
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puts("EP88xC 1.0");
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break;
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default:
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printf("unknown ID=%02X", bcsr[15]);
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}
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printf(" CPLD revision %d\n", bcsr[14]);
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return 0;
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}
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@ -0,0 +1,122 @@
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/*
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* (C) Copyright 2001-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Modified by Yuli Barcohen <yuli@arabellasw.com>
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*
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* See file CREDITS for list of people who contributed to this
|
||||||
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* project.
|
||||||
|
*
|
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|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
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|
||||||
|
OUTPUT_ARCH(powerpc)
|
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|
SECTIONS
|
||||||
|
{
|
||||||
|
/* Read-only sections, merged into text segment: */
|
||||||
|
. = + SIZEOF_HEADERS;
|
||||||
|
.interp : { *(.interp) }
|
||||||
|
.hash : { *(.hash) }
|
||||||
|
.dynsym : { *(.dynsym) }
|
||||||
|
.dynstr : { *(.dynstr) }
|
||||||
|
.rel.text : { *(.rel.text) }
|
||||||
|
.rela.text : { *(.rela.text) }
|
||||||
|
.rel.data : { *(.rel.data) }
|
||||||
|
.rela.data : { *(.rela.data) }
|
||||||
|
.rel.rodata : { *(.rel.rodata) }
|
||||||
|
.rela.rodata : { *(.rela.rodata) }
|
||||||
|
.rel.got : { *(.rel.got) }
|
||||||
|
.rela.got : { *(.rela.got) }
|
||||||
|
.rel.ctors : { *(.rel.ctors) }
|
||||||
|
.rela.ctors : { *(.rela.ctors) }
|
||||||
|
.rel.dtors : { *(.rel.dtors) }
|
||||||
|
.rela.dtors : { *(.rela.dtors) }
|
||||||
|
.rel.bss : { *(.rel.bss) }
|
||||||
|
.rela.bss : { *(.rela.bss) }
|
||||||
|
.rel.plt : { *(.rel.plt) }
|
||||||
|
.rela.plt : { *(.rela.plt) }
|
||||||
|
.init : { *(.init) }
|
||||||
|
.plt : { *(.plt) }
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
cpu/mpc8xx/start.o (.text)
|
||||||
|
*(.text)
|
||||||
|
*(.fixup)
|
||||||
|
*(.got1)
|
||||||
|
. = ALIGN(16);
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||||||
|
*(.rodata)
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||||||
|
*(.rodata1)
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||||||
|
*(.rodata.str1.4)
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||||||
|
}
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||||||
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.fini : { *(.fini) } =0
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||||||
|
.ctors : { *(.ctors) }
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||||||
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.dtors : { *(.dtors) }
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||||||
|
|
||||||
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/* Read-write section, merged into data segment: */
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||||||
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. = (. + 0x0FFF) & 0xFFFFF000;
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||||||
|
_erotext = .;
|
||||||
|
PROVIDE (erotext = .);
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||||||
|
.reloc :
|
||||||
|
{
|
||||||
|
*(.got)
|
||||||
|
_GOT2_TABLE_ = .;
|
||||||
|
*(.got2)
|
||||||
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_FIXUP_TABLE_ = .;
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||||||
|
*(.fixup)
|
||||||
|
}
|
||||||
|
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
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||||||
|
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
|
||||||
|
|
||||||
|
.data :
|
||||||
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{
|
||||||
|
*(.data)
|
||||||
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*(.data1)
|
||||||
|
*(.sdata)
|
||||||
|
*(.sdata2)
|
||||||
|
*(.dynamic)
|
||||||
|
CONSTRUCTORS
|
||||||
|
}
|
||||||
|
_edata = .;
|
||||||
|
PROVIDE (edata = .);
|
||||||
|
|
||||||
|
__u_boot_cmd_start = .;
|
||||||
|
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||||
|
__u_boot_cmd_end = .;
|
||||||
|
|
||||||
|
|
||||||
|
__start___ex_table = .;
|
||||||
|
__ex_table : { *(__ex_table) }
|
||||||
|
__stop___ex_table = .;
|
||||||
|
|
||||||
|
. = ALIGN(4096);
|
||||||
|
__init_begin = .;
|
||||||
|
.text.init : { *(.text.init) }
|
||||||
|
.data.init : { *(.data.init) }
|
||||||
|
. = ALIGN(4096);
|
||||||
|
__init_end = .;
|
||||||
|
|
||||||
|
__bss_start = .;
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
*(.sbss) *(.scommon)
|
||||||
|
*(.dynbss)
|
||||||
|
*(.bss)
|
||||||
|
*(COMMON)
|
||||||
|
}
|
||||||
|
_end = . ;
|
||||||
|
PROVIDE (end = .);
|
||||||
|
}
|
||||||
|
ENTRY(_start)
|
||||||
|
|
@ -0,0 +1,205 @@
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2005 Arabella Software Ltd.
|
||||||
|
* Yuli Barcohen <yuli@arabellasw.com>
|
||||||
|
*
|
||||||
|
* Support for Embedded Planet EP88x boards.
|
||||||
|
* Tested on EP88xC with MPC885 CPU, 64MB SDRAM and 16MB flash.
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
#ifndef __CONFIG_H
|
||||||
|
#define __CONFIG_H
|
||||||
|
|
||||||
|
#define CONFIG_MPC885
|
||||||
|
|
||||||
|
#define CONFIG_EP88X /* Embedded Planet EP88x board */
|
||||||
|
|
||||||
|
#define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */
|
||||||
|
|
||||||
|
/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
|
||||||
|
#define CONFIG_ENV_OVERWRITE
|
||||||
|
|
||||||
|
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
|
||||||
|
#define CONFIG_BAUDRATE 38400
|
||||||
|
|
||||||
|
#define CONFIG_ETHER_ON_FEC1 /* Enable Ethernet on FEC1 */
|
||||||
|
#define CONFIG_ETHER_ON_FEC2 /* Enable Ethernet on FEC2 */
|
||||||
|
#if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2)
|
||||||
|
#define CFG_DISCOVER_PHY
|
||||||
|
#define FEC_ENET
|
||||||
|
#endif /* CONFIG_FEC_ENET */
|
||||||
|
|
||||||
|
#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
|
||||||
|
#define CONFIG_8xx_CPUCLK_DEFAULT 100000000
|
||||||
|
#define CFG_8xx_CPUCLK_MIN 40000000
|
||||||
|
#define CFG_8xx_CPUCLK_MAX 133000000
|
||||||
|
|
||||||
|
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
|
||||||
|
| CFG_CMD_DHCP \
|
||||||
|
| CFG_CMD_IMMAP \
|
||||||
|
| CFG_CMD_MII \
|
||||||
|
| CFG_CMD_PING \
|
||||||
|
)
|
||||||
|
|
||||||
|
/* This must be included AFTER the definition of CONFIG_COMMANDS */
|
||||||
|
#include <cmd_confdefs.h>
|
||||||
|
|
||||||
|
#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */
|
||||||
|
#define CONFIG_BOOTCOMMAND "bootm fe060000" /* Autoboot command */
|
||||||
|
#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=phys:2M(ROM)ro,-(root)"
|
||||||
|
|
||||||
|
#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */
|
||||||
|
#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* Miscellaneous configurable options
|
||||||
|
*/
|
||||||
|
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||||
|
#define CFG_HUSH_PARSER
|
||||||
|
#define CFG_PROMPT_HUSH_PS2 "> "
|
||||||
|
#define CFG_LONGHELP /* #undef to save memory */
|
||||||
|
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||||
|
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
|
||||||
|
#define CFG_MAXARGS 16 /* Max number of command args */
|
||||||
|
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||||
|
|
||||||
|
#define CFG_LOAD_ADDR 0x400000 /* Default load address */
|
||||||
|
|
||||||
|
#define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */
|
||||||
|
|
||||||
|
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* RAM configuration (note that CFG_SDRAM_BASE must be zero)
|
||||||
|
*/
|
||||||
|
#define CFG_SDRAM_BASE 0x00000000
|
||||||
|
#define CFG_SDRAM_MAX_SIZE 0x08000000 /* Up to 128 Mbyte */
|
||||||
|
|
||||||
|
#define CFG_MAMR 0x00805000
|
||||||
|
|
||||||
|
/*
|
||||||
|
* 4096 Up to 4096 SDRAM rows
|
||||||
|
* 1000 factor s -> ms
|
||||||
|
* 32 PTP (pre-divider from MPTPR)
|
||||||
|
* 4 Number of refresh cycles per period
|
||||||
|
* 64 Refresh cycle in ms per number of rows
|
||||||
|
*/
|
||||||
|
#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
|
||||||
|
|
||||||
|
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
|
||||||
|
#define CFG_MEMTEST_END 0x00500000 /* 1 ... 5 MB in SDRAM */
|
||||||
|
|
||||||
|
#define CFG_RESET_ADDRESS 0x09900000
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* For booting Linux, the board info and command line data
|
||||||
|
* have to be in the first 8 MB of memory, since this is
|
||||||
|
* the maximum mapped by the Linux kernel during initialization.
|
||||||
|
*/
|
||||||
|
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||||
|
|
||||||
|
#define CFG_MONITOR_BASE TEXT_BASE
|
||||||
|
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 KB for Monitor */
|
||||||
|
#ifdef CONFIG_BZIP2
|
||||||
|
#define CFG_MALLOC_LEN (4096 << 10) /* Reserve ~4 MB for malloc() */
|
||||||
|
#else
|
||||||
|
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
|
||||||
|
#endif /* CONFIG_BZIP2 */
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* Flash organisation
|
||||||
|
*/
|
||||||
|
#define CFG_FLASH_BASE 0xFC000000
|
||||||
|
#define CFG_FLASH_CFI /* The flash is CFI compatible */
|
||||||
|
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
|
||||||
|
#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
|
||||||
|
#define CFG_MAX_FLASH_SECT 512 /* Max num of sects on one chip */
|
||||||
|
|
||||||
|
/* Environment is in flash */
|
||||||
|
#define CFG_ENV_IS_IN_FLASH
|
||||||
|
#define CFG_ENV_SECT_SIZE 0x20000 /* We use one complete sector */
|
||||||
|
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
|
||||||
|
|
||||||
|
#define CFG_OR0_PRELIM 0xFC000160
|
||||||
|
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_32 | BR_MS_GPCM | BR_V)
|
||||||
|
|
||||||
|
#define CFG_DIRECT_FLASH_TFTP
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* BCSR
|
||||||
|
*/
|
||||||
|
#define CFG_OR3_PRELIM 0xFF0005B0
|
||||||
|
#define CFG_BR3_PRELIM (0xFA000000 |BR_PS_16 | BR_MS_GPCM | BR_V)
|
||||||
|
|
||||||
|
#define CFG_BCSR 0xFA400000
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* Internal Memory Map Register
|
||||||
|
*/
|
||||||
|
#define CFG_IMMR 0xF0000000
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||||
|
*/
|
||||||
|
#define CFG_INIT_RAM_ADDR CFG_IMMR
|
||||||
|
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
|
||||||
|
#define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial data */
|
||||||
|
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||||
|
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* Configuration registers
|
||||||
|
*/
|
||||||
|
#ifdef CONFIG_WATCHDOG
|
||||||
|
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \
|
||||||
|
SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | \
|
||||||
|
SYPCR_SWP)
|
||||||
|
#else
|
||||||
|
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \
|
||||||
|
SYPCR_SWF | SYPCR_SWP)
|
||||||
|
#endif /* CONFIG_WATCHDOG */
|
||||||
|
|
||||||
|
#define CFG_SIUMCR (SIUMCR_MLRC01 | SIUMCR_DBGC11)
|
||||||
|
|
||||||
|
/* TBSCR - Time Base Status and Control Register */
|
||||||
|
#define CFG_TBSCR (TBSCR_TBF | TBSCR_TBE)
|
||||||
|
|
||||||
|
/* PISCR - Periodic Interrupt Status and Control */
|
||||||
|
#define CFG_PISCR PISCR_PS
|
||||||
|
|
||||||
|
/* SCCR - System Clock and reset Control Register */
|
||||||
|
#define SCCR_MASK SCCR_EBDF11
|
||||||
|
#define CFG_SCCR SCCR_RTSEL
|
||||||
|
|
||||||
|
#define CFG_DER 0
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* Cache Configuration
|
||||||
|
*/
|
||||||
|
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx chips */
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* Internal Definitions
|
||||||
|
*
|
||||||
|
* Boot Flags
|
||||||
|
*/
|
||||||
|
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from flash */
|
||||||
|
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||||
|
|
||||||
|
#endif /* __CONFIG_H */
|
||||||
Loading…
Reference in New Issue