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Enable 8544 support 

* Add support to the Makefile
* Add 8544 configuration support to the tsec driver
* Add 8544 SVR numbers to processor.h

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
This commit is contained in:
Andy Fleming 2007-04-23 02:24:28 -05:00 committed by Andrew Fleming-AFLEMING
parent 0d8c3a2096
commit 81f481ca70
5 changed files with 23 additions and 8 deletions
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8
MAKEALL
View File

@ -142,10 +142,10 @@ LIST_83xx=" \
######################################################################### #########################################################################
LIST_85xx=" \ LIST_85xx=" \
MPC8540ADS MPC8540EVAL MPC8541CDS MPC8548CDS \ MPC8540ADS MPC8540EVAL MPC8541CDS MPC8544DS \
MPC8555CDS MPC8560ADS PM854 PM856 \ MPC8548CDS MPC8555CDS MPC8560ADS PM854 \
sbc8540 sbc8560 stxgp3 TQM8540 \ PM856 sbc8540 sbc8560 stxgp3 \
TQM8541 TQM8555 TQM8560 \ TQM8540 TQM8541 TQM8555 TQM8560 \
" "
######################################################################### #########################################################################

3
Makefile
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@ -1730,6 +1730,9 @@ MPC8560ADS_config: unconfig
MPC8541CDS_config: unconfig MPC8541CDS_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8541cds cds @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8541cds cds
MPC8544DS_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8544ds freescale
MPC8548CDS_config: unconfig MPC8548CDS_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8548cds cds @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8548cds cds

6
drivers/tsec.c
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@ -5,7 +5,7 @@
* terms of the GNU Public License, Version 2, incorporated * terms of the GNU Public License, Version 2, incorporated
* herein by reference. * herein by reference.
* *
* Copyright 2004 Freescale Semiconductor. * Copyright 2004, 2007 Freescale Semiconductor, Inc.
* (C) Copyright 2003, Motorola, Inc. * (C) Copyright 2003, Motorola, Inc.
* author Andy Fleming * author Andy Fleming
* *
@ -66,7 +66,11 @@ struct tsec_info_struct {
*/ */
static struct tsec_info_struct tsec_info[] = { static struct tsec_info_struct tsec_info[] = {
#if defined(CONFIG_MPC85XX_TSEC1) || defined(CONFIG_MPC83XX_TSEC1) #if defined(CONFIG_MPC85XX_TSEC1) || defined(CONFIG_MPC83XX_TSEC1)
#if defined(CONFIG_MPC8544DS)
{TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX},
#else
{TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX}, {TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX},
#endif
#elif defined(CONFIG_MPC86XX_TSEC1) #elif defined(CONFIG_MPC86XX_TSEC1)
{TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX}, {TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX},
#else #else

3
drivers/tsec.h
View File

@ -7,7 +7,7 @@
* terms of the GNU Public License, Version 2, incorporated * terms of the GNU Public License, Version 2, incorporated
* herein by reference. * herein by reference.
* *
* Copyright 2004 Freescale Semiconductor. * Copyright 2004, 2007 Freescale Semiconductor, Inc.
* (C) Copyright 2003, Motorola, Inc. * (C) Copyright 2003, Motorola, Inc.
* maintained by Xianghua Xiao (x.xiao@motorola.com) * maintained by Xianghua Xiao (x.xiao@motorola.com)
* author Andy Fleming * author Andy Fleming
@ -65,6 +65,7 @@
#define ECNTRL_INIT_SETTINGS 0x00001000 #define ECNTRL_INIT_SETTINGS 0x00001000
#define ECNTRL_TBI_MODE 0x00000020 #define ECNTRL_TBI_MODE 0x00000020
#define ECNTRL_R100 0x00000008 #define ECNTRL_R100 0x00000008
#define ECNTRL_SGMII_MODE 0x00000002
#define miim_end -2 #define miim_end -2
#define miim_read -1 #define miim_read -1

11
include/asm-ppc/processor.h
View File

@ -232,6 +232,9 @@
#define HID0_BHTE (1<<2) /* Branch History Table Enable */ #define HID0_BHTE (1<<2) /* Branch History Table Enable */
#define HID0_BTCD (1<<1) /* Branch target cache disable */ #define HID0_BTCD (1<<1) /* Branch target cache disable */
#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */ #define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */
#define HID1_RFXE (1<<17) /* Read Fault Exception Enable */
#define HID1_ASTME (1<<13) /* Address bus streaming mode */
#define HID1_ABE (1<<12) /* Address broadcast enable */
#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
#ifndef CONFIG_BOOKE #ifndef CONFIG_BOOKE
#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */
@ -415,10 +418,12 @@
#define SPRN_IVOR15 0x19f /* Interrupt Vector Offset Register 15 */ #define SPRN_IVOR15 0x19f /* Interrupt Vector Offset Register 15 */
/* e500 definitions */ /* e500 definitions */
#define SPRN_L1CSR0 0x3f2 /* L1 Cache Control and Status Register 0 */ #define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */
#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
#define SPRN_L1CSR1 0x3f3 /* L1 Cache Control and Status Register 1 */ #define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */
#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
@ -840,6 +845,8 @@
#define SVR_8560 0x8070 #define SVR_8560 0x8070
#define SVR_8555 0x8079 #define SVR_8555 0x8079
#define SVR_8541 0x807A #define SVR_8541 0x807A
#define SVR_8544 0x8034
#define SVR_8544_E 0x803C
#define SVR_8548 0x8031 #define SVR_8548 0x8031
#define SVR_8548_E 0x8039 #define SVR_8548_E 0x8039
#define SVR_8641 0x8090 #define SVR_8641 0x8090