SPEAr : Adding basic SPEAr architecture support.
SPEAr Architecture support added. It contains the support for following SPEAr blocks - Timer - System controller - Misc registers Signed-off-by: Vipin <vipin.kumar@st.com>
This commit is contained in:
Vipin KUMAR
Tom Rix
parent
6fffcdf8c8
commit
81c0ebf623
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(SOC).a
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COBJS := reset.o \
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timer.o
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SOBJS :=
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,54 @@
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/*
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* (C) Copyright 2009
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* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
|
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/spr_syscntl.h>
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void reset_cpu(ulong ignored)
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{
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struct syscntl_regs *syscntl_regs_p =
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(struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE;
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printf("System is going to reboot ...\n");
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/*
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* This 1 second delay will allow the above message
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* to be printed before reset
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*/
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udelay((1000 * 1000));
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/* Going into slow mode before resetting SOC */
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writel(0x02, &syscntl_regs_p->scctrl);
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/*
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* Writing any value to the system status register will
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* reset the SoC
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*/
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writel(0x00, &syscntl_regs_p->scsysstat);
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/* system will restart */
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while (1)
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;
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}
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@ -0,0 +1,153 @@
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/*
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* (C) Copyright 2009
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* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
|
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* published by the Free Software Foundation; either version 2 of
|
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/spr_gpt.h>
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#include <asm/arch/spr_misc.h>
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#define GPT_RESOLUTION (CONFIG_SPEAR_HZ_CLOCK / CONFIG_SPEAR_HZ)
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#define READ_TIMER() (readl(&gpt_regs_p->count) & GPT_FREE_RUNNING)
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static struct gpt_regs *const gpt_regs_p =
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(struct gpt_regs *)CONFIG_SPEAR_TIMERBASE;
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static struct misc_regs *const misc_regs_p =
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(struct misc_regs *)CONFIG_SPEAR_MISCBASE;
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static ulong timestamp;
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static ulong lastdec;
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int timer_init(void)
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{
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u32 synth;
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/* Prescaler setting */
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#if defined(CONFIG_SPEAR3XX)
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writel(MISC_PRSC_CFG, &misc_regs_p->prsc2_clk_cfg);
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synth = MISC_GPT4SYNTH;
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#elif defined(CONFIG_SPEAR600)
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writel(MISC_PRSC_CFG, &misc_regs_p->prsc1_clk_cfg);
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synth = MISC_GPT3SYNTH;
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#else
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# error Incorrect config. Can only be spear{600|300|310|320}
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#endif
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writel(readl(&misc_regs_p->periph_clk_cfg) | synth,
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&misc_regs_p->periph_clk_cfg);
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/* disable timers */
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writel(GPT_PRESCALER_1 | GPT_MODE_AUTO_RELOAD, &gpt_regs_p->control);
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/* load value for free running */
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writel(GPT_FREE_RUNNING, &gpt_regs_p->compare);
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/* auto reload, start timer */
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writel(readl(&gpt_regs_p->control) | GPT_ENABLE, &gpt_regs_p->control);
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reset_timer_masked();
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return 0;
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}
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/*
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* timer without interrupts
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*/
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void reset_timer(void)
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{
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reset_timer_masked();
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}
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ulong get_timer(ulong base)
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{
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return (get_timer_masked() / GPT_RESOLUTION) - base;
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}
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void set_timer(ulong t)
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{
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timestamp = t;
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}
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void __udelay(unsigned long usec)
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{
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ulong tmo;
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ulong start = get_timer_masked();
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ulong tenudelcnt = CONFIG_SPEAR_HZ_CLOCK / (1000 * 100);
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ulong rndoff;
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rndoff = (usec % 10) ? 1 : 0;
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/* tenudelcnt timer tick gives 10 microsecconds delay */
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tmo = ((usec / 10) + rndoff) * tenudelcnt;
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while ((ulong) (get_timer_masked() - start) < tmo)
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;
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}
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void reset_timer_masked(void)
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{
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/* reset time */
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lastdec = READ_TIMER();
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timestamp = 0;
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}
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ulong get_timer_masked(void)
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{
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ulong now = READ_TIMER();
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if (now >= lastdec) {
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/* normal mode */
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timestamp += now - lastdec;
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} else {
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/* we have an overflow ... */
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timestamp += now + GPT_FREE_RUNNING - lastdec;
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}
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lastdec = now;
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return timestamp;
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}
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void udelay_masked(unsigned long usec)
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{
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return udelay(usec);
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}
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/*
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* This function is derived from PowerPC code (read timebase as long long).
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* On ARM it just returns the timer value.
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*/
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unsigned long long get_ticks(void)
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{
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return get_timer(0);
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}
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/*
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* This function is derived from PowerPC code (timebase clock frequency).
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* On ARM it returns the number of timer ticks per second.
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*/
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ulong get_tbclk(void)
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{
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return CONFIG_SPEAR_HZ;
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}
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@ -0,0 +1,66 @@
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/*
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* (C) Copyright 2009
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* Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
|
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
|
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*
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* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
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||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _ASM_ARCH_HARDWARE_H
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#define _ASM_ARCH_HARDWARE_H
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#define CONFIG_SYS_USBD_BASE (0xE1100000)
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#define CONFIG_SYS_PLUG_BASE (0xE1200000)
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#define CONFIG_SYS_FIFO_BASE (0xE1000800)
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#define CONFIG_SYS_SMI_BASE (0xFC000000)
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#define CONFIG_SPEAR_SYSCNTLBASE (0xFCA00000)
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#define CONFIG_SPEAR_TIMERBASE (0xFC800000)
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#define CONFIG_SPEAR_MISCBASE (0xFCA80000)
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#define CONFIG_SYS_NAND_CLE (1 << 16)
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#define CONFIG_SYS_NAND_ALE (1 << 17)
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#if defined(CONFIG_SPEAR600)
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#define CONFIG_SYS_I2C_BASE (0xD0200000)
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#define CONFIG_SPEAR_FSMCBASE (0xD1800000)
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#elif defined(CONFIG_SPEAR300)
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#define CONFIG_SYS_I2C_BASE (0xD0180000)
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#define CONFIG_SPEAR_FSMCBASE (0x94000000)
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#elif defined(CONFIG_SPEAR310)
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#define CONFIG_SYS_I2C_BASE (0xD0180000)
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#define CONFIG_SPEAR_FSMCBASE (0x44000000)
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#undef CONFIG_SYS_NAND_CLE
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#undef CONFIG_SYS_NAND_ALE
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#define CONFIG_SYS_NAND_CLE (1 << 17)
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#define CONFIG_SYS_NAND_ALE (1 << 16)
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#define CONFIG_SPEAR_EMIBASE (0x4F000000)
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#define CONFIG_SPEAR_RASBASE (0xB4000000)
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#elif defined(CONFIG_SPEAR320)
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#define CONFIG_SYS_I2C_BASE (0xD0180000)
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#define CONFIG_SPEAR_FSMCBASE (0x4C000000)
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#define CONFIG_SPEAR_EMIBASE (0x40000000)
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#define CONFIG_SPEAR_RASBASE (0xB3000000)
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#endif
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#endif /* _ASM_ARCH_HARDWARE_H */
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@ -0,0 +1,85 @@
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/*
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* (C) Copyright 2009
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* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
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*
|
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* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _SPR_GPT_H
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#define _SPR_GPT_H
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struct gpt_regs {
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u8 reserved[0x80];
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u32 control;
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u32 status;
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u32 compare;
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u32 count;
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u32 capture_re;
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u32 capture_fe;
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};
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/*
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* TIMER_CONTROL register settings
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*/
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#define GPT_PRESCALER_MASK 0x000F
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#define GPT_PRESCALER_1 0x0000
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#define GPT_PRESCALER_2 0x0001
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#define GPT_PRESCALER_4 0x0002
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#define GPT_PRESCALER_8 0x0003
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#define GPT_PRESCALER_16 0x0004
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#define GPT_PRESCALER_32 0x0005
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#define GPT_PRESCALER_64 0x0006
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#define GPT_PRESCALER_128 0x0007
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#define GPT_PRESCALER_256 0x0008
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#define GPT_MODE_SINGLE_SHOT 0x0010
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#define GPT_MODE_AUTO_RELOAD 0x0000
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#define GPT_ENABLE 0x0020
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#define GPT_CAPT_MODE_MASK 0x00C0
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#define GPT_CAPT_MODE_NONE 0x0000
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#define GPT_CAPT_MODE_RE 0x0040
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#define GPT_CAPT_MODE_FE 0x0080
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#define GPT_CAPT_MODE_BOTH 0x00C0
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#define GPT_INT_MATCH 0x0100
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#define GPT_INT_FE 0x0200
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#define GPT_INT_RE 0x0400
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/*
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* TIMER_STATUS register settings
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*/
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#define GPT_STS_MATCH 0x0001
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#define GPT_STS_FE 0x0002
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#define GPT_STS_RE 0x0004
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/*
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* TIMER_COMPARE register settings
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*/
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#define GPT_FREE_RUNNING 0xFFFF
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/* Timer, HZ specific defines */
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#define CONFIG_SPEAR_HZ (1000)
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#define CONFIG_SPEAR_HZ_CLOCK (8300000)
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#endif
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@ -0,0 +1,130 @@
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/*
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* (C) Copyright 2009
|
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* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
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#ifndef _SPR_MISC_H
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#define _SPR_MISC_H
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struct misc_regs {
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u32 auto_cfg_reg; /* 0x0 */
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u32 armdbg_ctr_reg; /* 0x4 */
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u32 pll1_cntl; /* 0x8 */
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u32 pll1_frq; /* 0xc */
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u32 pll1_mod; /* 0x10 */
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u32 pll2_cntl; /* 0x14 */
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u32 pll2_frq; /* 0x18 */
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u32 pll2_mod; /* 0x1C */
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u32 pll_ctr_reg; /* 0x20 */
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u32 amba_clk_cfg; /* 0x24 */
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u32 periph_clk_cfg; /* 0x28 */
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u32 periph1_clken; /* 0x2C */
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u32 periph2_clken; /* 0x30 */
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u32 ras_clken; /* 0x34 */
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u32 periph1_rst; /* 0x38 */
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u32 periph2_rst; /* 0x3C */
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u32 ras_rst; /* 0x40 */
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u32 prsc1_clk_cfg; /* 0x44 */
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u32 prsc2_clk_cfg; /* 0x48 */
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u32 prsc3_clk_cfg; /* 0x4C */
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u32 amem_cfg_ctrl; /* 0x50 */
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u32 port_cfg_ctrl; /* 0x54 */
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u32 reserved_1; /* 0x58 */
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u32 clcd_synth_clk; /* 0x5C */
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u32 irda_synth_clk; /* 0x60 */
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u32 uart_synth_clk; /* 0x64 */
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u32 gmac_synth_clk; /* 0x68 */
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u32 ras_synth1_clk; /* 0x6C */
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u32 ras_synth2_clk; /* 0x70 */
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u32 ras_synth3_clk; /* 0x74 */
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u32 ras_synth4_clk; /* 0x78 */
|
||||
u32 arb_icm_ml1; /* 0x7C */
|
||||
u32 arb_icm_ml2; /* 0x80 */
|
||||
u32 arb_icm_ml3; /* 0x84 */
|
||||
u32 arb_icm_ml4; /* 0x88 */
|
||||
u32 arb_icm_ml5; /* 0x8C */
|
||||
u32 arb_icm_ml6; /* 0x90 */
|
||||
u32 arb_icm_ml7; /* 0x94 */
|
||||
u32 arb_icm_ml8; /* 0x98 */
|
||||
u32 arb_icm_ml9; /* 0x9C */
|
||||
u32 dma_src_sel; /* 0xA0 */
|
||||
u32 uphy_ctr_reg; /* 0xA4 */
|
||||
u32 gmac_ctr_reg; /* 0xA8 */
|
||||
u32 port_bridge_ctrl; /* 0xAC */
|
||||
u32 reserved_2[4]; /* 0xB0--0xBC */
|
||||
u32 prc1_ilck_ctrl_reg; /* 0xC0 */
|
||||
u32 prc2_ilck_ctrl_reg; /* 0xC4 */
|
||||
u32 prc3_ilck_ctrl_reg; /* 0xC8 */
|
||||
u32 prc4_ilck_ctrl_reg; /* 0xCC */
|
||||
u32 prc1_intr_ctrl_reg; /* 0xD0 */
|
||||
u32 prc2_intr_ctrl_reg; /* 0xD4 */
|
||||
u32 prc3_intr_ctrl_reg; /* 0xD8 */
|
||||
u32 prc4_intr_ctrl_reg; /* 0xDC */
|
||||
u32 powerdown_cfg_reg; /* 0xE0 */
|
||||
u32 ddr_1v8_compensation; /* 0xE4 */
|
||||
u32 ddr_2v5_compensation; /* 0xE8 */
|
||||
u32 core_3v3_compensation; /* 0xEC */
|
||||
u32 ddr_pad; /* 0xF0 */
|
||||
u32 bist1_ctr_reg; /* 0xF4 */
|
||||
u32 bist2_ctr_reg; /* 0xF8 */
|
||||
u32 bist3_ctr_reg; /* 0xFC */
|
||||
u32 bist4_ctr_reg; /* 0x100 */
|
||||
u32 bist5_ctr_reg; /* 0x104 */
|
||||
u32 bist1_rslt_reg; /* 0x108 */
|
||||
u32 bist2_rslt_reg; /* 0x10C */
|
||||
u32 bist3_rslt_reg; /* 0x110 */
|
||||
u32 bist4_rslt_reg; /* 0x114 */
|
||||
u32 bist5_rslt_reg; /* 0x118 */
|
||||
u32 syst_error_reg; /* 0x11C */
|
||||
u32 reserved_3[0x1FB8]; /* 0x120--0x7FFC */
|
||||
u32 ras_gpp1_in; /* 0x8000 */
|
||||
u32 ras_gpp2_in; /* 0x8004 */
|
||||
u32 ras_gpp1_out; /* 0x8008 */
|
||||
u32 ras_gpp2_out; /* 0x800C */
|
||||
};
|
||||
|
||||
/* AUTO_CFG_REG value */
|
||||
#define MISC_SOCCFGMSK 0x0000003F
|
||||
#define MISC_SOCCFG30 0x0000000C
|
||||
#define MISC_SOCCFG31 0x0000000D
|
||||
#define MISC_NANDDIS 0x00020000
|
||||
|
||||
/* PERIPH_CLK_CFG value */
|
||||
#define MISC_GPT3SYNTH 0x00000400
|
||||
#define MISC_GPT4SYNTH 0x00000800
|
||||
|
||||
/* PRSC_CLK_CFG value */
|
||||
/*
|
||||
* Fout = Fin / (2^(N+1) * (M + 1))
|
||||
*/
|
||||
#define MISC_PRSC_N_1 0x00001000
|
||||
#define MISC_PRSC_M_9 0x00000009
|
||||
#define MISC_PRSC_N_4 0x00004000
|
||||
#define MISC_PRSC_M_399 0x0000018F
|
||||
#define MISC_PRSC_N_6 0x00006000
|
||||
#define MISC_PRSC_M_2593 0x00000A21
|
||||
#define MISC_PRSC_M_124 0x0000007C
|
||||
#define MISC_PRSC_CFG (MISC_PRSC_N_1 | MISC_PRSC_M_9)
|
||||
|
||||
/* PERIPH1_CLKEN, PERIPH1_RST value */
|
||||
#define MISC_USBDENB 0x01000000
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* (C) Copyright 2009
|
||||
* Ryan CHEN, ST Micoelectronics, ryan.chen@st.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
struct syscntl_regs {
|
||||
u32 scctrl;
|
||||
u32 scsysstat;
|
||||
u32 scimctrl;
|
||||
u32 scimsysstat;
|
||||
u32 scxtalctrl;
|
||||
u32 scpllctrl;
|
||||
u32 scpllfctrl;
|
||||
u32 scperctrl0;
|
||||
u32 scperctrl1;
|
||||
u32 scperen;
|
||||
u32 scperdis;
|
||||
const u32 scperclken;
|
||||
const u32 scperstat;
|
||||
};
|
||||
Loading…
Reference in New Issue