4xx: Remove binary cpld bitstream from VOM405 board
This patch removes the cpld binary bitstream that is used by esd's cpld command on VOM405 boards. Because u-boot with an external cpld bitstream may not take more space in flash than before the u-boot binary is shrinked a little bit. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
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0bb1063036
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@ -20,10 +20,4 @@
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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# MA 02111-1307 USA
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#
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#
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TEXT_BASE = 0xFFFC8000
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#
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# esd VOH405 boards
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#
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TEXT_BASE = 0xFFFC0000
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#TEXT_BASE = 0x00FC0000
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File diff suppressed because it is too large
Load Diff
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@ -31,13 +31,6 @@ DECLARE_GLOBAL_DATA_PTR;
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extern void lxt971_no_sleep(void);
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extern void lxt971_no_sleep(void);
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/* fpga configuration data - not compressed, generated by bin2c */
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const unsigned char fpgadata[] =
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{
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#include "fpgadata.c"
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};
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int filesize = sizeof(fpgadata);
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int board_early_init_f (void)
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int board_early_init_f (void)
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{
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{
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/*
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/*
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@ -177,10 +177,10 @@
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
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#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
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#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
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#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
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#define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1)
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#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
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#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
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#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
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#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
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# define CONFIG_SYS_RAMBOOT 1
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# define CONFIG_SYS_RAMBOOT 1
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@ -231,8 +231,7 @@
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/*
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/*
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* FPGA stuff
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* FPGA stuff
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*/
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*/
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#define CONFIG_SYS_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */
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#define CONFIG_SYS_XSVF_DEFAULT_ADDR 0xfffc0000
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#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */
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/* FPGA program pin configuration */
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/* FPGA program pin configuration */
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#define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */
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#define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */
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@ -293,17 +292,7 @@
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* Default speed selection (cpu_plb_opb_ebc) in mhz.
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* Default speed selection (cpu_plb_opb_ebc) in mhz.
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* This value will be set if iic boot eprom is disabled.
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* This value will be set if iic boot eprom is disabled.
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*/
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*/
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#if 0
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#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
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#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
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#endif
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#if 0
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#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
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#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
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#endif
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#if 1
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#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
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#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
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#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
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#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
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#endif
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#endif /* __CONFIG_H */
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#endif /* __CONFIG_H */
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