* Patch by Pierre Aubert, 11 Mar 2004:
- add bitmap command and splash screen support in cfb console - add [optional] origin in the bitmap display command * Patch by Travis Sawyer, 11 Mar 2004: Fix ocotea board early init interrupt setup. * Patch by Thomas Viehweger, 11 Mar 2004: Remove redundand code; add PCI-specific bits to include/mpc8260.h
This commit is contained in:
parent
aaf224ab4e
commit
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10
CHANGELOG
10
CHANGELOG
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@ -2,6 +2,16 @@
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Changes for U-Boot 1.0.2:
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Changes for U-Boot 1.0.2:
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======================================================================
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======================================================================
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* Patch by Pierre Aubert, 11 Mar 2004:
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- add bitmap command and splash screen support in cfb console
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- add [optional] origin in the bitmap display command
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* Patch by Travis Sawyer, 11 Mar 2004:
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Fix ocotea board early init interrupt setup.
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* Patch by Thomas Viehweger, 11 Mar 2004:
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Remove redundand code; add PCI-specific bits to include/mpc8260.h
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* Patch by Stephan Linz, 09 Mar 2004
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* Patch by Stephan Linz, 09 Mar 2004
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- Add support for the SSV ADNP/ESC1 (Nios Softcore)
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- Add support for the SSV ADNP/ESC1 (Nios Softcore)
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@ -36,6 +36,7 @@ void fpga_init (void);
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int board_early_init_f (void)
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int board_early_init_f (void)
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{
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{
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unsigned long mfr;
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/*-------------------------------------------------------------------------+
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/*-------------------------------------------------------------------------+
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| Initialize EBC CONFIG
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| Initialize EBC CONFIG
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+-------------------------------------------------------------------------*/
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+-------------------------------------------------------------------------*/
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@ -116,6 +117,23 @@ int board_early_init_f (void)
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mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr (uic1sr, 0xffffffff); /* clear all */
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mtdcr (uic1sr, 0xffffffff); /* clear all */
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mtdcr (uic2sr, 0xffffffff); /* clear all */
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mtdcr (uic2er, 0x00000000); /* disable all */
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mtdcr (uic2cr, 0x00000000); /* all non-critical */
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mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */
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mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */
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mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr (uic2sr, 0xffffffff); /* clear all */
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mtdcr (uicb0sr, 0xfc000000); /* clear all */
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mtdcr (uicb0er, 0x00000000); /* disable all */
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mtdcr (uicb0cr, 0x00000000); /* all non-critical */
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mtdcr (uicb0pr, 0xfc000000); /* */
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mtdcr (uicb0tr, 0x00000000); /* */
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mtdcr (uicb0vr, 0x00000001); /* */
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mfsdr (sdr_mfr, mfr);
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mfr &= ~SDR0_MFR_ECS_MASK;
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/* mtsdr(sdr_mfr, mfr); */
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fpga_init();
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fpga_init();
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return 0;
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return 0;
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@ -32,7 +32,7 @@
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#if (CONFIG_COMMANDS & CFG_CMD_BMP)
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#if (CONFIG_COMMANDS & CFG_CMD_BMP)
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static int bmp_info (ulong addr);
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static int bmp_info (ulong addr);
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static int bmp_display (ulong addr);
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static int bmp_display (ulong addr, int x, int y);
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/*
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/*
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* Subroutine: do_bmp
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* Subroutine: do_bmp
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@ -47,6 +47,7 @@ static int bmp_display (ulong addr);
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int do_bmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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int do_bmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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{
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ulong addr;
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ulong addr;
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int x = 0, y = 0;
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switch (argc) {
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switch (argc) {
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case 2: /* use load_addr as default address */
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case 2: /* use load_addr as default address */
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@ -55,6 +56,11 @@ int do_bmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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case 3: /* use argument */
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case 3: /* use argument */
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addr = simple_strtoul(argv[2], NULL, 16);
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addr = simple_strtoul(argv[2], NULL, 16);
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break;
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break;
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case 5:
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addr = simple_strtoul(argv[2], NULL, 16);
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x = simple_strtoul(argv[3], NULL, 10);
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y = simple_strtoul(argv[4], NULL, 10);
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break;
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default:
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default:
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printf ("Usage:\n%s\n", cmdtp->usage);
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printf ("Usage:\n%s\n", cmdtp->usage);
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return 1;
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return 1;
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@ -66,7 +72,7 @@ int do_bmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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if (strncmp(argv[1],"info",1) == 0) {
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if (strncmp(argv[1],"info",1) == 0) {
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return (bmp_info(addr));
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return (bmp_info(addr));
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} else if (strncmp(argv[1],"display",1) == 0) {
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} else if (strncmp(argv[1],"display",1) == 0) {
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return (bmp_display(addr));
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return (bmp_display(addr, x, y));
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} else {
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} else {
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printf ("Usage:\n%s\n", cmdtp->usage);
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printf ("Usage:\n%s\n", cmdtp->usage);
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return 1;
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return 1;
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@ -74,10 +80,10 @@ int do_bmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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}
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}
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U_BOOT_CMD(
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U_BOOT_CMD(
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bmp, 3, 1, do_bmp,
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bmp, 5, 1, do_bmp,
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"bmp - manipulate BMP image data\n",
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"bmp - manipulate BMP image data\n",
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"info <imageAddr> - display image info\n"
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"info <imageAddr> - display image info\n"
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"bmp display <imageAddr> - display image\n"
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"bmp display <imageAddr> [x y] - display image at x,y\n"
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);
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);
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/*
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/*
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* Return: None
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* Return: None
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*
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*
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*/
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*/
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static int bmp_display(ulong addr)
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static int bmp_display(ulong addr, int x, int y)
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{
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{
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extern int lcd_display_bitmap (ulong);
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#ifdef CONFIG_LCD
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extern int lcd_display_bitmap (ulong, int, int);
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return (lcd_display_bitmap (addr));
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return (lcd_display_bitmap (addr, x, y));
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#endif
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#ifdef CONFIG_VIDEO
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extern int video_display_bitmap (ulong, int, int);
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return (video_display_bitmap (addr, x, y));
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#endif
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}
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}
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#endif /* (CONFIG_COMMANDS & CFG_CMD_BMP) */
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#endif /* (CONFIG_COMMANDS & CFG_CMD_BMP) */
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void cpu_init_f (volatile immap_t * immr)
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void cpu_init_f (volatile immap_t * immr)
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{
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{
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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#if !defined(CONFIG_COGENT) /* done in start.S for the cogent */
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uint sccr;
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#endif
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volatile memctl8260_t *memctl = &immr->im_memctl;
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volatile memctl8260_t *memctl = &immr->im_memctl;
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extern void m8260_cpm_reset (void);
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extern void m8260_cpm_reset (void);
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#if !defined(CONFIG_COGENT) /* done in start.S for the cogent */
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#if !defined(CONFIG_COGENT) /* done in start.S for the cogent */
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/* System clock control register (9-8) */
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/* System clock control register (9-8) */
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immr->im_clkrst.car_sccr = CFG_SCCR;
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sccr = immr->im_clkrst.car_sccr &
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(SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK);
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immr->im_clkrst.car_sccr = sccr |
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(CFG_SCCR & ~(SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK) );
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#endif /* !CONFIG_COGENT */
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#endif /* !CONFIG_COGENT */
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/*
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/*
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@ -1205,7 +1205,7 @@ static void bitmap_plot (int x, int y)
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* Display the BMP file located at address bmp_image.
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* Display the BMP file located at address bmp_image.
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* Only uncompressed
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* Only uncompressed
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*/
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*/
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int lcd_display_bitmap(ulong bmp_image)
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int lcd_display_bitmap(ulong bmp_image, int x, int y)
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{
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{
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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volatile cpm8xx_t *cp = &(immr->im_cpm);
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volatile cpm8xx_t *cp = &(immr->im_cpm);
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}
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}
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padded_line = (width&0x3) ? ((width&~0x3)+4) : (width);
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padded_line = (width&0x3) ? ((width&~0x3)+4) : (width);
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if (width>panel_info.vl_col)
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if ((x + width)>panel_info.vl_col)
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width = panel_info.vl_col;
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width = panel_info.vl_col - x;
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if (height>panel_info.vl_row)
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if ((y + height)>panel_info.vl_row)
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height = panel_info.vl_row;
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height = panel_info.vl_row - y;
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bmap = (uchar *)bmp + le32_to_cpu (bmp->header.data_offset);
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bmap = (uchar *)bmp + le32_to_cpu (bmp->header.data_offset);
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fb = (uchar *)
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fb = (uchar *) (lcd_base +
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(lcd_base +
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(y + height - 1) * lcd_line_length + x);
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(((height>=panel_info.vl_row) ? panel_info.vl_row : height)-1)
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* lcd_line_length);
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for (i = 0; i < height; ++i) {
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for (i = 0; i < height; ++i) {
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WATCHDOG_RESET();
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WATCHDOG_RESET();
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for (j = 0; j < width ; j++)
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for (j = 0; j < width ; j++)
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@ -1317,7 +1315,7 @@ static void *lcd_logo (void)
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if ((s = getenv("splashimage")) != NULL) {
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if ((s = getenv("splashimage")) != NULL) {
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addr = simple_strtoul(s, NULL, 16);
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addr = simple_strtoul(s, NULL, 16);
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if (lcd_display_bitmap (addr) == 0) {
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if (lcd_display_bitmap (addr, 0, 0) == 0) {
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return ((void *)lcd_base);
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return ((void *)lcd_base);
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}
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}
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}
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}
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File diff suppressed because it is too large
Load Diff
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/*
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/*
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* Flash configuration
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* Flash configuration
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*/
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*/
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#define CFG_FLASH_BASE 0xff000000
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#define CFG_FLASH_BASE 0xFF000000
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#define CFG_FLASH_SIZE 0x01000000
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#define CFG_FLASH_SIZE 0x01000000
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#if !defined(CFG_LOWBOOT)
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#if !defined(CFG_LOWBOOT)
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#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x740000 + 0x800000)
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#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00740000 + 0x00800000)
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#else /* CFG_LOWBOOT */
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#else /* CFG_LOWBOOT */
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#if defined(CFG_LOWBOOT08)
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#if defined(CFG_LOWBOOT08)
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#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x30000 + 0x800000)
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#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000 + 0x00800000)
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#endif
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#endif
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#if defined(CFG_LOWBOOT16)
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#if defined(CFG_LOWBOOT16)
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#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x30000)
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#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000)
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#endif
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#endif
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#endif /* CFG_LOWBOOT */
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#endif /* CFG_LOWBOOT */
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#define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */
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#define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */
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@ -207,7 +207,7 @@
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/*
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/*
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* Memory map
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* Memory map
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*/
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*/
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#define CFG_MBAR 0xf0000000
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#define CFG_MBAR 0xF0000000
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_DEFAULT_MBAR 0x80000000
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#define CFG_DEFAULT_MBAR 0x80000000
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#ifdef CONFIG_MPC5200_DDR
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#ifdef CONFIG_MPC5200_DDR
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#define CFG_BOOTCS_START 0xff800000
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#define CFG_BOOTCS_START 0xFF800000
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#define CFG_BOOTCS_SIZE 0x00800000
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#define CFG_BOOTCS_SIZE 0x00800000
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#define CFG_BOOTCS_CFG 0x00047801
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#define CFG_BOOTCS_CFG 0x00047801
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#define CFG_CS1_START 0xff000000
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#define CFG_CS1_START 0xFF000000
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#define CFG_CS1_SIZE 0x00800000
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#define CFG_CS1_SIZE 0x00800000
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#define CFG_CS1_CFG 0x00047800
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#define CFG_CS1_CFG 0x00047800
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#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
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#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
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/* Offset for alternate registers */
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/* Offset for alternate registers */
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#define CFG_ATA_ALT_OFFSET (0x005c)
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#define CFG_ATA_ALT_OFFSET (0x005C)
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/* Interval between registers */
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/* Interval between registers */
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#define CFG_ATA_STRIDE 4
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#define CFG_ATA_STRIDE 4
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/*-----------------------------------------------------------------------
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/*-----------------------------------------------------------------------
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* SCCR - System Clock Control Register 9-8
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* SCCR - System Clock Control Register 9-8
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*/
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*/
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#define SCCR_PCI_MODE 0x00000100 /* PCI Mode */
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#define SCCR_PCI_MODCK 0x00000080 /* Value of PCI_MODCK pin */
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#define SCCR_PCIDF_MSK 0x00000078 /* PCI division factor */
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#define SCCR_PCIDF_SHIFT 3
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#define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */
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#define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */
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#define SCCR_DFBRG_MSK 0x00000003 /* Division factor of BRGCLK Mask */
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#define SCCR_DFBRG_MSK 0x00000003 /* Division factor of BRGCLK Mask */
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#define SCCR_DFBRG_SHIFT 0
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#define SCCR_DFBRG_SHIFT 0
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