[Blackfin]PATCH-1/2]: Remove obsolete blackfin port and add bf533 platform support
This commit is contained in:
parent
eb92f61355
commit
3f0606ad0b
|
@ -1,9 +1,9 @@
|
||||||
#
|
#
|
||||||
# U-boot - Makefile
|
# U-boot - Makefile
|
||||||
#
|
#
|
||||||
# Copyright (c) 2005 blackfin.uclinux.org
|
# Copyright (c) 2005-2007 Analog Device Inc.
|
||||||
#
|
#
|
||||||
# (C) Copyright 2000-2006
|
# (C) Copyright 2000-2004
|
||||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
#
|
#
|
||||||
# See file CREDITS for list of people who contributed to this
|
# See file CREDITS for list of people who contributed to this
|
||||||
|
@ -27,22 +27,22 @@
|
||||||
|
|
||||||
include $(TOPDIR)/config.mk
|
include $(TOPDIR)/config.mk
|
||||||
|
|
||||||
LIB = $(obj)lib$(BOARD).a
|
LIB = lib$(BOARD).a
|
||||||
|
|
||||||
COBJS = $(BOARD).o flash.o ezkit533.o
|
OBJS = $(BOARD).o flash.o
|
||||||
|
|
||||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
$(LIB): .depend $(OBJS) u-boot.lds
|
||||||
OBJS := $(addprefix $(obj),$(COBJS))
|
$(AR) cr $@ $(OBJS)
|
||||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
|
||||||
|
|
||||||
$(LIB): $(obj).depend $(OBJS)
|
u-boot.lds: u-boot.lds.S
|
||||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
$(CPP) $(CPPFLAGS) -P -Ubfin $^ > $@.tmp
|
||||||
|
mv -f $@.tmp $@
|
||||||
|
|
||||||
#########################################################################
|
#########################################################################
|
||||||
|
|
||||||
# defines $(obj).depend target
|
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
|
||||||
include $(SRCTREE)/rules.mk
|
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
|
||||||
|
|
||||||
sinclude $(obj).depend
|
sinclude .depend
|
||||||
|
|
||||||
#########################################################################
|
#########################################################################
|
|
@ -30,19 +30,23 @@
|
||||||
#include "psd4256.h"
|
#include "psd4256.h"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
|
||||||
|
|
||||||
int checkboard(void)
|
int checkboard(void)
|
||||||
{
|
{
|
||||||
|
#if (BFIN_CPU == ADSP_BF531)
|
||||||
|
printf("CPU: ADSP BF531 Rev.: 0.%d\n", *pCHIPID >> 28);
|
||||||
|
#elif (BFIN_CPU == ADSP_BF532)
|
||||||
|
printf("CPU: ADSP BF532 Rev.: 0.%d\n", *pCHIPID >> 28);
|
||||||
|
#else
|
||||||
printf("CPU: ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28);
|
printf("CPU: ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28);
|
||||||
|
#endif
|
||||||
printf("Board: ADI BF533 EZ-Kit Lite board\n");
|
printf("Board: ADI BF533 EZ-Kit Lite board\n");
|
||||||
printf(" Support: http://blackfin.uclinux.org/\n");
|
printf(" Support: http://blackfin.uclinux.org/\n");
|
||||||
printf(" Richard Klingler <richard@uclinux.net>\n");
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
long int initdram(int board_type)
|
long int initdram(int board_type)
|
||||||
{
|
{
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
#ifdef DEBUG
|
#ifdef DEBUG
|
||||||
int brate;
|
int brate;
|
||||||
char *tmp = getenv("baudrate");
|
char *tmp = getenv("baudrate");
|
||||||
|
@ -65,8 +69,12 @@ long int initdram(int board_type)
|
||||||
int misc_init_r(void)
|
int misc_init_r(void)
|
||||||
{
|
{
|
||||||
/* Set direction bits for Video en/decoder reset as output */
|
/* Set direction bits for Video en/decoder reset as output */
|
||||||
*(volatile unsigned char *)(CFG_FLASH1_BASE + PSD_PORTA_DIR) = PSDA_VDEC_RST | PSDA_VENC_RST;
|
*(volatile unsigned char *)(CFG_FLASH1_BASE + PSD_PORTA_DIR) =
|
||||||
|
PSDA_VDEC_RST | PSDA_VENC_RST;
|
||||||
/* Deactivate Video en/decoder reset lines */
|
/* Deactivate Video en/decoder reset lines */
|
||||||
*(volatile unsigned char *)(CFG_FLASH1_BASE + PSD_PORTA_DOUT) = PSDA_VDEC_RST | PSDA_VENC_RST;
|
*(volatile unsigned char *)(CFG_FLASH1_BASE + PSD_PORTA_DOUT) =
|
||||||
|
PSDA_VDEC_RST | PSDA_VENC_RST;
|
||||||
|
|
||||||
|
return 0;
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
|
@ -20,6 +20,6 @@
|
||||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
# MA 02111-1307 USA
|
# MA 02111-1307 USA
|
||||||
#
|
#
|
||||||
|
# TEXT_BASE should be defined as the MAX_SDRAM Address - 256k bytes
|
||||||
|
# 256k is defined as CFG_MONITOR_LEN in ./include/configs/<board>.h
|
||||||
TEXT_BASE = 0x01FC0000
|
TEXT_BASE = 0x01FC0000
|
||||||
PLATFORM_CPPFLAGS += -I$(TOPDIR)
|
|
|
@ -52,10 +52,6 @@
|
||||||
#define CFG_FLASH0_BASE 0x20000000
|
#define CFG_FLASH0_BASE 0x20000000
|
||||||
#define RESET_VAL 0xF0
|
#define RESET_VAL 0xF0
|
||||||
|
|
||||||
|
|
||||||
asm("#define FLASH_START_L 0x0000");
|
|
||||||
asm("#define FLASH_START_H 0x2000");
|
|
||||||
|
|
||||||
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
|
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
|
||||||
|
|
||||||
int get_codes(void);
|
int get_codes(void);
|
|
@ -33,8 +33,7 @@ void flash_reset(void)
|
||||||
reset_flash();
|
reset_flash();
|
||||||
}
|
}
|
||||||
|
|
||||||
unsigned long flash_get_size(ulong baseaddr, flash_info_t * info,
|
unsigned long flash_get_size(ulong baseaddr, flash_info_t * info, int bank_flag)
|
||||||
int bank_flag)
|
|
||||||
{
|
{
|
||||||
int id = 0, i = 0;
|
int id = 0, i = 0;
|
||||||
static int FlagDev = 1;
|
static int FlagDev = 1;
|
||||||
|
@ -103,7 +102,8 @@ unsigned long flash_init(void)
|
||||||
size_b0, size_b0 >> 20);
|
size_b0, size_b0 >> 20);
|
||||||
}
|
}
|
||||||
|
|
||||||
(void)flash_protect(FLAG_PROTECT_SET,CFG_FLASH0_BASE,(flash_info[0].start[2] - 1),&flash_info[0]);
|
(void)flash_protect(FLAG_PROTECT_SET, CFG_FLASH0_BASE,
|
||||||
|
(flash_info[0].start[2] - 1), &flash_info[0]);
|
||||||
|
|
||||||
return (size_b0 + size_b1 + size_b2);
|
return (size_b0 + size_b1 + size_b2);
|
||||||
}
|
}
|
||||||
|
@ -122,15 +122,14 @@ void flash_print_info(flash_info_t * info)
|
||||||
printf("ST Microelectronics ");
|
printf("ST Microelectronics ");
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
printf("Unknown Vendor ");
|
printf("Unknown Vendor: (0x%08X) ", info->flash_id);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
for (i = 0; i < info->sector_count; ++i) {
|
for (i = 0; i < info->sector_count; ++i) {
|
||||||
if ((i % 5) == 0)
|
if ((i % 5) == 0)
|
||||||
printf("\n ");
|
printf("\n ");
|
||||||
printf(" %08lX%s",
|
printf(" %08lX%s",
|
||||||
info->start[i],
|
info->start[i], info->protect[i] ? " (RO)" : " ");
|
||||||
info->protect[i] ? " (RO)" : " ");
|
|
||||||
}
|
}
|
||||||
printf("\n");
|
printf("\n");
|
||||||
return;
|
return;
|
||||||
|
@ -148,7 +147,8 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
|
||||||
}
|
}
|
||||||
|
|
||||||
if (prot)
|
if (prot)
|
||||||
printf ("- Warning: %d protected sectors will not be erased!\n", prot);
|
printf("- Warning: %d protected sectors will not be erased!\n",
|
||||||
|
prot);
|
||||||
else
|
else
|
||||||
printf("\n");
|
printf("\n");
|
||||||
|
|
||||||
|
@ -184,7 +184,6 @@ int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
|
||||||
return FLASH_SUCCESS;
|
return FLASH_SUCCESS;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
int write_data(long lStart, long lCount, long lStride, int *pnData)
|
int write_data(long lStart, long lCount, long lStride, int *pnData)
|
||||||
{
|
{
|
||||||
long i = 0;
|
long i = 0;
|
||||||
|
@ -201,13 +200,16 @@ int write_data(long lStart, long lCount, long lStride, int *pnData)
|
||||||
j++, ulOffset += (lStride * 2)) {
|
j++, ulOffset += (lStride * 2)) {
|
||||||
if ((ulOffset >= INVALIDLOCNSTART)
|
if ((ulOffset >= INVALIDLOCNSTART)
|
||||||
&& (ulOffset < INVALIDLOCNEND)) {
|
&& (ulOffset < INVALIDLOCNEND)) {
|
||||||
printf("Invalid locations, Try writing to another location \n");
|
printf
|
||||||
|
("Invalid locations, Try writing to another location \n");
|
||||||
return FLASH_FAIL;
|
return FLASH_FAIL;
|
||||||
}
|
}
|
||||||
get_sector_number(ulOffset, &nSector);
|
get_sector_number(ulOffset, &nSector);
|
||||||
read_flash(ulOffset, &d);
|
read_flash(ulOffset, &d);
|
||||||
if (d != 0xffff) {
|
if (d != 0xffff) {
|
||||||
printf("Flash not erased at offset 0x%x Please erase to reprogram \n",ulOffset);
|
printf
|
||||||
|
("Flash not erased at offset 0x%x Please erase to reprogram \n",
|
||||||
|
ulOffset);
|
||||||
return FLASH_FAIL;
|
return FLASH_FAIL;
|
||||||
}
|
}
|
||||||
unlock_flash(ulOffset);
|
unlock_flash(ulOffset);
|
||||||
|
@ -225,7 +227,8 @@ int write_data(long lStart, long lCount, long lStride, int *pnData)
|
||||||
get_sector_number(ulOffset, &nSector);
|
get_sector_number(ulOffset, &nSector);
|
||||||
read_flash(ulOffset, &d);
|
read_flash(ulOffset, &d);
|
||||||
if (d != 0xffff) {
|
if (d != 0xffff) {
|
||||||
printf("Flash already programmed. Please erase to reprogram \n");
|
printf
|
||||||
|
("Flash already programmed. Please erase to reprogram \n");
|
||||||
printf("uloffset = 0x%x \t d = 0x%x\n", ulOffset, d);
|
printf("uloffset = 0x%x \t d = 0x%x\n", ulOffset, d);
|
||||||
return FLASH_FAIL;
|
return FLASH_FAIL;
|
||||||
}
|
}
|
||||||
|
@ -279,9 +282,9 @@ int write_flash(long nOffset, int nValue)
|
||||||
long addr;
|
long addr;
|
||||||
|
|
||||||
addr = (CFG_FLASH_BASE + nOffset);
|
addr = (CFG_FLASH_BASE + nOffset);
|
||||||
asm("ssync;");
|
__builtin_bfin_ssync();
|
||||||
*(unsigned volatile short *)addr = nValue;
|
*(unsigned volatile short *)addr = nValue;
|
||||||
asm("ssync;");
|
__builtin_bfin_ssync();
|
||||||
if (poll_toggle_bit(nOffset) < 0)
|
if (poll_toggle_bit(nOffset) < 0)
|
||||||
return FLASH_FAIL;
|
return FLASH_FAIL;
|
||||||
return FLASH_SUCCESS;
|
return FLASH_SUCCESS;
|
||||||
|
@ -294,9 +297,9 @@ int read_flash(long nOffset, int *pnValue)
|
||||||
|
|
||||||
if (nOffset != 0x2)
|
if (nOffset != 0x2)
|
||||||
reset_flash();
|
reset_flash();
|
||||||
asm("ssync;");
|
__builtin_bfin_ssync();
|
||||||
nValue = *(volatile unsigned short *)addr;
|
nValue = *(volatile unsigned short *)addr;
|
||||||
asm("ssync;");
|
__builtin_bfin_ssync();
|
||||||
*pnValue = nValue;
|
*pnValue = nValue;
|
||||||
return TRUE;
|
return TRUE;
|
||||||
}
|
}
|
||||||
|
@ -305,7 +308,8 @@ int poll_toggle_bit(long lOffset)
|
||||||
{
|
{
|
||||||
unsigned int u1, u2;
|
unsigned int u1, u2;
|
||||||
unsigned long timeout = 0xFFFFFFFF;
|
unsigned long timeout = 0xFFFFFFFF;
|
||||||
volatile unsigned long *FB = (volatile unsigned long *)(0x20000000 + lOffset);
|
volatile unsigned long *FB =
|
||||||
|
(volatile unsigned long *)(0x20000000 + lOffset);
|
||||||
while (1) {
|
while (1) {
|
||||||
if (timeout < 0)
|
if (timeout < 0)
|
||||||
break;
|
break;
|
||||||
|
@ -325,7 +329,8 @@ int poll_toggle_bit(long lOffset)
|
||||||
timeout--;
|
timeout--;
|
||||||
}
|
}
|
||||||
printf("Time out occured \n");
|
printf("Time out occured \n");
|
||||||
if(timeout <0) return FLASH_FAIL;
|
if (timeout < 0)
|
||||||
|
return FLASH_FAIL;
|
||||||
}
|
}
|
||||||
|
|
||||||
void reset_flash(void)
|
void reset_flash(void)
|
|
@ -1,7 +1,7 @@
|
||||||
/*
|
/*
|
||||||
* U-boot - u-boot.lds
|
* U-boot - u-boot.lds.S
|
||||||
*
|
*
|
||||||
* Copyright (c) 2005 blackfin.uclinux.org
|
* Copyright (c) 2005-2007 Analog Device Inc.
|
||||||
*
|
*
|
||||||
* (C) Copyright 2000-2004
|
* (C) Copyright 2000-2004
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
|
@ -25,6 +25,8 @@
|
||||||
* MA 02111-1307 USA
|
* MA 02111-1307 USA
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#include <config.h>
|
||||||
|
|
||||||
OUTPUT_ARCH(bfin)
|
OUTPUT_ARCH(bfin)
|
||||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
|
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
|
||||||
/* Do we need any of these for elf?
|
/* Do we need any of these for elf?
|
||||||
|
@ -55,6 +57,7 @@ SECTIONS
|
||||||
.rela.plt : { *(.rela.plt) }
|
.rela.plt : { *(.rela.plt) }
|
||||||
.init : { *(.init) }
|
.init : { *(.init) }
|
||||||
.plt : { *(.plt) }
|
.plt : { *(.plt) }
|
||||||
|
. = CFG_MONITOR_BASE;
|
||||||
.text :
|
.text :
|
||||||
{
|
{
|
||||||
/* WARNING - the following is hand-optimized to fit within */
|
/* WARNING - the following is hand-optimized to fit within */
|
||||||
|
@ -68,10 +71,11 @@ SECTIONS
|
||||||
cpu/bf533/interrupt.o (.text)
|
cpu/bf533/interrupt.o (.text)
|
||||||
cpu/bf533/serial.o (.text)
|
cpu/bf533/serial.o (.text)
|
||||||
common/dlmalloc.o (.text)
|
common/dlmalloc.o (.text)
|
||||||
lib_generic/vsprintf.o (.text)
|
/* lib_blackfin/bf533_string.o (.text) */
|
||||||
|
/* lib_generic/vsprintf.o (.text) */
|
||||||
lib_generic/crc32.o (.text)
|
lib_generic/crc32.o (.text)
|
||||||
lib_generic/zlib.o (.text)
|
lib_generic/zlib.o (.text)
|
||||||
board/ezkit533/ezkit533.o (.text)
|
board/bf533-ezkit/bf533-ezkit.o (.text)
|
||||||
|
|
||||||
. = DEFINED(env_offset) ? env_offset : .;
|
. = DEFINED(env_offset) ? env_offset : .;
|
||||||
common/environment.o (.text)
|
common/environment.o (.text)
|
||||||
|
@ -119,9 +123,9 @@ SECTIONS
|
||||||
_edata = .;
|
_edata = .;
|
||||||
PROVIDE (edata = .);
|
PROVIDE (edata = .);
|
||||||
|
|
||||||
__u_boot_cmd_start = .;
|
___u_boot_cmd_start = .;
|
||||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||||
__u_boot_cmd_end = .;
|
___u_boot_cmd_end = .;
|
||||||
|
|
||||||
|
|
||||||
__start___ex_table = .;
|
__start___ex_table = .;
|
||||||
|
@ -146,3 +150,4 @@ SECTIONS
|
||||||
_end = . ;
|
_end = . ;
|
||||||
PROVIDE (end = .);
|
PROVIDE (end = .);
|
||||||
}
|
}
|
||||||
|
|
|
@ -0,0 +1,48 @@
|
||||||
|
#
|
||||||
|
# U-boot - Makefile
|
||||||
|
#
|
||||||
|
# Copyright (c) 2005-2007 Analog Device Inc.
|
||||||
|
#
|
||||||
|
# (C) Copyright 2000-2004
|
||||||
|
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
|
#
|
||||||
|
# See file CREDITS for list of people who contributed to this
|
||||||
|
# project.
|
||||||
|
#
|
||||||
|
# This program is free software; you can redistribute it and/or
|
||||||
|
# modify it under the terms of the GNU General Public License as
|
||||||
|
# published by the Free Software Foundation; either version 2 of
|
||||||
|
# the License, or (at your option) any later version.
|
||||||
|
#
|
||||||
|
# This program is distributed in the hope that it will be useful,
|
||||||
|
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
# GNU General Public License for more details.
|
||||||
|
#
|
||||||
|
# You should have received a copy of the GNU General Public License
|
||||||
|
# along with this program; if not, write to the Free Software
|
||||||
|
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
# MA 02111-1307 USA
|
||||||
|
#
|
||||||
|
|
||||||
|
include $(TOPDIR)/config.mk
|
||||||
|
|
||||||
|
LIB = lib$(BOARD).a
|
||||||
|
|
||||||
|
OBJS = $(BOARD).o spi.o
|
||||||
|
|
||||||
|
$(LIB): .depend $(OBJS) u-boot.lds
|
||||||
|
$(AR) cr $@ $(OBJS)
|
||||||
|
|
||||||
|
u-boot.lds: u-boot.lds.S
|
||||||
|
$(CPP) $(CPPFLAGS) -P -Ubfin $^ > $@.tmp
|
||||||
|
mv -f $@.tmp $@
|
||||||
|
|
||||||
|
#########################################################################
|
||||||
|
|
||||||
|
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
|
||||||
|
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
|
||||||
|
|
||||||
|
sinclude .depend
|
||||||
|
|
||||||
|
#########################################################################
|
|
@ -27,9 +27,7 @@
|
||||||
|
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <asm/mem_init.h>
|
#include <asm/mem_init.h>
|
||||||
#include "stamp.h"
|
#include "bf533-stamp.h"
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
|
||||||
|
|
||||||
#define STATUS_LED_OFF 0
|
#define STATUS_LED_OFF 0
|
||||||
#define STATUS_LED_ON 1
|
#define STATUS_LED_ON 1
|
||||||
|
@ -42,24 +40,27 @@ DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
int checkboard(void)
|
int checkboard(void)
|
||||||
{
|
{
|
||||||
|
#if (BFIN_CPU == ADSP_BF531)
|
||||||
|
printf("CPU: ADSP BF531 Rev.: 0.%d\n", *pCHIPID >> 28);
|
||||||
|
#elif (BFIN_CPU == ADSP_BF532)
|
||||||
|
printf("CPU: ADSP BF532 Rev.: 0.%d\n", *pCHIPID >> 28);
|
||||||
|
#else
|
||||||
printf("CPU: ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28);
|
printf("CPU: ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28);
|
||||||
|
#endif
|
||||||
printf("Board: ADI BF533 Stamp board\n");
|
printf("Board: ADI BF533 Stamp board\n");
|
||||||
printf(" Support: http://blackfin.uclinux.org/\n");
|
printf(" Support: http://blackfin.uclinux.org/\n");
|
||||||
printf (" Richard Klingler <richard@uclinux.net>\n");
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
long int initdram(int board_type)
|
long int initdram(int board_type)
|
||||||
{
|
{
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
#ifdef DEBUG
|
#ifdef DEBUG
|
||||||
printf("SDRAM attributes:\n");
|
printf("SDRAM attributes:\n");
|
||||||
printf (" tRCD:%d Cycles; tRP:%d Cycles; tRAS:%d Cycles; tWR:%d Cycles; "
|
printf
|
||||||
"CAS Latency:%d cycles\n",
|
(" tRCD:%d Cycles; tRP:%d Cycles; tRAS:%d Cycles; tWR:%d Cycles; "
|
||||||
(SDRAM_tRCD >> 15),
|
"CAS Latency:%d cycles\n", (SDRAM_tRCD >> 15), (SDRAM_tRP >> 11),
|
||||||
(SDRAM_tRP >> 11),
|
(SDRAM_tRAS >> 6), (SDRAM_tWR >> 19), (SDRAM_CL >> 2));
|
||||||
(SDRAM_tRAS >> 6),
|
|
||||||
(SDRAM_tWR >> 19),
|
|
||||||
(SDRAM_CL >> 2));
|
|
||||||
printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
|
printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
|
||||||
printf("Bank size = %d MB\n", 128);
|
printf("Bank size = %d MB\n", 128);
|
||||||
#endif
|
#endif
|
||||||
|
@ -73,9 +74,9 @@ void swap_to (int device_id)
|
||||||
|
|
||||||
if (device_id == ETHERNET) {
|
if (device_id == ETHERNET) {
|
||||||
*pFIO_DIR = PF0;
|
*pFIO_DIR = PF0;
|
||||||
asm ("ssync;");
|
__builtin_bfin_ssync();
|
||||||
*pFIO_FLAG_S = PF0;
|
*pFIO_FLAG_S = PF0;
|
||||||
asm ("ssync;");
|
__builtin_bfin_ssync();
|
||||||
} else if (device_id == FLASH) {
|
} else if (device_id == FLASH) {
|
||||||
*pFIO_DIR = (PF4 | PF3 | PF2 | PF1 | PF0);
|
*pFIO_DIR = (PF4 | PF3 | PF2 | PF1 | PF0);
|
||||||
*pFIO_FLAG_S = (PF4 | PF3 | PF2);
|
*pFIO_FLAG_S = (PF4 | PF3 | PF2);
|
||||||
|
@ -85,7 +86,7 @@ void swap_to (int device_id)
|
||||||
*pFIO_EDGE = (PF8 | PF7 | PF6 | PF5);
|
*pFIO_EDGE = (PF8 | PF7 | PF6 | PF5);
|
||||||
*pFIO_INEN = (PF8 | PF7 | PF6 | PF5);
|
*pFIO_INEN = (PF8 | PF7 | PF6 | PF5);
|
||||||
*pFIO_FLAG_D = (PF4 | PF3 | PF2);
|
*pFIO_FLAG_D = (PF4 | PF3 | PF2);
|
||||||
asm ("ssync;");
|
__builtin_bfin_ssync();
|
||||||
} else {
|
} else {
|
||||||
printf("Unknown bank to switch\n");
|
printf("Unknown bank to switch\n");
|
||||||
}
|
}
|
||||||
|
@ -115,7 +116,6 @@ int misc_init_r (void)
|
||||||
*pFIO_EDGE = FIO_EDGE_BITS;
|
*pFIO_EDGE = FIO_EDGE_BITS;
|
||||||
*pFIO_POLAR = FIO_POLAR_BITS;
|
*pFIO_POLAR = FIO_POLAR_BITS;
|
||||||
|
|
||||||
|
|
||||||
if (cf_stat) {
|
if (cf_stat) {
|
||||||
printf("Booting from COMPACT flash\n");
|
printf("Booting from COMPACT flash\n");
|
||||||
|
|
||||||
|
@ -139,7 +139,7 @@ int misc_init_r (void)
|
||||||
printf("Booting from FLASH\n");
|
printf("Booting from FLASH\n");
|
||||||
}
|
}
|
||||||
|
|
||||||
return 1;
|
return 0;
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
@ -153,15 +153,15 @@ void cf_outb (unsigned char val, volatile unsigned char *addr)
|
||||||
*/
|
*/
|
||||||
*pFIO_FLAG_S = CF_PF0;
|
*pFIO_FLAG_S = CF_PF0;
|
||||||
*pFIO_FLAG_C = CF_PF1;
|
*pFIO_FLAG_C = CF_PF1;
|
||||||
asm ("ssync;");
|
__builtin_bfin_ssync();
|
||||||
|
|
||||||
*(addr) = val;
|
*(addr) = val;
|
||||||
asm ("ssync;");
|
__builtin_bfin_ssync();
|
||||||
|
|
||||||
/* Setback PF1 PF0 to 0 0 to address external
|
/* Setback PF1 PF0 to 0 0 to address external
|
||||||
* memory banks */
|
* memory banks */
|
||||||
*(volatile unsigned short *)pFIO_FLAG_C = CF_PF1_PF0;
|
*(volatile unsigned short *)pFIO_FLAG_C = CF_PF1_PF0;
|
||||||
asm ("ssync;");
|
__builtin_bfin_ssync();
|
||||||
}
|
}
|
||||||
|
|
||||||
unsigned char cf_inb(volatile unsigned char *addr)
|
unsigned char cf_inb(volatile unsigned char *addr)
|
||||||
|
@ -170,13 +170,13 @@ unsigned char cf_inb (volatile unsigned char *addr)
|
||||||
|
|
||||||
*pFIO_FLAG_S = CF_PF0;
|
*pFIO_FLAG_S = CF_PF0;
|
||||||
*pFIO_FLAG_C = CF_PF1;
|
*pFIO_FLAG_C = CF_PF1;
|
||||||
asm ("ssync;");
|
__builtin_bfin_ssync();
|
||||||
|
|
||||||
c = *(addr);
|
c = *(addr);
|
||||||
asm ("ssync;");
|
__builtin_bfin_ssync();
|
||||||
|
|
||||||
*pFIO_FLAG_C = CF_PF1_PF0;
|
*pFIO_FLAG_C = CF_PF1_PF0;
|
||||||
asm ("ssync;");
|
__builtin_bfin_ssync();
|
||||||
|
|
||||||
return c;
|
return c;
|
||||||
}
|
}
|
||||||
|
@ -187,15 +187,15 @@ void cf_insw (unsigned short *sect_buf, unsigned short *addr, int words)
|
||||||
|
|
||||||
*pFIO_FLAG_S = CF_PF0;
|
*pFIO_FLAG_S = CF_PF0;
|
||||||
*pFIO_FLAG_C = CF_PF1;
|
*pFIO_FLAG_C = CF_PF1;
|
||||||
asm ("ssync;");
|
__builtin_bfin_ssync();
|
||||||
|
|
||||||
for (i = 0; i < words; i++) {
|
for (i = 0; i < words; i++) {
|
||||||
*(sect_buf + i) = *(addr);
|
*(sect_buf + i) = *(addr);
|
||||||
asm ("ssync;");
|
__builtin_bfin_ssync();
|
||||||
}
|
}
|
||||||
|
|
||||||
*pFIO_FLAG_C = CF_PF1_PF0;
|
*pFIO_FLAG_C = CF_PF1_PF0;
|
||||||
asm ("ssync;");
|
__builtin_bfin_ssync();
|
||||||
}
|
}
|
||||||
|
|
||||||
void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
|
void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
|
||||||
|
@ -204,15 +204,15 @@ void cf_outsw (unsigned short *addr, unsigned short *sect_buf, int words)
|
||||||
|
|
||||||
*pFIO_FLAG_S = CF_PF0;
|
*pFIO_FLAG_S = CF_PF0;
|
||||||
*pFIO_FLAG_C = CF_PF1;
|
*pFIO_FLAG_C = CF_PF1;
|
||||||
asm ("ssync;");
|
__builtin_bfin_ssync();
|
||||||
|
|
||||||
for (i = 0; i < words; i++) {
|
for (i = 0; i < words; i++) {
|
||||||
*(addr) = *(sect_buf + i);
|
*(addr) = *(sect_buf + i);
|
||||||
asm ("ssync;");
|
__builtin_bfin_ssync();
|
||||||
}
|
}
|
||||||
|
|
||||||
*pFIO_FLAG_C = CF_PF1_PF0;
|
*pFIO_FLAG_C = CF_PF1_PF0;
|
||||||
asm ("ssync;");
|
__builtin_bfin_ssync();
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
@ -233,7 +233,7 @@ void stamp_led_set (int LED1, int LED2, int LED3)
|
||||||
*pFIO_FLAG_S = PF4;
|
*pFIO_FLAG_S = PF4;
|
||||||
else
|
else
|
||||||
*pFIO_FLAG_C = PF4;
|
*pFIO_FLAG_C = PF4;
|
||||||
asm ("ssync;");
|
__builtin_bfin_ssync();
|
||||||
}
|
}
|
||||||
|
|
||||||
void show_boot_progress(int status)
|
void show_boot_progress(int status)
|
||||||
|
@ -266,8 +266,7 @@ void show_boot_progress (int status)
|
||||||
case 13:
|
case 13:
|
||||||
case 14:
|
case 14:
|
||||||
case 15:
|
case 15:
|
||||||
stamp_led_set (STATUS_LED_OFF, STATUS_LED_OFF,
|
stamp_led_set(STATUS_LED_OFF, STATUS_LED_OFF, STATUS_LED_OFF);
|
||||||
STATUS_LED_OFF);
|
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
stamp_led_set(STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_ON);
|
stamp_led_set(STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_ON);
|
|
@ -36,7 +36,6 @@ extern volatile unsigned long *amgctl;
|
||||||
|
|
||||||
extern unsigned long pll_div_fact;
|
extern unsigned long pll_div_fact;
|
||||||
extern void serial_setbrg(void);
|
extern void serial_setbrg(void);
|
||||||
extern void pll_set(int vco, int crystal_frq, int pll_div);
|
|
||||||
|
|
||||||
/* Definitions used in Compact Flash Boot support */
|
/* Definitions used in Compact Flash Boot support */
|
||||||
#define FIO_EDGE_CF_BITS 0x0000
|
#define FIO_EDGE_CF_BITS 0x0000
|
|
@ -20,6 +20,6 @@
|
||||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
# MA 02111-1307 USA
|
# MA 02111-1307 USA
|
||||||
#
|
#
|
||||||
|
# TEXT_BASE should be defined as the MAX_SDRAM Address - 256k bytes
|
||||||
|
# 256k is defined as CFG_MONITOR_LEN in ./include/configs/<board>.h
|
||||||
TEXT_BASE = 0x07FC0000
|
TEXT_BASE = 0x07FC0000
|
||||||
PLATFORM_CPPFLAGS += -I$(TOPDIR)
|
|
|
@ -0,0 +1,472 @@
|
||||||
|
/****************************************************************************
|
||||||
|
* SPI flash driver for M25P64
|
||||||
|
****************************************************************************/
|
||||||
|
#include <common.h>
|
||||||
|
#include <linux/ctype.h>
|
||||||
|
|
||||||
|
#if defined(CONFIG_SPI)
|
||||||
|
|
||||||
|
/*Application definitions */
|
||||||
|
|
||||||
|
#define NUM_SECTORS 128 /* number of sectors */
|
||||||
|
#define SECTOR_SIZE 0x10000
|
||||||
|
#define NOP_NUM 1000
|
||||||
|
|
||||||
|
#define COMMON_SPI_SETTINGS (SPE|MSTR|CPHA|CPOL) /*Settings to the SPI_CTL */
|
||||||
|
#define TIMOD01 (0x01) /*stes the SPI to work with core instructions */
|
||||||
|
|
||||||
|
/*Flash commands */
|
||||||
|
#define SPI_WREN (0x06) /*Set Write Enable Latch */
|
||||||
|
#define SPI_WRDI (0x04) /*Reset Write Enable Latch */
|
||||||
|
#define SPI_RDSR (0x05) /*Read Status Register */
|
||||||
|
#define SPI_WRSR (0x01) /*Write Status Register */
|
||||||
|
#define SPI_READ (0x03) /*Read data from memory */
|
||||||
|
#define SPI_PP (0x02) /*Program Data into memory */
|
||||||
|
#define SPI_SE (0xD8) /*Erase one sector in memory */
|
||||||
|
#define SPI_BE (0xC7) /*Erase all memory */
|
||||||
|
#define WIP (0x1) /*Check the write in progress bit of the SPI status register */
|
||||||
|
#define WEL (0x2) /*Check the write enable bit of the SPI status register */
|
||||||
|
|
||||||
|
#define TIMEOUT 350000000
|
||||||
|
|
||||||
|
typedef enum {
|
||||||
|
NO_ERR,
|
||||||
|
POLL_TIMEOUT,
|
||||||
|
INVALID_SECTOR,
|
||||||
|
INVALID_BLOCK,
|
||||||
|
} ERROR_CODE;
|
||||||
|
|
||||||
|
void spi_init_f(void);
|
||||||
|
void spi_init_r(void);
|
||||||
|
ssize_t spi_read(uchar *, int, uchar *, int);
|
||||||
|
ssize_t spi_write(uchar *, int, uchar *, int);
|
||||||
|
|
||||||
|
char ReadStatusRegister(void);
|
||||||
|
void Wait_For_SPIF(void);
|
||||||
|
void SetupSPI(const int spi_setting);
|
||||||
|
void SPI_OFF(void);
|
||||||
|
void SendSingleCommand(const int iCommand);
|
||||||
|
|
||||||
|
ERROR_CODE GetSectorNumber(unsigned long ulOffset, int *pnSector);
|
||||||
|
ERROR_CODE EraseBlock(int nBlock);
|
||||||
|
ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData);
|
||||||
|
ERROR_CODE WriteData(unsigned long ulStart, long lCount, int *pnData);
|
||||||
|
ERROR_CODE Wait_For_Status(char Statusbit);
|
||||||
|
ERROR_CODE Wait_For_WEL(void);
|
||||||
|
|
||||||
|
/* -------------------
|
||||||
|
* Variables
|
||||||
|
* ------------------- */
|
||||||
|
|
||||||
|
/* **************************************************************************
|
||||||
|
*
|
||||||
|
* Function: spi_init_f
|
||||||
|
*
|
||||||
|
* Description: Init SPI-Controller (ROM part)
|
||||||
|
*
|
||||||
|
* return: ---
|
||||||
|
*
|
||||||
|
* *********************************************************************** */
|
||||||
|
void spi_init_f(void)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
/* **************************************************************************
|
||||||
|
*
|
||||||
|
* Function: spi_init_r
|
||||||
|
*
|
||||||
|
* Description: Init SPI-Controller (RAM part) -
|
||||||
|
* The malloc engine is ready and we can move our buffers to
|
||||||
|
* normal RAM
|
||||||
|
*
|
||||||
|
* return: ---
|
||||||
|
*
|
||||||
|
* *********************************************************************** */
|
||||||
|
void spi_init_r(void)
|
||||||
|
{
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
/****************************************************************************
|
||||||
|
* Function: spi_write
|
||||||
|
**************************************************************************** */
|
||||||
|
ssize_t spi_write(uchar * addr, int alen, uchar * buffer, int len)
|
||||||
|
{
|
||||||
|
unsigned long offset;
|
||||||
|
int start_block, end_block;
|
||||||
|
int start_byte, end_byte;
|
||||||
|
ERROR_CODE result = NO_ERR;
|
||||||
|
uchar temp[SECTOR_SIZE];
|
||||||
|
int i, num;
|
||||||
|
|
||||||
|
offset = addr[0] << 16 | addr[1] << 8 | addr[2];
|
||||||
|
/* Get the start block number */
|
||||||
|
result = GetSectorNumber(offset, &start_block);
|
||||||
|
if (result == INVALID_SECTOR) {
|
||||||
|
printf("Invalid sector! ");
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
/* Get the end block number */
|
||||||
|
result = GetSectorNumber(offset + len - 1, &end_block);
|
||||||
|
if (result == INVALID_SECTOR) {
|
||||||
|
printf("Invalid sector! ");
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
for (num = start_block; num <= end_block; num++) {
|
||||||
|
ReadData(num * SECTOR_SIZE, SECTOR_SIZE, (int *)temp);
|
||||||
|
start_byte = num * SECTOR_SIZE;
|
||||||
|
end_byte = (num + 1) * SECTOR_SIZE - 1;
|
||||||
|
if (start_byte < offset)
|
||||||
|
start_byte = offset;
|
||||||
|
if (end_byte > (offset + len))
|
||||||
|
end_byte = (offset + len - 1);
|
||||||
|
for (i = start_byte; i <= end_byte; i++)
|
||||||
|
temp[i - num * SECTOR_SIZE] = buffer[i - offset];
|
||||||
|
EraseBlock(num);
|
||||||
|
result = WriteData(num * SECTOR_SIZE, SECTOR_SIZE, (int *)temp);
|
||||||
|
if (result != NO_ERR)
|
||||||
|
return 0;
|
||||||
|
printf(".");
|
||||||
|
}
|
||||||
|
return len;
|
||||||
|
}
|
||||||
|
|
||||||
|
/****************************************************************************
|
||||||
|
* Function: spi_read
|
||||||
|
**************************************************************************** */
|
||||||
|
ssize_t spi_read(uchar * addr, int alen, uchar * buffer, int len)
|
||||||
|
{
|
||||||
|
unsigned long offset;
|
||||||
|
offset = addr[0] << 16 | addr[1] << 8 | addr[2];
|
||||||
|
ReadData(offset, len, (int *)buffer);
|
||||||
|
return len;
|
||||||
|
}
|
||||||
|
|
||||||
|
void SendSingleCommand(const int iCommand)
|
||||||
|
{
|
||||||
|
unsigned short dummy;
|
||||||
|
|
||||||
|
/*turns on the SPI in single write mode */
|
||||||
|
SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
|
||||||
|
|
||||||
|
/*sends the actual command to the SPI TX register */
|
||||||
|
*pSPI_TDBR = iCommand;
|
||||||
|
__builtin_bfin_ssync();
|
||||||
|
|
||||||
|
/*The SPI status register will be polled to check the SPIF bit */
|
||||||
|
Wait_For_SPIF();
|
||||||
|
|
||||||
|
dummy = *pSPI_RDBR;
|
||||||
|
|
||||||
|
/*The SPI will be turned off */
|
||||||
|
SPI_OFF();
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
void SetupSPI(const int spi_setting)
|
||||||
|
{
|
||||||
|
|
||||||
|
if (icache_status() || dcache_status())
|
||||||
|
udelay(CONFIG_CCLK_HZ / 50000000);
|
||||||
|
/*sets up the PF2 to be the slave select of the SPI */
|
||||||
|
*pSPI_FLG = 0xFB04;
|
||||||
|
*pSPI_BAUD = CONFIG_SPI_BAUD;
|
||||||
|
*pSPI_CTL = spi_setting;
|
||||||
|
__builtin_bfin_ssync();
|
||||||
|
}
|
||||||
|
|
||||||
|
void SPI_OFF(void)
|
||||||
|
{
|
||||||
|
|
||||||
|
*pSPI_CTL = 0x0400; /* disable SPI */
|
||||||
|
*pSPI_FLG = 0;
|
||||||
|
*pSPI_BAUD = 0;
|
||||||
|
__builtin_bfin_ssync();
|
||||||
|
udelay(CONFIG_CCLK_HZ / 50000000);
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
void Wait_For_SPIF(void)
|
||||||
|
{
|
||||||
|
unsigned short dummyread;
|
||||||
|
while ((*pSPI_STAT & TXS)) ;
|
||||||
|
while (!(*pSPI_STAT & SPIF)) ;
|
||||||
|
while (!(*pSPI_STAT & RXS)) ;
|
||||||
|
dummyread = *pSPI_RDBR; /* Read dummy to empty the receive register */
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
ERROR_CODE Wait_For_WEL(void)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
char status_register = 0;
|
||||||
|
ERROR_CODE ErrorCode = NO_ERR; /* tells us if there was an error erasing flash */
|
||||||
|
|
||||||
|
for (i = 0; i < TIMEOUT; i++) {
|
||||||
|
status_register = ReadStatusRegister();
|
||||||
|
if ((status_register & WEL)) {
|
||||||
|
ErrorCode = NO_ERR; /* tells us if there was an error erasing flash */
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
ErrorCode = POLL_TIMEOUT; /* Time out error */
|
||||||
|
};
|
||||||
|
|
||||||
|
return ErrorCode;
|
||||||
|
}
|
||||||
|
|
||||||
|
ERROR_CODE Wait_For_Status(char Statusbit)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
char status_register = 0xFF;
|
||||||
|
ERROR_CODE ErrorCode = NO_ERR; /* tells us if there was an error erasing flash */
|
||||||
|
|
||||||
|
for (i = 0; i < TIMEOUT; i++) {
|
||||||
|
status_register = ReadStatusRegister();
|
||||||
|
if (!(status_register & Statusbit)) {
|
||||||
|
ErrorCode = NO_ERR; /* tells us if there was an error erasing flash */
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
ErrorCode = POLL_TIMEOUT; /* Time out error */
|
||||||
|
};
|
||||||
|
|
||||||
|
return ErrorCode;
|
||||||
|
}
|
||||||
|
|
||||||
|
char ReadStatusRegister(void)
|
||||||
|
{
|
||||||
|
char status_register = 0;
|
||||||
|
|
||||||
|
SetupSPI((COMMON_SPI_SETTINGS | TIMOD01)); /* Turn on the SPI */
|
||||||
|
|
||||||
|
*pSPI_TDBR = SPI_RDSR; /* send instruction to read status register */
|
||||||
|
__builtin_bfin_ssync();
|
||||||
|
Wait_For_SPIF(); /*wait until the instruction has been sent */
|
||||||
|
*pSPI_TDBR = 0; /*send dummy to receive the status register */
|
||||||
|
__builtin_bfin_ssync();
|
||||||
|
Wait_For_SPIF(); /*wait until the data has been sent */
|
||||||
|
status_register = *pSPI_RDBR; /*read the status register */
|
||||||
|
|
||||||
|
SPI_OFF(); /* Turn off the SPI */
|
||||||
|
|
||||||
|
return status_register;
|
||||||
|
}
|
||||||
|
|
||||||
|
ERROR_CODE GetSectorNumber(unsigned long ulOffset, int *pnSector)
|
||||||
|
{
|
||||||
|
int nSector = 0;
|
||||||
|
ERROR_CODE ErrorCode = NO_ERR;
|
||||||
|
|
||||||
|
if (ulOffset > (NUM_SECTORS * 0x10000 - 1)) {
|
||||||
|
ErrorCode = INVALID_SECTOR;
|
||||||
|
return ErrorCode;
|
||||||
|
}
|
||||||
|
|
||||||
|
nSector = (int)ulOffset / 0x10000;
|
||||||
|
*pnSector = nSector;
|
||||||
|
|
||||||
|
/* ok */
|
||||||
|
return ErrorCode;
|
||||||
|
}
|
||||||
|
|
||||||
|
ERROR_CODE EraseBlock(int nBlock)
|
||||||
|
{
|
||||||
|
unsigned long ulSectorOff = 0x0, ShiftValue;
|
||||||
|
ERROR_CODE ErrorCode = NO_ERR;
|
||||||
|
|
||||||
|
/* if the block is invalid just return */
|
||||||
|
if ((nBlock < 0) || (nBlock > NUM_SECTORS)) {
|
||||||
|
ErrorCode = INVALID_BLOCK; /* tells us if there was an error erasing flash */
|
||||||
|
return ErrorCode;
|
||||||
|
}
|
||||||
|
/* figure out the offset of the block in flash */
|
||||||
|
if ((nBlock >= 0) && (nBlock < NUM_SECTORS)) {
|
||||||
|
ulSectorOff = (nBlock * SECTOR_SIZE);
|
||||||
|
|
||||||
|
} else {
|
||||||
|
ErrorCode = INVALID_BLOCK; /* tells us if there was an error erasing flash */
|
||||||
|
return ErrorCode;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* A write enable instruction must previously have been executed */
|
||||||
|
SendSingleCommand(SPI_WREN);
|
||||||
|
|
||||||
|
/*The status register will be polled to check the write enable latch "WREN" */
|
||||||
|
ErrorCode = Wait_For_WEL();
|
||||||
|
|
||||||
|
if (POLL_TIMEOUT == ErrorCode) {
|
||||||
|
printf("SPI Erase block error\n");
|
||||||
|
return ErrorCode;
|
||||||
|
} else
|
||||||
|
/*Turn on the SPI to send single commands */
|
||||||
|
SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
|
||||||
|
|
||||||
|
/* Send the erase block command to the flash followed by the 24 address */
|
||||||
|
/* to point to the start of a sector. */
|
||||||
|
*pSPI_TDBR = SPI_SE;
|
||||||
|
__builtin_bfin_ssync();
|
||||||
|
Wait_For_SPIF();
|
||||||
|
ShiftValue = (ulSectorOff >> 16); /* Send the highest byte of the 24 bit address at first */
|
||||||
|
*pSPI_TDBR = ShiftValue;
|
||||||
|
__builtin_bfin_ssync();
|
||||||
|
Wait_For_SPIF(); /* Wait until the instruction has been sent */
|
||||||
|
ShiftValue = (ulSectorOff >> 8); /* Send the middle byte of the 24 bit address at second */
|
||||||
|
*pSPI_TDBR = ShiftValue;
|
||||||
|
__builtin_bfin_ssync();
|
||||||
|
Wait_For_SPIF(); /* Wait until the instruction has been sent */
|
||||||
|
*pSPI_TDBR = ulSectorOff; /* Send the lowest byte of the 24 bit address finally */
|
||||||
|
__builtin_bfin_ssync();
|
||||||
|
Wait_For_SPIF(); /* Wait until the instruction has been sent */
|
||||||
|
|
||||||
|
/*Turns off the SPI */
|
||||||
|
SPI_OFF();
|
||||||
|
|
||||||
|
/* Poll the status register to check the Write in Progress bit */
|
||||||
|
/* Sector erase takes time */
|
||||||
|
ErrorCode = Wait_For_Status(WIP);
|
||||||
|
|
||||||
|
/* block erase should be complete */
|
||||||
|
return ErrorCode;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*****************************************************************************
|
||||||
|
* ERROR_CODE ReadData()
|
||||||
|
*
|
||||||
|
* Read a value from flash for verify purpose
|
||||||
|
*
|
||||||
|
* Inputs: unsigned long ulStart - holds the SPI start address
|
||||||
|
* int pnData - pointer to store value read from flash
|
||||||
|
* long lCount - number of elements to read
|
||||||
|
***************************************************************************** */
|
||||||
|
ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData)
|
||||||
|
{
|
||||||
|
unsigned long ShiftValue;
|
||||||
|
char *cnData;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
cnData = (char *)pnData; /* Pointer cast to be able to increment byte wise */
|
||||||
|
|
||||||
|
/* Start SPI interface */
|
||||||
|
SetupSPI((COMMON_SPI_SETTINGS | TIMOD01));
|
||||||
|
|
||||||
|
*pSPI_TDBR = SPI_READ; /* Send the read command to SPI device */
|
||||||
|
__builtin_bfin_ssync();
|
||||||
|
Wait_For_SPIF(); /* Wait until the instruction has been sent */
|
||||||
|
ShiftValue = (ulStart >> 16); /* Send the highest byte of the 24 bit address at first */
|
||||||
|
*pSPI_TDBR = ShiftValue; /* Send the byte to the SPI device */
|
||||||
|
__builtin_bfin_ssync();
|
||||||
|
Wait_For_SPIF(); /* Wait until the instruction has been sent */
|
||||||
|
ShiftValue = (ulStart >> 8); /* Send the middle byte of the 24 bit address at second */
|
||||||
|
*pSPI_TDBR = ShiftValue; /* Send the byte to the SPI device */
|
||||||
|
__builtin_bfin_ssync();
|
||||||
|
Wait_For_SPIF(); /* Wait until the instruction has been sent */
|
||||||
|
*pSPI_TDBR = ulStart; /* Send the lowest byte of the 24 bit address finally */
|
||||||
|
__builtin_bfin_ssync();
|
||||||
|
Wait_For_SPIF(); /* Wait until the instruction has been sent */
|
||||||
|
|
||||||
|
/* After the SPI device address has been placed on the MOSI pin the data can be */
|
||||||
|
/* received on the MISO pin. */
|
||||||
|
for (i = 0; i < lCount; i++) {
|
||||||
|
*pSPI_TDBR = 0; /*send dummy */
|
||||||
|
__builtin_bfin_ssync();
|
||||||
|
while (!(*pSPI_STAT & RXS)) ;
|
||||||
|
*cnData++ = *pSPI_RDBR; /*read */
|
||||||
|
|
||||||
|
if ((i >= SECTOR_SIZE) && (i % SECTOR_SIZE == 0))
|
||||||
|
printf(".");
|
||||||
|
}
|
||||||
|
|
||||||
|
SPI_OFF(); /* Turn off the SPI */
|
||||||
|
|
||||||
|
return NO_ERR;
|
||||||
|
}
|
||||||
|
|
||||||
|
ERROR_CODE WriteFlash(unsigned long ulStartAddr, long lTransferCount,
|
||||||
|
int *iDataSource, long *lWriteCount)
|
||||||
|
{
|
||||||
|
|
||||||
|
unsigned long ulWAddr;
|
||||||
|
long lWTransferCount = 0;
|
||||||
|
int i;
|
||||||
|
char iData;
|
||||||
|
char *temp = (char *)iDataSource;
|
||||||
|
ERROR_CODE ErrorCode = NO_ERR; /* tells us if there was an error erasing flash */
|
||||||
|
|
||||||
|
/* First, a Write Enable Command must be sent to the SPI. */
|
||||||
|
SendSingleCommand(SPI_WREN);
|
||||||
|
|
||||||
|
/* Second, the SPI Status Register will be tested whether the */
|
||||||
|
/* Write Enable Bit has been set. */
|
||||||
|
ErrorCode = Wait_For_WEL();
|
||||||
|
if (POLL_TIMEOUT == ErrorCode) {
|
||||||
|
printf("SPI Write Time Out\n");
|
||||||
|
return ErrorCode;
|
||||||
|
} else
|
||||||
|
/* Third, the 24 bit address will be shifted out the SPI MOSI bytewise. */
|
||||||
|
SetupSPI((COMMON_SPI_SETTINGS | TIMOD01)); /* Turns the SPI on */
|
||||||
|
*pSPI_TDBR = SPI_PP;
|
||||||
|
__builtin_bfin_ssync();
|
||||||
|
Wait_For_SPIF(); /*wait until the instruction has been sent */
|
||||||
|
ulWAddr = (ulStartAddr >> 16);
|
||||||
|
*pSPI_TDBR = ulWAddr;
|
||||||
|
__builtin_bfin_ssync();
|
||||||
|
Wait_For_SPIF(); /*wait until the instruction has been sent */
|
||||||
|
ulWAddr = (ulStartAddr >> 8);
|
||||||
|
*pSPI_TDBR = ulWAddr;
|
||||||
|
__builtin_bfin_ssync();
|
||||||
|
Wait_For_SPIF(); /*wait until the instruction has been sent */
|
||||||
|
ulWAddr = ulStartAddr;
|
||||||
|
*pSPI_TDBR = ulWAddr;
|
||||||
|
__builtin_bfin_ssync();
|
||||||
|
Wait_For_SPIF(); /*wait until the instruction has been sent */
|
||||||
|
/* Fourth, maximum number of 256 bytes will be taken from the Buffer */
|
||||||
|
/* and sent to the SPI device. */
|
||||||
|
for (i = 0; (i < lTransferCount) && (i < 256); i++, lWTransferCount++) {
|
||||||
|
iData = *temp;
|
||||||
|
*pSPI_TDBR = iData;
|
||||||
|
__builtin_bfin_ssync();
|
||||||
|
Wait_For_SPIF(); /*wait until the instruction has been sent */
|
||||||
|
temp++;
|
||||||
|
}
|
||||||
|
|
||||||
|
SPI_OFF(); /* Turns the SPI off */
|
||||||
|
|
||||||
|
/* Sixth, the SPI Write in Progress Bit must be toggled to ensure the */
|
||||||
|
/* programming is done before start of next transfer. */
|
||||||
|
ErrorCode = Wait_For_Status(WIP);
|
||||||
|
|
||||||
|
if (POLL_TIMEOUT == ErrorCode) {
|
||||||
|
printf("SPI Program Time out!\n");
|
||||||
|
return ErrorCode;
|
||||||
|
} else
|
||||||
|
|
||||||
|
*lWriteCount = lWTransferCount;
|
||||||
|
|
||||||
|
return ErrorCode;
|
||||||
|
}
|
||||||
|
|
||||||
|
ERROR_CODE WriteData(unsigned long ulStart, long lCount, int *pnData)
|
||||||
|
{
|
||||||
|
|
||||||
|
unsigned long ulWStart = ulStart;
|
||||||
|
long lWCount = lCount, lWriteCount;
|
||||||
|
long *pnWriteCount = &lWriteCount;
|
||||||
|
|
||||||
|
ERROR_CODE ErrorCode = NO_ERR;
|
||||||
|
|
||||||
|
while (lWCount != 0) {
|
||||||
|
ErrorCode = WriteFlash(ulWStart, lWCount, pnData, pnWriteCount);
|
||||||
|
|
||||||
|
/* After each function call of WriteFlash the counter must be adjusted */
|
||||||
|
lWCount -= *pnWriteCount;
|
||||||
|
|
||||||
|
/* Also, both address pointers must be recalculated. */
|
||||||
|
ulWStart += *pnWriteCount;
|
||||||
|
pnData += *pnWriteCount / 4;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* return the appropriate error code */
|
||||||
|
return ErrorCode;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* CONFIG_SPI */
|
|
@ -1,7 +1,7 @@
|
||||||
/*
|
/*
|
||||||
* U-boot - u-boot.lds
|
* U-boot - u-boot.lds.S
|
||||||
*
|
*
|
||||||
* Copyright (c) 2005 blackfin.uclinux.org
|
* Copyright (c) 2005-2007 Analog Device Inc.
|
||||||
*
|
*
|
||||||
* (C) Copyright 2000-2004
|
* (C) Copyright 2000-2004
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
|
@ -25,6 +25,8 @@
|
||||||
* MA 02111-1307 USA
|
* MA 02111-1307 USA
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#include <config.h>
|
||||||
|
|
||||||
OUTPUT_ARCH(bfin)
|
OUTPUT_ARCH(bfin)
|
||||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
|
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
|
||||||
/* Do we need any of these for elf?
|
/* Do we need any of these for elf?
|
||||||
|
@ -55,6 +57,7 @@ SECTIONS
|
||||||
.rela.plt : { *(.rela.plt) }
|
.rela.plt : { *(.rela.plt) }
|
||||||
.init : { *(.init) }
|
.init : { *(.init) }
|
||||||
.plt : { *(.plt) }
|
.plt : { *(.plt) }
|
||||||
|
. = CFG_MONITOR_BASE;
|
||||||
.text :
|
.text :
|
||||||
{
|
{
|
||||||
/* WARNING - the following is hand-optimized to fit within */
|
/* WARNING - the following is hand-optimized to fit within */
|
||||||
|
@ -68,9 +71,11 @@ SECTIONS
|
||||||
cpu/bf533/interrupt.o (.text)
|
cpu/bf533/interrupt.o (.text)
|
||||||
cpu/bf533/serial.o (.text)
|
cpu/bf533/serial.o (.text)
|
||||||
common/dlmalloc.o (.text)
|
common/dlmalloc.o (.text)
|
||||||
lib_generic/vsprintf.o (.text)
|
/* lib_blackfin/bf533_string.o (.text) */
|
||||||
|
/* lib_generic/vsprintf.o (.text) */
|
||||||
lib_generic/crc32.o (.text)
|
lib_generic/crc32.o (.text)
|
||||||
lib_generic/zlib.o (.text)
|
/* lib_generic/zlib.o (.text) */
|
||||||
|
/* board/stamp/stamp.o (.text) */
|
||||||
|
|
||||||
. = DEFINED(env_offset) ? env_offset : .;
|
. = DEFINED(env_offset) ? env_offset : .;
|
||||||
common/environment.o (.text)
|
common/environment.o (.text)
|
||||||
|
@ -118,9 +123,9 @@ SECTIONS
|
||||||
_edata = .;
|
_edata = .;
|
||||||
PROVIDE (edata = .);
|
PROVIDE (edata = .);
|
||||||
|
|
||||||
__u_boot_cmd_start = .;
|
___u_boot_cmd_start = .;
|
||||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||||
__u_boot_cmd_end = .;
|
___u_boot_cmd_end = .;
|
||||||
|
|
||||||
|
|
||||||
__start___ex_table = .;
|
__start___ex_table = .;
|
||||||
|
@ -145,3 +150,4 @@ SECTIONS
|
||||||
_end = . ;
|
_end = . ;
|
||||||
PROVIDE (end = .);
|
PROVIDE (end = .);
|
||||||
}
|
}
|
||||||
|
|
|
@ -1,71 +0,0 @@
|
||||||
#
|
|
||||||
# U-boot - Makefile
|
|
||||||
#
|
|
||||||
# Copyright (c) 2005 blackfin.uclinux.org
|
|
||||||
#
|
|
||||||
# (C) Copyright 2000-2006
|
|
||||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
#
|
|
||||||
# See file CREDITS for list of people who contributed to this
|
|
||||||
# project.
|
|
||||||
#
|
|
||||||
# This program is free software; you can redistribute it and/or
|
|
||||||
# modify it under the terms of the GNU General Public License as
|
|
||||||
# published by the Free Software Foundation; either version 2 of
|
|
||||||
# the License, or (at your option) any later version.
|
|
||||||
#
|
|
||||||
# This program is distributed in the hope that it will be useful,
|
|
||||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
# GNU General Public License for more details.
|
|
||||||
#
|
|
||||||
# You should have received a copy of the GNU General Public License
|
|
||||||
# along with this program; if not, write to the Free Software
|
|
||||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
||||||
# MA 02111-1307 USA
|
|
||||||
#
|
|
||||||
|
|
||||||
#
|
|
||||||
# (C) Copyright 2001-2006
|
|
||||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
#
|
|
||||||
# See file CREDITS for list of people who contributed to this
|
|
||||||
# project.
|
|
||||||
#
|
|
||||||
# This program is free software; you can redistribute it and/or
|
|
||||||
# modify it under the terms of the GNU General Public License as
|
|
||||||
# published by the Free Software Foundation; either version 2 of
|
|
||||||
# the License, or (at your option) any later version.
|
|
||||||
#
|
|
||||||
# This program is distributed in the hope that it will be useful,
|
|
||||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
# GNU General Public License for more details.
|
|
||||||
#
|
|
||||||
# You should have received a copy of the GNU General Public License
|
|
||||||
# along with this program; if not, write to the Free Software
|
|
||||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
||||||
# MA 02111-1307 USA
|
|
||||||
#
|
|
||||||
|
|
||||||
include $(TOPDIR)/config.mk
|
|
||||||
|
|
||||||
LIB = $(obj)lib$(BOARD).a
|
|
||||||
|
|
||||||
COBJS = $(BOARD).o stamp.o
|
|
||||||
|
|
||||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
|
||||||
OBJS := $(addprefix $(obj),$(COBJS))
|
|
||||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
|
||||||
|
|
||||||
$(LIB): $(obj).depend $(OBJS)
|
|
||||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
|
||||||
|
|
||||||
#########################################################################
|
|
||||||
|
|
||||||
# defines $(obj).depend target
|
|
||||||
include $(SRCTREE)/rules.mk
|
|
||||||
|
|
||||||
sinclude $(obj).depend
|
|
||||||
|
|
||||||
#########################################################################
|
|
|
@ -2,7 +2,7 @@
|
||||||
#
|
#
|
||||||
# Copyright (c) 2005 blackfin.uclinux.org
|
# Copyright (c) 2005 blackfin.uclinux.org
|
||||||
#
|
#
|
||||||
# (C) Copyright 2000-2006
|
# (C) Copyright 2000-2004
|
||||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
#
|
#
|
||||||
# See file CREDITS for list of people who contributed to this
|
# See file CREDITS for list of people who contributed to this
|
||||||
|
@ -26,25 +26,23 @@
|
||||||
|
|
||||||
include $(TOPDIR)/config.mk
|
include $(TOPDIR)/config.mk
|
||||||
|
|
||||||
LIB = $(obj)lib$(CPU).a
|
LIB = lib$(CPU).a
|
||||||
|
|
||||||
START = start.o start1.o interrupt.o cache.o cplbhdlr.o cplbmgr.o flush.o
|
START = start.o start1.o interrupt.o cache.o flush.o init_sdram.o
|
||||||
COBJS = cpu.o traps.o ints.o serial.o interrupts.o
|
OBJS = cpu.o traps.o ints.o serial.o interrupts.o video.o
|
||||||
|
|
||||||
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
EXTRA = init_sdram_bootrom_initblock.o
|
||||||
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
|
|
||||||
START := $(addprefix $(obj),$(START))
|
|
||||||
|
|
||||||
all: $(obj).depend $(START) $(LIB)
|
all: .depend $(START) $(LIB) .depend $(EXTRA)
|
||||||
|
|
||||||
$(LIB): $(OBJS)
|
$(LIB): $(OBJS)
|
||||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
$(AR) cr $@ $(OBJS)
|
||||||
|
|
||||||
#########################################################################
|
#########################################################################
|
||||||
|
|
||||||
# defines $(obj).depend target
|
.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
|
||||||
include $(SRCTREE)/rules.mk
|
$(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
|
||||||
|
|
||||||
sinclude $(obj).depend
|
sinclude .depend
|
||||||
|
|
||||||
#########################################################################
|
#########################################################################
|
||||||
|
|
|
@ -63,7 +63,6 @@ int serial_getc(void);
|
||||||
void serial_puts(const char *s);
|
void serial_puts(const char *s);
|
||||||
static void local_put_char(char ch);
|
static void local_put_char(char ch);
|
||||||
|
|
||||||
extern int get_clock(void);
|
|
||||||
int baud_table[5] = { 9600, 19200, 38400, 57600, 115200 };
|
int baud_table[5] = { 9600, 19200, 38400, 57600, 115200 };
|
||||||
|
|
||||||
struct {
|
struct {
|
||||||
|
|
|
@ -1,12 +1,11 @@
|
||||||
|
|
||||||
|
|
||||||
#define ASSEMBLY
|
#define ASSEMBLY
|
||||||
#include <asm/linkage.h>
|
#include <asm/linkage.h>
|
||||||
#include <asm/cpu/def_LPBlackfin.h>
|
#include <config.h>
|
||||||
|
#include <asm/blackfin.h>
|
||||||
|
|
||||||
.text
|
.text
|
||||||
.align 2
|
.align 2
|
||||||
ENTRY(blackfin_icache_flush_range)
|
ENTRY(_blackfin_icache_flush_range)
|
||||||
R2 = -32;
|
R2 = -32;
|
||||||
R2 = R0 & R2;
|
R2 = R0 & R2;
|
||||||
P0 = R2;
|
P0 = R2;
|
||||||
|
@ -20,7 +19,7 @@ ENTRY(blackfin_icache_flush_range)
|
||||||
SSYNC;
|
SSYNC;
|
||||||
RTS;
|
RTS;
|
||||||
|
|
||||||
ENTRY(blackfin_dcache_flush_range)
|
ENTRY(_blackfin_dcache_flush_range)
|
||||||
R2 = -32;
|
R2 = -32;
|
||||||
R2 = R0 & R2;
|
R2 = R0 & R2;
|
||||||
P0 = R2;
|
P0 = R2;
|
||||||
|
@ -35,19 +34,21 @@ ENTRY(blackfin_dcache_flush_range)
|
||||||
RTS;
|
RTS;
|
||||||
|
|
||||||
ENTRY(_icache_invalidate)
|
ENTRY(_icache_invalidate)
|
||||||
ENTRY(invalidate_entire_icache)
|
ENTRY(_invalidate_entire_icache)
|
||||||
[--SP] = (R7:5);
|
[--SP] = (R7:5);
|
||||||
|
|
||||||
P0.L = (IMEM_CONTROL & 0xFFFF);
|
P0.L = (IMEM_CONTROL & 0xFFFF);
|
||||||
P0.H = (IMEM_CONTROL >> 16);
|
P0.H = (IMEM_CONTROL >> 16);
|
||||||
R7 =[P0];
|
R7 =[P0];
|
||||||
|
|
||||||
/* Clear the IMC bit , All valid bits in the instruction
|
/*
|
||||||
|
* Clear the IMC bit , All valid bits in the instruction
|
||||||
* cache are set to the invalid state
|
* cache are set to the invalid state
|
||||||
*/
|
*/
|
||||||
BITCLR(R7, IMC_P);
|
BITCLR(R7, IMC_P);
|
||||||
CLI R6;
|
CLI R6;
|
||||||
SSYNC; /* SSYNC required before invalidating cache. */
|
/* SSYNC required before invalidating cache. */
|
||||||
|
SSYNC;
|
||||||
.align 8;
|
.align 8;
|
||||||
[P0] = R7;
|
[P0] = R7;
|
||||||
SSYNC;
|
SSYNC;
|
||||||
|
@ -58,7 +59,7 @@ ENTRY(invalidate_entire_icache)
|
||||||
R7 = R7 | R6;
|
R7 = R7 | R6;
|
||||||
|
|
||||||
CLI R6;
|
CLI R6;
|
||||||
SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */
|
SSYNC;
|
||||||
.align 8;
|
.align 8;
|
||||||
[P0] = R7;
|
[P0] = R7;
|
||||||
SSYNC;
|
SSYNC;
|
||||||
|
@ -67,10 +68,11 @@ ENTRY(invalidate_entire_icache)
|
||||||
(R7:5) =[SP++];
|
(R7:5) =[SP++];
|
||||||
RTS;
|
RTS;
|
||||||
|
|
||||||
/* Invalidate the Entire Data cache by
|
/*
|
||||||
|
* Invalidate the Entire Data cache by
|
||||||
* clearing DMC[1:0] bits
|
* clearing DMC[1:0] bits
|
||||||
*/
|
*/
|
||||||
ENTRY(invalidate_entire_dcache)
|
ENTRY(_invalidate_entire_dcache)
|
||||||
ENTRY(_dcache_invalidate)
|
ENTRY(_dcache_invalidate)
|
||||||
[--SP] = (R7:6);
|
[--SP] = (R7:6);
|
||||||
|
|
||||||
|
@ -78,25 +80,25 @@ ENTRY(_dcache_invalidate)
|
||||||
P0.H = (DMEM_CONTROL >> 16);
|
P0.H = (DMEM_CONTROL >> 16);
|
||||||
R7 =[P0];
|
R7 =[P0];
|
||||||
|
|
||||||
/* Clear the DMC[1:0] bits, All valid bits in the data
|
/*
|
||||||
|
* Clear the DMC[1:0] bits, All valid bits in the data
|
||||||
* cache are set to the invalid state
|
* cache are set to the invalid state
|
||||||
*/
|
*/
|
||||||
BITCLR(R7, DMC0_P);
|
BITCLR(R7, DMC0_P);
|
||||||
BITCLR(R7, DMC1_P);
|
BITCLR(R7, DMC1_P);
|
||||||
CLI R6;
|
CLI R6;
|
||||||
SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */
|
SSYNC;
|
||||||
.align 8;
|
.align 8;
|
||||||
[P0] = R7;
|
[P0] = R7;
|
||||||
SSYNC;
|
SSYNC;
|
||||||
STI R6;
|
STI R6;
|
||||||
|
|
||||||
/* Configures the data cache again */
|
/* Configures the data cache again */
|
||||||
|
|
||||||
R6 = (ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
|
R6 = (ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
|
||||||
R7 = R7 | R6;
|
R7 = R7 | R6;
|
||||||
|
|
||||||
CLI R6;
|
CLI R6;
|
||||||
SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */
|
SSYNC;
|
||||||
.align 8;
|
.align 8;
|
||||||
[P0] = R7;
|
[P0] = R7;
|
||||||
SSYNC;
|
SSYNC;
|
||||||
|
@ -105,7 +107,7 @@ ENTRY(_dcache_invalidate)
|
||||||
(R7:6) =[SP++];
|
(R7:6) =[SP++];
|
||||||
RTS;
|
RTS;
|
||||||
|
|
||||||
ENTRY(blackfin_dcache_invalidate_range)
|
ENTRY(_blackfin_dcache_invalidate_range)
|
||||||
R2 = -32;
|
R2 = -32;
|
||||||
R2 = R0 & R2;
|
R2 = R0 & R2;
|
||||||
P0 = R2;
|
P0 = R2;
|
||||||
|
@ -116,9 +118,10 @@ ENTRY(blackfin_dcache_invalidate_range)
|
||||||
CC = P0 < P1(iu);
|
CC = P0 < P1(iu);
|
||||||
IF CC JUMP 1b(bp);
|
IF CC JUMP 1b(bp);
|
||||||
|
|
||||||
/* If the data crosses a cache line, then we'll be pointing to
|
/*
|
||||||
** the last cache line, but won't have flushed/invalidated it yet, so do
|
* If the data crosses a cache line, then we'll be pointing to
|
||||||
** one more.
|
* the last cache line, but won't have flushed/invalidated it yet, so do
|
||||||
|
* one more.
|
||||||
*/
|
*/
|
||||||
FLUSHINV[P0];
|
FLUSHINV[P0];
|
||||||
SSYNC;
|
SSYNC;
|
||||||
|
|
|
@ -24,4 +24,4 @@
|
||||||
# MA 02111-1307 USA
|
# MA 02111-1307 USA
|
||||||
#
|
#
|
||||||
|
|
||||||
PLATFORM_RELFLAGS += -ffixed-P5
|
PLATFORM_RELFLAGS += -mcpu=bf533 -ffixed-P5
|
||||||
|
|
|
@ -1,193 +0,0 @@
|
||||||
/* Copyright (C) 2003 Analog Devices, Inc. All Rights Reserved.
|
|
||||||
*
|
|
||||||
* This file is subject to the terms and conditions of the GNU General Public
|
|
||||||
* License.
|
|
||||||
*
|
|
||||||
* Blackfin BF533/2.6 support : LG Soft India
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/* Include an exception handler to invoke the CPLB manager
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <asm-blackfin/linkage.h>
|
|
||||||
#include <asm/cplb.h>
|
|
||||||
#include <asm/entry.h>
|
|
||||||
|
|
||||||
|
|
||||||
.text
|
|
||||||
|
|
||||||
.globl _cplb_hdr;
|
|
||||||
.type _cplb_hdr, STT_FUNC;
|
|
||||||
.extern _cplb_mgr;
|
|
||||||
.type _cplb_mgr, STT_FUNC;
|
|
||||||
.extern __unknown_exception_occurred;
|
|
||||||
.type __unknown_exception_occurred, STT_FUNC;
|
|
||||||
.extern __cplb_miss_all_locked;
|
|
||||||
.type __cplb_miss_all_locked, STT_FUNC;
|
|
||||||
.extern __cplb_miss_without_replacement;
|
|
||||||
.type __cplb_miss_without_replacement, STT_FUNC;
|
|
||||||
.extern __cplb_protection_violation;
|
|
||||||
.type __cplb_protection_violation, STT_FUNC;
|
|
||||||
.extern panic_pv;
|
|
||||||
|
|
||||||
.align 2;
|
|
||||||
|
|
||||||
ENTRY(_cplb_hdr)
|
|
||||||
SSYNC;
|
|
||||||
[--SP] = ( R7:0, P5:0 );
|
|
||||||
[--SP] = ASTAT;
|
|
||||||
[--SP] = SEQSTAT;
|
|
||||||
[--SP] = I0;
|
|
||||||
[--SP] = I1;
|
|
||||||
[--SP] = I2;
|
|
||||||
[--SP] = I3;
|
|
||||||
[--SP] = LT0;
|
|
||||||
[--SP] = LB0;
|
|
||||||
[--SP] = LC0;
|
|
||||||
[--SP] = LT1;
|
|
||||||
[--SP] = LB1;
|
|
||||||
[--SP] = LC1;
|
|
||||||
R2 = SEQSTAT;
|
|
||||||
|
|
||||||
/*Mask the contents of SEQSTAT and leave only EXCAUSE in R2*/
|
|
||||||
R2 <<= 26;
|
|
||||||
R2 >>= 26;
|
|
||||||
|
|
||||||
R1 = 0x23; /* Data access CPLB protection violation */
|
|
||||||
CC = R2 == R1;
|
|
||||||
IF !CC JUMP not_data_write;
|
|
||||||
R0 = 2; /* is a write to data space*/
|
|
||||||
JUMP is_icplb_miss;
|
|
||||||
|
|
||||||
not_data_write:
|
|
||||||
R1 = 0x2C; /* CPLB miss on an instruction fetch */
|
|
||||||
CC = R2 == R1;
|
|
||||||
R0 = 0; /* is_data_miss == False*/
|
|
||||||
IF CC JUMP is_icplb_miss;
|
|
||||||
|
|
||||||
R1 = 0x26;
|
|
||||||
CC = R2 == R1;
|
|
||||||
IF !CC JUMP unknown;
|
|
||||||
|
|
||||||
R0 = 1; /* is_data_miss == True*/
|
|
||||||
|
|
||||||
is_icplb_miss:
|
|
||||||
|
|
||||||
#if ( defined (CONFIG_BLKFIN_CACHE) || defined (CONFIG_BLKFIN_DCACHE))
|
|
||||||
#if ( defined (CONFIG_BLKFIN_CACHE) && !defined (CONFIG_BLKFIN_DCACHE))
|
|
||||||
R1 = CPLB_ENABLE_ICACHE;
|
|
||||||
#endif
|
|
||||||
#if ( !defined (CONFIG_BLKFIN_CACHE) && defined (CONFIG_BLKFIN_DCACHE))
|
|
||||||
R1 = CPLB_ENABLE_DCACHE;
|
|
||||||
#endif
|
|
||||||
#if ( defined (CONFIG_BLKFIN_CACHE) && defined (CONFIG_BLKFIN_DCACHE))
|
|
||||||
R1 = CPLB_ENABLE_DCACHE | CPLB_ENABLE_ICACHE;
|
|
||||||
#endif
|
|
||||||
#else
|
|
||||||
R1 = 0;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
[--SP] = RETS;
|
|
||||||
CALL _cplb_mgr;
|
|
||||||
RETS = [SP++];
|
|
||||||
CC = R0 == 0;
|
|
||||||
IF !CC JUMP not_replaced;
|
|
||||||
LC1 = [SP++];
|
|
||||||
LB1 = [SP++];
|
|
||||||
LT1 = [SP++];
|
|
||||||
LC0 = [SP++];
|
|
||||||
LB0 = [SP++];
|
|
||||||
LT0 = [SP++];
|
|
||||||
I3 = [SP++];
|
|
||||||
I2 = [SP++];
|
|
||||||
I1 = [SP++];
|
|
||||||
I0 = [SP++];
|
|
||||||
SEQSTAT = [SP++];
|
|
||||||
ASTAT = [SP++];
|
|
||||||
( R7:0, P5:0 ) = [SP++];
|
|
||||||
RTS;
|
|
||||||
|
|
||||||
unknown:
|
|
||||||
[--SP] = RETS;
|
|
||||||
CALL __unknown_exception_occurred;
|
|
||||||
RETS = [SP++];
|
|
||||||
JUMP unknown;
|
|
||||||
not_replaced:
|
|
||||||
CC = R0 == CPLB_NO_UNLOCKED;
|
|
||||||
IF !CC JUMP next_check;
|
|
||||||
[--SP] = RETS;
|
|
||||||
CALL __cplb_miss_all_locked;
|
|
||||||
RETS = [SP++];
|
|
||||||
next_check:
|
|
||||||
CC = R0 == CPLB_NO_ADDR_MATCH;
|
|
||||||
IF !CC JUMP next_check2;
|
|
||||||
[--SP] = RETS;
|
|
||||||
CALL __cplb_miss_without_replacement;
|
|
||||||
RETS = [SP++];
|
|
||||||
JUMP not_replaced;
|
|
||||||
next_check2:
|
|
||||||
CC = R0 == CPLB_PROT_VIOL;
|
|
||||||
IF !CC JUMP strange_return_from_cplb_mgr;
|
|
||||||
[--SP] = RETS;
|
|
||||||
CALL __cplb_protection_violation;
|
|
||||||
RETS = [SP++];
|
|
||||||
JUMP not_replaced;
|
|
||||||
strange_return_from_cplb_mgr:
|
|
||||||
IDLE;
|
|
||||||
CSYNC;
|
|
||||||
JUMP strange_return_from_cplb_mgr;
|
|
||||||
|
|
||||||
/************************************
|
|
||||||
* Diagnostic exception handlers
|
|
||||||
*/
|
|
||||||
|
|
||||||
__cplb_miss_all_locked:
|
|
||||||
sp += -12;
|
|
||||||
R0 = CPLB_NO_UNLOCKED;
|
|
||||||
call panic_bfin;
|
|
||||||
SP += 12;
|
|
||||||
RTS;
|
|
||||||
|
|
||||||
__cplb_miss_without_replacement:
|
|
||||||
sp += -12;
|
|
||||||
R0 = CPLB_NO_ADDR_MATCH;
|
|
||||||
call panic_bfin;
|
|
||||||
SP += 12;
|
|
||||||
RTS;
|
|
||||||
|
|
||||||
__cplb_protection_violation:
|
|
||||||
sp += -12;
|
|
||||||
R0 = CPLB_PROT_VIOL;
|
|
||||||
call panic_bfin;
|
|
||||||
SP += 12;
|
|
||||||
RTS;
|
|
||||||
|
|
||||||
__unknown_exception_occurred:
|
|
||||||
|
|
||||||
/* This function is invoked by the default exception
|
|
||||||
* handler, if it does not recognise the kind of
|
|
||||||
* exception that has occurred. In other words, the
|
|
||||||
* default handler only handles some of the system's
|
|
||||||
* exception types, and it does not expect any others
|
|
||||||
* to occur. If your application is going to be using
|
|
||||||
* other kinds of exceptions, you must replace the
|
|
||||||
* default handler with your own, that handles all the
|
|
||||||
* exceptions you will use.
|
|
||||||
*
|
|
||||||
* Since there's nothing we can do, we just loop here
|
|
||||||
* at what we hope is a suitably informative label.
|
|
||||||
*/
|
|
||||||
|
|
||||||
IDLE;
|
|
||||||
do_not_know_what_to_do:
|
|
||||||
CSYNC;
|
|
||||||
JUMP __unknown_exception_occurred;
|
|
||||||
|
|
||||||
RTS;
|
|
||||||
.__unknown_exception_occurred.end:
|
|
||||||
.global __unknown_exception_occurred;
|
|
||||||
.type __unknown_exception_occurred, STT_FUNC;
|
|
||||||
|
|
||||||
panic_bfin:
|
|
||||||
RTS;
|
|
|
@ -1,601 +0,0 @@
|
||||||
/*This file is subject to the terms and conditions of the GNU General Public
|
|
||||||
* License.
|
|
||||||
*
|
|
||||||
* Blackfin BF533/2.6 support : LG Soft India
|
|
||||||
* Modification: Dec 07 2004
|
|
||||||
* 1. Correction in icheck_lock. Valid lock entries were
|
|
||||||
* geting victimized, for instruction cplb replacement.
|
|
||||||
* 2. Setup loop's are modified as now toolchain support's P Indexed
|
|
||||||
* addressing
|
|
||||||
* :LG Soft India
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Usage: int _cplb_mgr(is_data_miss,int enable_cache)
|
|
||||||
* is_data_miss==2 => Mark as Dirty, write to the clean data page
|
|
||||||
* is_data_miss==1 => Replace a data CPLB.
|
|
||||||
* is_data_miss==0 => Replace an instruction CPLB.
|
|
||||||
*
|
|
||||||
* Returns:
|
|
||||||
* CPLB_RELOADED => Successfully updated CPLB table.
|
|
||||||
* CPLB_NO_UNLOCKED => All CPLBs are locked, so cannot be evicted.This indicates
|
|
||||||
* that the CPLBs in the configuration tablei are badly
|
|
||||||
* configured, as this should never occur.
|
|
||||||
* CPLB_NO_ADDR_MATCH => The address being accessed, that triggered the exception,
|
|
||||||
* is not covered by any of the CPLBs in the configuration
|
|
||||||
* table. The application isi presumably misbehaving.
|
|
||||||
* CPLB_PROT_VIOL => The address being accessed, that triggered thei exception,
|
|
||||||
* was not a first-write to a clean Write Back Data page,
|
|
||||||
* and so presumably is a genuine violation of the page's
|
|
||||||
* protection attributes. The application is misbehaving.
|
|
||||||
*/
|
|
||||||
#define ASSEMBLY
|
|
||||||
|
|
||||||
#include <asm-blackfin/linkage.h>
|
|
||||||
#include <asm-blackfin/blackfin.h>
|
|
||||||
#include <asm-blackfin/cplbtab.h>
|
|
||||||
#include <asm-blackfin/cplb.h>
|
|
||||||
|
|
||||||
.text
|
|
||||||
|
|
||||||
.align 2;
|
|
||||||
ENTRY(_cplb_mgr)
|
|
||||||
|
|
||||||
[--SP]=( R7:0,P5:0 );
|
|
||||||
|
|
||||||
CC = R0 == 2;
|
|
||||||
IF CC JUMP dcplb_write;
|
|
||||||
|
|
||||||
CC = R0 == 0;
|
|
||||||
IF !CC JUMP dcplb_miss_compare;
|
|
||||||
|
|
||||||
/* ICPLB Miss Exception. We need to choose one of the
|
|
||||||
* currently-installed CPLBs, and replace it with one
|
|
||||||
* from the configuration table.
|
|
||||||
*/
|
|
||||||
|
|
||||||
P4.L = (ICPLB_FAULT_ADDR & 0xFFFF);
|
|
||||||
P4.H = (ICPLB_FAULT_ADDR >> 16);
|
|
||||||
|
|
||||||
P1 = 16;
|
|
||||||
P5.L = page_size_table;
|
|
||||||
P5.H = page_size_table;
|
|
||||||
|
|
||||||
P0.L = (ICPLB_DATA0 & 0xFFFF);
|
|
||||||
P0.H = (ICPLB_DATA0 >> 16);
|
|
||||||
R4 = [P4]; /* Get faulting address*/
|
|
||||||
R6 = 64; /* Advance past the fault address, which*/
|
|
||||||
R6 = R6 + R4; /* we'll use if we find a match*/
|
|
||||||
R3 = ((16 << 8) | 2); /* Extract mask, bits 16 and 17.*/
|
|
||||||
|
|
||||||
R5 = 0;
|
|
||||||
isearch:
|
|
||||||
|
|
||||||
R1 = [P0-0x100]; /* Address for this CPLB */
|
|
||||||
|
|
||||||
R0 = [P0++]; /* Info for this CPLB*/
|
|
||||||
CC = BITTST(R0,0); /* Is the CPLB valid?*/
|
|
||||||
IF !CC JUMP nomatch; /* Skip it, if not.*/
|
|
||||||
CC = R4 < R1(IU); /* If fault address less than page start*/
|
|
||||||
IF CC JUMP nomatch; /* then skip this one.*/
|
|
||||||
R2 = EXTRACT(R0,R3.L) (Z); /* Get page size*/
|
|
||||||
P1 = R2;
|
|
||||||
P1 = P5 + (P1<<2); /* index into page-size table*/
|
|
||||||
R2 = [P1]; /* Get the page size*/
|
|
||||||
R1 = R1 + R2; /* and add to page start, to get page end*/
|
|
||||||
CC = R4 < R1(IU); /* and see whether fault addr is in page.*/
|
|
||||||
IF !CC R4 = R6; /* If so, advance the address and finish loop.*/
|
|
||||||
IF !CC JUMP isearch_done;
|
|
||||||
nomatch:
|
|
||||||
/* Go around again*/
|
|
||||||
R5 += 1;
|
|
||||||
CC = BITTST(R5, 4); /* i.e CC = R5 >= 16*/
|
|
||||||
IF !CC JUMP isearch;
|
|
||||||
|
|
||||||
isearch_done:
|
|
||||||
I0 = R4; /* Fault address we'll search for*/
|
|
||||||
|
|
||||||
/* set up pointers */
|
|
||||||
P0.L = (ICPLB_DATA0 & 0xFFFF);
|
|
||||||
P0.H = (ICPLB_DATA0 >> 16);
|
|
||||||
|
|
||||||
/* The replacement procedure for ICPLBs */
|
|
||||||
|
|
||||||
P4.L = (IMEM_CONTROL & 0xFFFF);
|
|
||||||
P4.H = (IMEM_CONTROL >> 16);
|
|
||||||
|
|
||||||
/* disable cplbs */
|
|
||||||
R5 = [P4]; /* Control Register*/
|
|
||||||
BITCLR(R5,ENICPLB_P);
|
|
||||||
CLI R1;
|
|
||||||
SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */
|
|
||||||
.align 8;
|
|
||||||
[P4] = R5;
|
|
||||||
SSYNC;
|
|
||||||
STI R1;
|
|
||||||
|
|
||||||
R1 = -1; /* end point comparison */
|
|
||||||
R3 = 16; /* counter */
|
|
||||||
|
|
||||||
/* Search through CPLBs for first non-locked entry */
|
|
||||||
/* Overwrite it by moving everyone else up by 1 */
|
|
||||||
icheck_lock:
|
|
||||||
R0 = [P0++];
|
|
||||||
R3 = R3 + R1;
|
|
||||||
CC = R3 == R1;
|
|
||||||
IF CC JUMP all_locked;
|
|
||||||
CC = BITTST(R0, 0); /* an invalid entry is good */
|
|
||||||
IF !CC JUMP ifound_victim;
|
|
||||||
CC = BITTST(R0,1); /* but a locked entry isn't */
|
|
||||||
IF CC JUMP icheck_lock;
|
|
||||||
|
|
||||||
ifound_victim:
|
|
||||||
#ifdef CONFIG_CPLB_INFO
|
|
||||||
R7 = [P0 - 0x104];
|
|
||||||
P2.L = ipdt_table;
|
|
||||||
P2.H = ipdt_table;
|
|
||||||
P3.L = ipdt_swapcount_table;
|
|
||||||
P3.H = ipdt_swapcount_table;
|
|
||||||
P3 += -4;
|
|
||||||
icount:
|
|
||||||
R2 = [P2]; /* address from config table */
|
|
||||||
P2 += 8;
|
|
||||||
P3 += 8;
|
|
||||||
CC = R2==-1;
|
|
||||||
IF CC JUMP icount_done;
|
|
||||||
CC = R7==R2;
|
|
||||||
IF !CC JUMP icount;
|
|
||||||
R7 = [P3];
|
|
||||||
R7 += 1;
|
|
||||||
[P3] = R7;
|
|
||||||
CSYNC;
|
|
||||||
icount_done:
|
|
||||||
#endif
|
|
||||||
LC0=R3;
|
|
||||||
LSETUP(is_move,ie_move) LC0;
|
|
||||||
is_move:
|
|
||||||
R0 = [P0];
|
|
||||||
[P0 - 4] = R0;
|
|
||||||
R0 = [P0 - 0x100];
|
|
||||||
[P0-0x104] = R0;
|
|
||||||
ie_move:P0+=4;
|
|
||||||
|
|
||||||
/* We've made space in the ICPLB table, so that ICPLB15
|
|
||||||
* is now free to be overwritten. Next, we have to determine
|
|
||||||
* which CPLB we need to install, from the configuration
|
|
||||||
* table. This is a matter of getting the start-of-page
|
|
||||||
* addresses and page-lengths from the config table, and
|
|
||||||
* determining whether the fault address falls within that
|
|
||||||
* range.
|
|
||||||
*/
|
|
||||||
|
|
||||||
P2.L = ipdt_table;
|
|
||||||
P2.H = ipdt_table;
|
|
||||||
#ifdef CONFIG_CPLB_INFO
|
|
||||||
P3.L = ipdt_swapcount_table;
|
|
||||||
P3.H = ipdt_swapcount_table;
|
|
||||||
P3 += -8;
|
|
||||||
#endif
|
|
||||||
P0.L = page_size_table;
|
|
||||||
P0.H = page_size_table;
|
|
||||||
|
|
||||||
/* Retrieve our fault address (which may have been advanced
|
|
||||||
* because the faulting instruction crossed a page boundary).
|
|
||||||
*/
|
|
||||||
|
|
||||||
R0 = I0;
|
|
||||||
|
|
||||||
/* An extraction pattern, to get the page-size bits from
|
|
||||||
* the CPLB data entry. Bits 16-17, so two bits at posn 16.
|
|
||||||
*/
|
|
||||||
|
|
||||||
R1 = ((16<<8)|2);
|
|
||||||
inext: R4 = [P2++]; /* address from config table */
|
|
||||||
R2 = [P2++]; /* data from config table */
|
|
||||||
#ifdef CONFIG_CPLB_INFO
|
|
||||||
P3 += 8;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
CC = R4 == -1; /* End of config table*/
|
|
||||||
IF CC JUMP no_page_in_table;
|
|
||||||
|
|
||||||
/* See if failed address > start address */
|
|
||||||
CC = R4 <= R0(IU);
|
|
||||||
IF !CC JUMP inext;
|
|
||||||
|
|
||||||
/* extract page size (17:16)*/
|
|
||||||
R3 = EXTRACT(R2, R1.L) (Z);
|
|
||||||
|
|
||||||
/* add page size to addr to get range */
|
|
||||||
|
|
||||||
P5 = R3;
|
|
||||||
P5 = P0 + (P5 << 2); /* scaled, for int access*/
|
|
||||||
R3 = [P5];
|
|
||||||
R3 = R3 + R4;
|
|
||||||
|
|
||||||
/* See if failed address < (start address + page size) */
|
|
||||||
CC = R0 < R3(IU);
|
|
||||||
IF !CC JUMP inext;
|
|
||||||
|
|
||||||
/* We've found a CPLB in the config table that covers
|
|
||||||
* the faulting address, so install this CPLB into the
|
|
||||||
* last entry of the table.
|
|
||||||
*/
|
|
||||||
|
|
||||||
P1.L = (ICPLB_DATA15 & 0xFFFF); /*ICPLB_DATA15*/
|
|
||||||
P1.H = (ICPLB_DATA15 >> 16);
|
|
||||||
[P1] = R2;
|
|
||||||
[P1-0x100] = R4;
|
|
||||||
#ifdef CONFIG_CPLB_INFO
|
|
||||||
R3 = [P3];
|
|
||||||
R3 += 1;
|
|
||||||
[P3] = R3;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* P4 points to IMEM_CONTROL, and R5 contains its old
|
|
||||||
* value, after we disabled ICPLBS. Re-enable them.
|
|
||||||
*/
|
|
||||||
|
|
||||||
BITSET(R5,ENICPLB_P);
|
|
||||||
CLI R2;
|
|
||||||
SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */
|
|
||||||
.align 8;
|
|
||||||
[P4] = R5;
|
|
||||||
SSYNC;
|
|
||||||
STI R2;
|
|
||||||
|
|
||||||
( R7:0,P5:0 ) = [SP++];
|
|
||||||
R0 = CPLB_RELOADED;
|
|
||||||
RTS;
|
|
||||||
|
|
||||||
/* FAILED CASES*/
|
|
||||||
no_page_in_table:
|
|
||||||
( R7:0,P5:0 ) = [SP++];
|
|
||||||
R0 = CPLB_NO_ADDR_MATCH;
|
|
||||||
RTS;
|
|
||||||
all_locked:
|
|
||||||
( R7:0,P5:0 ) = [SP++];
|
|
||||||
R0 = CPLB_NO_UNLOCKED;
|
|
||||||
RTS;
|
|
||||||
prot_violation:
|
|
||||||
( R7:0,P5:0 ) = [SP++];
|
|
||||||
R0 = CPLB_PROT_VIOL;
|
|
||||||
RTS;
|
|
||||||
|
|
||||||
dcplb_write:
|
|
||||||
|
|
||||||
/* if a DCPLB is marked as write-back (CPLB_WT==0), and
|
|
||||||
* it is clean (CPLB_DIRTY==0), then a write to the
|
|
||||||
* CPLB's page triggers a protection violation. We have to
|
|
||||||
* mark the CPLB as dirty, to indicate that there are
|
|
||||||
* pending writes associated with the CPLB.
|
|
||||||
*/
|
|
||||||
|
|
||||||
P4.L = (DCPLB_STATUS & 0xFFFF);
|
|
||||||
P4.H = (DCPLB_STATUS >> 16);
|
|
||||||
P3.L = (DCPLB_DATA0 & 0xFFFF);
|
|
||||||
P3.H = (DCPLB_DATA0 >> 16);
|
|
||||||
R5 = [P4];
|
|
||||||
|
|
||||||
/* A protection violation can be caused by more than just writes
|
|
||||||
* to a clean WB page, so we have to ensure that:
|
|
||||||
* - It's a write
|
|
||||||
* - to a clean WB page
|
|
||||||
* - and is allowed in the mode the access occurred.
|
|
||||||
*/
|
|
||||||
|
|
||||||
CC = BITTST(R5, 16); /* ensure it was a write*/
|
|
||||||
IF !CC JUMP prot_violation;
|
|
||||||
|
|
||||||
/* to check the rest, we have to retrieve the DCPLB.*/
|
|
||||||
|
|
||||||
/* The low half of DCPLB_STATUS is a bit mask*/
|
|
||||||
|
|
||||||
R2 = R5.L (Z); /* indicating which CPLB triggered the event.*/
|
|
||||||
R3 = 30; /* so we can use this to determine the offset*/
|
|
||||||
R2.L = SIGNBITS R2;
|
|
||||||
R2 = R2.L (Z); /* into the DCPLB table.*/
|
|
||||||
R3 = R3 - R2;
|
|
||||||
P4 = R3;
|
|
||||||
P3 = P3 + (P4<<2);
|
|
||||||
R3 = [P3]; /* Retrieve the CPLB*/
|
|
||||||
|
|
||||||
/* Now we can check whether it's a clean WB page*/
|
|
||||||
|
|
||||||
CC = BITTST(R3, 14); /* 0==WB, 1==WT*/
|
|
||||||
IF CC JUMP prot_violation;
|
|
||||||
CC = BITTST(R3, 7); /* 0 == clean, 1 == dirty*/
|
|
||||||
IF CC JUMP prot_violation;
|
|
||||||
|
|
||||||
/* Check whether the write is allowed in the mode that was active.*/
|
|
||||||
|
|
||||||
R2 = 1<<3; /* checking write in user mode*/
|
|
||||||
CC = BITTST(R5, 17); /* 0==was user, 1==was super*/
|
|
||||||
R5 = CC;
|
|
||||||
R2 <<= R5; /* if was super, check write in super mode*/
|
|
||||||
R2 = R3 & R2;
|
|
||||||
CC = R2 == 0;
|
|
||||||
IF CC JUMP prot_violation;
|
|
||||||
|
|
||||||
/* It's a genuine write-to-clean-page.*/
|
|
||||||
|
|
||||||
BITSET(R3, 7); /* mark as dirty*/
|
|
||||||
[P3] = R3; /* and write back.*/
|
|
||||||
CSYNC;
|
|
||||||
( R7:0,P5:0 ) = [SP++];
|
|
||||||
R0 = CPLB_RELOADED;
|
|
||||||
RTS;
|
|
||||||
|
|
||||||
dcplb_miss_compare:
|
|
||||||
|
|
||||||
/* Data CPLB Miss event. We need to choose a CPLB to
|
|
||||||
* evict, and then locate a new CPLB to install from the
|
|
||||||
* config table, that covers the faulting address.
|
|
||||||
*/
|
|
||||||
|
|
||||||
P1.L = (DCPLB_DATA15 & 0xFFFF);
|
|
||||||
P1.H = (DCPLB_DATA15 >> 16);
|
|
||||||
|
|
||||||
P4.L = (DCPLB_FAULT_ADDR & 0xFFFF);
|
|
||||||
P4.H = (DCPLB_FAULT_ADDR >> 16);
|
|
||||||
R4 = [P4];
|
|
||||||
I0 = R4;
|
|
||||||
|
|
||||||
/* The replacement procedure for DCPLBs*/
|
|
||||||
|
|
||||||
R6 = R1; /* Save for later*/
|
|
||||||
|
|
||||||
/* Turn off CPLBs while we work.*/
|
|
||||||
P4.L = (DMEM_CONTROL & 0xFFFF);
|
|
||||||
P4.H = (DMEM_CONTROL >> 16);
|
|
||||||
R5 = [P4];
|
|
||||||
BITCLR(R5,ENDCPLB_P);
|
|
||||||
CLI R0;
|
|
||||||
SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */
|
|
||||||
.align 8;
|
|
||||||
[P4] = R5;
|
|
||||||
SSYNC;
|
|
||||||
STI R0;
|
|
||||||
|
|
||||||
/* Start looking for a CPLB to evict. Our order of preference
|
|
||||||
* is: invalid CPLBs, clean CPLBs, dirty CPLBs. Locked CPLBs
|
|
||||||
* are no good.
|
|
||||||
*/
|
|
||||||
|
|
||||||
I1.L = (DCPLB_DATA0 & 0xFFFF);
|
|
||||||
I1.H = (DCPLB_DATA0 >> 16);
|
|
||||||
P1 = 3;
|
|
||||||
P2 = 16;
|
|
||||||
I2.L = dcplb_preference;
|
|
||||||
I2.H = dcplb_preference;
|
|
||||||
LSETUP(sdsearch1, edsearch1) LC0 = P1;
|
|
||||||
sdsearch1:
|
|
||||||
R0 = [I2++]; /* Get the bits we're interested in*/
|
|
||||||
P0 = I1; /* Go back to start of table*/
|
|
||||||
LSETUP (sdsearch2, edsearch2) LC1 = P2;
|
|
||||||
sdsearch2:
|
|
||||||
R1 = [P0++]; /* Fetch each installed CPLB in turn*/
|
|
||||||
R2 = R1 & R0; /* and test for interesting bits.*/
|
|
||||||
CC = R2 == 0; /* If none are set, it'll do.*/
|
|
||||||
IF !CC JUMP skip_stack_check;
|
|
||||||
|
|
||||||
R2 = [P0 - 0x104]; /* R2 - PageStart */
|
|
||||||
P3.L = page_size_table; /* retrive end address */
|
|
||||||
P3.H = page_size_table; /* retrive end address */
|
|
||||||
R3 = 0x2; /* 0th - position, 2 bits -length */
|
|
||||||
nop; /*Anamoly 05000209*/
|
|
||||||
R7 = EXTRACT(R1,R3.l);
|
|
||||||
R7 = R7 << 2; /* Page size index offset */
|
|
||||||
P5 = R7;
|
|
||||||
P3 = P3 + P5;
|
|
||||||
R7 = [P3]; /* page size in 1K bytes */
|
|
||||||
|
|
||||||
R7 = R7 << 0xA; /* in bytes * 1024*/
|
|
||||||
R7 = R2 + R7; /* R7 - PageEnd */
|
|
||||||
R4 = SP; /* Test SP is in range */
|
|
||||||
|
|
||||||
CC = R7 < R4; /* if PageEnd < SP */
|
|
||||||
IF CC JUMP dfound_victim;
|
|
||||||
R3 = 0x284; /* stack length from start of trap till the point */
|
|
||||||
/* 20 stack locations for future modifications */
|
|
||||||
R4 = R4 + R3;
|
|
||||||
CC = R4 < R2; /* if SP + stacklen < PageStart */
|
|
||||||
IF CC JUMP dfound_victim;
|
|
||||||
skip_stack_check:
|
|
||||||
|
|
||||||
edsearch2: NOP;
|
|
||||||
edsearch1: NOP;
|
|
||||||
|
|
||||||
/* If we got here, we didn't find a DCPLB we considered
|
|
||||||
* replacable, which means all of them were locked.
|
|
||||||
*/
|
|
||||||
|
|
||||||
JUMP all_locked;
|
|
||||||
dfound_victim:
|
|
||||||
|
|
||||||
#ifdef CONFIG_CPLB_INFO
|
|
||||||
R1 = [P0 - 0x104];
|
|
||||||
P2.L = dpdt_table;
|
|
||||||
P2.H = dpdt_table;
|
|
||||||
P3.L = dpdt_swapcount_table;
|
|
||||||
P3.H = dpdt_swapcount_table;
|
|
||||||
P3 += -4;
|
|
||||||
dicount:
|
|
||||||
R2 = [P2];
|
|
||||||
P2 += 8;
|
|
||||||
P3 += 8;
|
|
||||||
CC = R2==-1;
|
|
||||||
IF CC JUMP dicount_done;
|
|
||||||
CC = R1==R2;
|
|
||||||
IF !CC JUMP dicount;
|
|
||||||
R1 = [P3];
|
|
||||||
R1 += 1;
|
|
||||||
[P3] = R1;
|
|
||||||
CSYNC;
|
|
||||||
dicount_done:
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Clean down the hardware loops*/
|
|
||||||
R2 = 0;
|
|
||||||
LC1 = R2;
|
|
||||||
LC0 = R2;
|
|
||||||
|
|
||||||
/* There's a suitable victim in [P0-4] (because we've
|
|
||||||
* advanced already). If it's a valid dirty write-back
|
|
||||||
* CPLB, we need to flush the pending writes first.
|
|
||||||
*/
|
|
||||||
|
|
||||||
CC = BITTST(R1, 0); /* Is it valid?*/
|
|
||||||
IF !CC JUMP Ddoverwrite;/* nope.*/
|
|
||||||
CC = BITTST(R1, 7); /* Is it dirty?*/
|
|
||||||
IF !CC JUMP Ddoverwrite (BP); /* Nope.*/
|
|
||||||
CC = BITTST(R1, 14); /* Is it Write-Through?*/
|
|
||||||
IF CC JUMP Ddoverwrite; /* Yep*/
|
|
||||||
|
|
||||||
/* This is a dirty page, so we need to flush all writes
|
|
||||||
* that are pending on the page.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Retrieve the page start address*/
|
|
||||||
R0 = [P0 - 0x104];
|
|
||||||
[--sp] = rets;
|
|
||||||
CALL dcplb_flush; /* R0==CPLB addr, R1==CPLB data*/
|
|
||||||
rets = [sp++];
|
|
||||||
Ddoverwrite:
|
|
||||||
|
|
||||||
/* [P0-4] is a suitable victim CPLB, so we want to
|
|
||||||
* overwrite it by moving all the following CPLBs
|
|
||||||
* one space closer to the start.
|
|
||||||
*/
|
|
||||||
|
|
||||||
R1.L = ((DCPLB_DATA15+4) & 0xFFFF); /*DCPLB_DATA15+4*/
|
|
||||||
R1.H = ((DCPLB_DATA15+4) >> 16);
|
|
||||||
R0 = P0;
|
|
||||||
|
|
||||||
/* If the victim happens to be in DCPLB15,
|
|
||||||
* we don't need to move anything.
|
|
||||||
*/
|
|
||||||
|
|
||||||
CC = R1 == R0;
|
|
||||||
IF CC JUMP de_moved;
|
|
||||||
R1 = R1 - R0;
|
|
||||||
R1 >>= 2;
|
|
||||||
P1 = R1;
|
|
||||||
LSETUP(ds_move, de_move) LC0=P1;
|
|
||||||
ds_move:
|
|
||||||
R0 = [P0++]; /* move data */
|
|
||||||
[P0 - 8] = R0;
|
|
||||||
R0 = [P0-0x104] /* move address */
|
|
||||||
de_move: [P0-0x108] = R0;
|
|
||||||
|
|
||||||
/* We've now made space in DCPLB15 for the new CPLB to be
|
|
||||||
* installed. The next stage is to locate a CPLB in the
|
|
||||||
* config table that covers the faulting address.
|
|
||||||
*/
|
|
||||||
|
|
||||||
de_moved:NOP;
|
|
||||||
R0 = I0; /* Our faulting address */
|
|
||||||
|
|
||||||
P2.L = dpdt_table;
|
|
||||||
P2.H = dpdt_table;
|
|
||||||
#ifdef CONFIG_CPLB_INFO
|
|
||||||
P3.L = dpdt_swapcount_table;
|
|
||||||
P3.H = dpdt_swapcount_table;
|
|
||||||
P3 += -8;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
P1.L = page_size_table;
|
|
||||||
P1.H = page_size_table;
|
|
||||||
|
|
||||||
/* An extraction pattern, to retrieve bits 17:16.*/
|
|
||||||
|
|
||||||
R1 = (16<<8)|2;
|
|
||||||
dnext: R4 = [P2++]; /* address */
|
|
||||||
R2 = [P2++]; /* data */
|
|
||||||
#ifdef CONFIG_CPLB_INFO
|
|
||||||
P3 += 8;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
CC = R4 == -1;
|
|
||||||
IF CC JUMP no_page_in_table;
|
|
||||||
|
|
||||||
/* See if failed address > start address */
|
|
||||||
CC = R4 <= R0(IU);
|
|
||||||
IF !CC JUMP dnext;
|
|
||||||
|
|
||||||
/* extract page size (17:16)*/
|
|
||||||
R3 = EXTRACT(R2, R1.L) (Z);
|
|
||||||
|
|
||||||
/* add page size to addr to get range */
|
|
||||||
|
|
||||||
P5 = R3;
|
|
||||||
P5 = P1 + (P5 << 2);
|
|
||||||
R3 = [P5];
|
|
||||||
R3 = R3 + R4;
|
|
||||||
|
|
||||||
/* See if failed address < (start address + page size) */
|
|
||||||
CC = R0 < R3(IU);
|
|
||||||
IF !CC JUMP dnext;
|
|
||||||
|
|
||||||
/* We've found the CPLB that should be installed, so
|
|
||||||
* write it into CPLB15, masking off any caching bits
|
|
||||||
* if necessary.
|
|
||||||
*/
|
|
||||||
|
|
||||||
P1.L = (DCPLB_DATA15 & 0xFFFF);
|
|
||||||
P1.H = (DCPLB_DATA15 >> 16);
|
|
||||||
|
|
||||||
/* If the DCPLB has cache bits set, but caching hasn't
|
|
||||||
* been enabled, then we want to mask off the cache-in-L1
|
|
||||||
* bit before installing. Moreover, if caching is off, we
|
|
||||||
* also want to ensure that the DCPLB has WT mode set, rather
|
|
||||||
* than WB, since WB pages still trigger first-write exceptions
|
|
||||||
* even when not caching is off, and the page isn't marked as
|
|
||||||
* cachable. Finally, we could mark the page as clean, not dirty,
|
|
||||||
* but we choose to leave that decision to the user; if the user
|
|
||||||
* chooses to have a CPLB pre-defined as dirty, then they always
|
|
||||||
* pay the cost of flushing during eviction, but don't pay the
|
|
||||||
* cost of first-write exceptions to mark the page as dirty.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef CONFIG_BLKFIN_WT
|
|
||||||
BITSET(R6, 14); /* Set WT*/
|
|
||||||
#endif
|
|
||||||
|
|
||||||
[P1] = R2;
|
|
||||||
[P1-0x100] = R4;
|
|
||||||
#ifdef CONFIG_CPLB_INFO
|
|
||||||
R3 = [P3];
|
|
||||||
R3 += 1;
|
|
||||||
[P3] = R3;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* We've installed the CPLB, so re-enable CPLBs. P4
|
|
||||||
* points to DMEM_CONTROL, and R5 is the value we
|
|
||||||
* last wrote to it, when we were disabling CPLBs.
|
|
||||||
*/
|
|
||||||
|
|
||||||
BITSET(R5,ENDCPLB_P);
|
|
||||||
CLI R2;
|
|
||||||
.align 8;
|
|
||||||
[P4] = R5;
|
|
||||||
SSYNC;
|
|
||||||
STI R2;
|
|
||||||
|
|
||||||
( R7:0,P5:0 ) = [SP++];
|
|
||||||
R0 = CPLB_RELOADED;
|
|
||||||
RTS;
|
|
||||||
|
|
||||||
.data
|
|
||||||
.align 4;
|
|
||||||
page_size_table:
|
|
||||||
.byte4 0x00000400; /* 1K */
|
|
||||||
.byte4 0x00001000; /* 4K */
|
|
||||||
.byte4 0x00100000; /* 1M */
|
|
||||||
.byte4 0x00400000; /* 4M */
|
|
||||||
|
|
||||||
.align 4;
|
|
||||||
dcplb_preference:
|
|
||||||
.byte4 0x00000001; /* valid bit */
|
|
||||||
.byte4 0x00000082; /* dirty+lock bits */
|
|
||||||
.byte4 0x00000002; /* lock bit */
|
|
192
cpu/bf533/cpu.c
192
cpu/bf533/cpu.c
|
@ -29,71 +29,27 @@
|
||||||
#include <asm/blackfin.h>
|
#include <asm/blackfin.h>
|
||||||
#include <command.h>
|
#include <command.h>
|
||||||
#include <asm/entry.h>
|
#include <asm/entry.h>
|
||||||
|
#include <asm/cplb.h>
|
||||||
|
|
||||||
#define SSYNC() asm("ssync;")
|
|
||||||
#define CACHE_ON 1
|
#define CACHE_ON 1
|
||||||
#define CACHE_OFF 0
|
#define CACHE_OFF 0
|
||||||
|
|
||||||
/* Data Attibutes*/
|
extern unsigned int icplb_table[page_descriptor_table_size][2];
|
||||||
|
extern unsigned int dcplb_table[page_descriptor_table_size][2];
|
||||||
|
|
||||||
#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
|
#ifdef DEBUG
|
||||||
#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
|
#define pr_debug(fmt,arg...) printf(fmt,##arg)
|
||||||
#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
|
#else
|
||||||
#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
|
static inline int
|
||||||
|
__attribute__ ((format(printf, 1, 2))) pr_debug(const char *fmt, ...)
|
||||||
#define ANOMALY_05000158 0x200
|
{
|
||||||
#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
|
return 0;
|
||||||
#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
|
}
|
||||||
#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
|
#endif
|
||||||
#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
|
|
||||||
#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
|
|
||||||
|
|
||||||
static unsigned int icplb_table[16][2]={
|
|
||||||
{0xFFA00000, L1_IMEMORY},
|
|
||||||
{0x00000000, SDRAM_IKERNEL}, /*SDRAM_Page1*/
|
|
||||||
{0x00400000, SDRAM_IKERNEL}, /*SDRAM_Page1*/
|
|
||||||
{0x07C00000, SDRAM_IKERNEL}, /*SDRAM_Page14*/
|
|
||||||
{0x00800000, SDRAM_IGENERIC}, /*SDRAM_Page2*/
|
|
||||||
{0x00C00000, SDRAM_IGENERIC}, /*SDRAM_Page2*/
|
|
||||||
{0x01000000, SDRAM_IGENERIC}, /*SDRAM_Page4*/
|
|
||||||
{0x01400000, SDRAM_IGENERIC}, /*SDRAM_Page5*/
|
|
||||||
{0x01800000, SDRAM_IGENERIC}, /*SDRAM_Page6*/
|
|
||||||
{0x01C00000, SDRAM_IGENERIC}, /*SDRAM_Page7*/
|
|
||||||
{0x02000000, SDRAM_IGENERIC}, /*SDRAM_Page8*/
|
|
||||||
{0x02400000, SDRAM_IGENERIC}, /*SDRAM_Page9*/
|
|
||||||
{0x02800000, SDRAM_IGENERIC}, /*SDRAM_Page10*/
|
|
||||||
{0x02C00000, SDRAM_IGENERIC}, /*SDRAM_Page11*/
|
|
||||||
{0x03000000, SDRAM_IGENERIC}, /*SDRAM_Page12*/
|
|
||||||
{0x03400000, SDRAM_IGENERIC}, /*SDRAM_Page13*/
|
|
||||||
};
|
|
||||||
|
|
||||||
static unsigned int dcplb_table[16][2]={
|
|
||||||
{0xFFA00000,L1_DMEMORY},
|
|
||||||
{0x00000000,SDRAM_DKERNEL}, /*SDRAM_Page1*/
|
|
||||||
{0x00400000,SDRAM_DKERNEL}, /*SDRAM_Page1*/
|
|
||||||
{0x07C00000,SDRAM_DKERNEL}, /*SDRAM_Page15*/
|
|
||||||
{0x00800000,SDRAM_DGENERIC}, /*SDRAM_Page2*/
|
|
||||||
{0x00C00000,SDRAM_DGENERIC}, /*SDRAM_Page3*/
|
|
||||||
{0x01000000,SDRAM_DGENERIC}, /*SDRAM_Page4*/
|
|
||||||
{0x01400000,SDRAM_DGENERIC}, /*SDRAM_Page5*/
|
|
||||||
{0x01800000,SDRAM_DGENERIC}, /*SDRAM_Page6*/
|
|
||||||
{0x01C00000,SDRAM_DGENERIC}, /*SDRAM_Page7*/
|
|
||||||
{0x02000000,SDRAM_DGENERIC}, /*SDRAM_Page8*/
|
|
||||||
{0x02400000,SDRAM_DGENERIC}, /*SDRAM_Page9*/
|
|
||||||
{0x02800000,SDRAM_DGENERIC}, /*SDRAM_Page10*/
|
|
||||||
{0x02C00000,SDRAM_DGENERIC}, /*SDRAM_Page11*/
|
|
||||||
{0x03000000,SDRAM_DGENERIC}, /*SDRAM_Page12*/
|
|
||||||
{0x20000000,SDRAM_EBIU}, /*For Network */
|
|
||||||
};
|
|
||||||
|
|
||||||
int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
|
int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
|
||||||
{
|
{
|
||||||
__asm__ __volatile__
|
__asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_ISRAM)
|
||||||
("cli r3;"
|
|
||||||
"P0 = %0;"
|
|
||||||
"JUMP (P0);"
|
|
||||||
:
|
|
||||||
: "r" (L1_ISRAM)
|
|
||||||
);
|
);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
|
@ -113,28 +69,69 @@ int cleanup_before_linux(void)
|
||||||
void icache_enable(void)
|
void icache_enable(void)
|
||||||
{
|
{
|
||||||
unsigned int *I0, *I1;
|
unsigned int *I0, *I1;
|
||||||
int i;
|
int i, j = 0;
|
||||||
|
#ifdef __ADSPBF537__
|
||||||
|
if ((*pCHIPID >> 28) < 2)
|
||||||
|
return;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Before enable icache, disable it first */
|
||||||
|
icache_disable();
|
||||||
I0 = (unsigned int *)ICPLB_ADDR0;
|
I0 = (unsigned int *)ICPLB_ADDR0;
|
||||||
I1 = (unsigned int *)ICPLB_DATA0;
|
I1 = (unsigned int *)ICPLB_DATA0;
|
||||||
|
|
||||||
for(i=0;i<16;i++){
|
/* make sure the locked ones go in first */
|
||||||
|
for (i = 0; i < page_descriptor_table_size; i++) {
|
||||||
|
if (CPLB_LOCK & icplb_table[i][1]) {
|
||||||
|
pr_debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
|
||||||
|
icplb_table[i][0], icplb_table[i][1]);
|
||||||
*I0++ = icplb_table[i][0];
|
*I0++ = icplb_table[i][0];
|
||||||
*I1++ = icplb_table[i][1];
|
*I1++ = icplb_table[i][1];
|
||||||
|
j++;
|
||||||
}
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
for (i = 0; i < page_descriptor_table_size; i++) {
|
||||||
|
if (!(CPLB_LOCK & icplb_table[i][1])) {
|
||||||
|
pr_debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
|
||||||
|
icplb_table[i][0], icplb_table[i][1]);
|
||||||
|
*I0++ = icplb_table[i][0];
|
||||||
|
*I1++ = icplb_table[i][1];
|
||||||
|
j++;
|
||||||
|
if (j == 16) {
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Fill the rest with invalid entry */
|
||||||
|
if (j <= 15) {
|
||||||
|
for (; j <= 16; j++) {
|
||||||
|
pr_debug("filling %i with 0", j);
|
||||||
|
*I1++ = 0x0;
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
cli();
|
cli();
|
||||||
SSYNC();
|
__builtin_bfin_ssync();
|
||||||
|
asm(" .align 8; ");
|
||||||
*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
|
*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
|
||||||
SSYNC();
|
__builtin_bfin_ssync();
|
||||||
sti();
|
sti();
|
||||||
}
|
}
|
||||||
|
|
||||||
void icache_disable(void)
|
void icache_disable(void)
|
||||||
{
|
{
|
||||||
|
#ifdef __ADSPBF537__
|
||||||
|
if ((*pCHIPID >> 28) < 2)
|
||||||
|
return;
|
||||||
|
#endif
|
||||||
cli();
|
cli();
|
||||||
SSYNC();
|
__builtin_bfin_ssync();
|
||||||
|
asm(" .align 8; ");
|
||||||
*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
|
*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
|
||||||
SSYNC();
|
__builtin_bfin_ssync();
|
||||||
sti();
|
sti();
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -153,29 +150,82 @@ void dcache_enable(void)
|
||||||
{
|
{
|
||||||
unsigned int *I0, *I1;
|
unsigned int *I0, *I1;
|
||||||
unsigned int temp;
|
unsigned int temp;
|
||||||
int i;
|
int i, j = 0;
|
||||||
|
|
||||||
|
/* Before enable dcache, disable it first */
|
||||||
|
dcache_disable();
|
||||||
I0 = (unsigned int *)DCPLB_ADDR0;
|
I0 = (unsigned int *)DCPLB_ADDR0;
|
||||||
I1 = (unsigned int *)DCPLB_DATA0;
|
I1 = (unsigned int *)DCPLB_DATA0;
|
||||||
|
|
||||||
for(i=0;i<16;i++){
|
/* make sure the locked ones go in first */
|
||||||
|
for (i = 0; i < page_descriptor_table_size; i++) {
|
||||||
|
if (CPLB_LOCK & dcplb_table[i][1]) {
|
||||||
|
pr_debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
|
||||||
|
dcplb_table[i][0], dcplb_table[i][1]);
|
||||||
*I0++ = dcplb_table[i][0];
|
*I0++ = dcplb_table[i][0];
|
||||||
*I1++ = dcplb_table[i][1];
|
*I1++ = dcplb_table[i][1];
|
||||||
|
j++;
|
||||||
|
} else {
|
||||||
|
pr_debug("skip %02i %02i 0x%08x 0x%08x\n", i, j,
|
||||||
|
dcplb_table[i][0], dcplb_table[i][1]);
|
||||||
}
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
for (i = 0; i < page_descriptor_table_size; i++) {
|
||||||
|
if (!(CPLB_LOCK & dcplb_table[i][1])) {
|
||||||
|
pr_debug("adding %02i %02i 0x%08x 0x%08x\n", i, j,
|
||||||
|
dcplb_table[i][0], dcplb_table[i][1]);
|
||||||
|
*I0++ = dcplb_table[i][0];
|
||||||
|
*I1++ = dcplb_table[i][1];
|
||||||
|
j++;
|
||||||
|
if (j == 16) {
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Fill the rest with invalid entry */
|
||||||
|
if (j <= 15) {
|
||||||
|
for (; j <= 16; j++) {
|
||||||
|
pr_debug("filling %i with 0", j);
|
||||||
|
*I1++ = 0x0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
cli();
|
cli();
|
||||||
temp = *(unsigned int *)DMEM_CONTROL;
|
temp = *(unsigned int *)DMEM_CONTROL;
|
||||||
SSYNC();
|
__builtin_bfin_ssync();
|
||||||
*(unsigned int *)DMEM_CONTROL = ACACHE_BCACHE |ENDCPLB |PORT_PREF0|temp;
|
asm(" .align 8; ");
|
||||||
SSYNC();
|
*(unsigned int *)DMEM_CONTROL =
|
||||||
|
ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | temp;
|
||||||
|
__builtin_bfin_ssync();
|
||||||
sti();
|
sti();
|
||||||
}
|
}
|
||||||
|
|
||||||
void dcache_disable(void)
|
void dcache_disable(void)
|
||||||
{
|
{
|
||||||
|
|
||||||
|
unsigned int *I0, *I1;
|
||||||
|
int i;
|
||||||
|
|
||||||
cli();
|
cli();
|
||||||
SSYNC();
|
__builtin_bfin_ssync();
|
||||||
*(unsigned int *)DMEM_CONTROL &= ~(ACACHE_BCACHE |ENDCPLB |PORT_PREF0);
|
asm(" .align 8; ");
|
||||||
SSYNC();
|
*(unsigned int *)DMEM_CONTROL &=
|
||||||
|
~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
|
||||||
|
__builtin_bfin_ssync();
|
||||||
sti();
|
sti();
|
||||||
|
|
||||||
|
/* after disable dcache,
|
||||||
|
* clear it so we don't confuse the next application
|
||||||
|
*/
|
||||||
|
I0 = (unsigned int *)DCPLB_ADDR0;
|
||||||
|
I1 = (unsigned int *)DCPLB_DATA0;
|
||||||
|
|
||||||
|
for (i = 0; i < 16; i++) {
|
||||||
|
*I0++ = 0x0;
|
||||||
|
*I1++ = 0x0;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
int dcache_status(void)
|
int dcache_status(void)
|
||||||
|
|
|
@ -60,6 +60,7 @@ void blackfin_disable_irq(unsigned int irq);
|
||||||
extern int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]);
|
extern int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]);
|
||||||
int blackfin_request_irq(unsigned int irq,
|
int blackfin_request_irq(unsigned int irq,
|
||||||
void (*handler) (int, void *, struct pt_regs *),
|
void (*handler) (int, void *, struct pt_regs *),
|
||||||
unsigned long flags,const char *devname,void *dev_id);
|
unsigned long flags, const char *devname,
|
||||||
|
void *dev_id);
|
||||||
void timer_init(void);
|
void timer_init(void);
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -3,13 +3,12 @@
|
||||||
*
|
*
|
||||||
* This file is subject to the terms and conditions of the GNU General Public
|
* This file is subject to the terms and conditions of the GNU General Public
|
||||||
* License.
|
* License.
|
||||||
*
|
|
||||||
* Blackfin BF533/2.6 support : LG Soft India
|
|
||||||
*/
|
*/
|
||||||
#define ASSEMBLY
|
#define ASSEMBLY
|
||||||
|
|
||||||
#include <asm/linkage.h>
|
#include <asm/linkage.h>
|
||||||
#include <asm/cplb.h>
|
#include <asm/cplb.h>
|
||||||
|
#include <config.h>
|
||||||
#include <asm/blackfin.h>
|
#include <asm/blackfin.h>
|
||||||
|
|
||||||
.text
|
.text
|
||||||
|
@ -20,7 +19,7 @@
|
||||||
* in the instruction cache.
|
* in the instruction cache.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
ENTRY(flush_instruction_cache)
|
ENTRY(_flush_instruction_cache)
|
||||||
[--SP] = ( R7:6, P5:4 );
|
[--SP] = ( R7:6, P5:4 );
|
||||||
LINK 12;
|
LINK 12;
|
||||||
SP += -12;
|
SP += -12;
|
||||||
|
@ -33,7 +32,7 @@ ENTRY(flush_instruction_cache)
|
||||||
inext: R0 = [P5++];
|
inext: R0 = [P5++];
|
||||||
R1 = [P4++];
|
R1 = [P4++];
|
||||||
[--SP] = RETS;
|
[--SP] = RETS;
|
||||||
CALL icplb_flush; /* R0 = page, R1 = data*/
|
CALL _icplb_flush; /* R0 = page, R1 = data*/
|
||||||
RETS = [SP++];
|
RETS = [SP++];
|
||||||
iskip: R6 += -1;
|
iskip: R6 += -1;
|
||||||
CC = R6;
|
CC = R6;
|
||||||
|
@ -52,7 +51,7 @@ iskip: R6 += -1;
|
||||||
*/
|
*/
|
||||||
|
|
||||||
.align 2
|
.align 2
|
||||||
ENTRY(icplb_flush)
|
ENTRY(_icplb_flush)
|
||||||
[--SP] = ( R7:0, P5:0 );
|
[--SP] = ( R7:0, P5:0 );
|
||||||
[--SP] = LC0;
|
[--SP] = LC0;
|
||||||
[--SP] = LT0;
|
[--SP] = LT0;
|
||||||
|
@ -88,8 +87,9 @@ ENTRY(icplb_flush)
|
||||||
R3 = ((12<<8)|2); /* Extraction pattern */
|
R3 = ((12<<8)|2); /* Extraction pattern */
|
||||||
nop; /* Anamoly 05000209 */
|
nop; /* Anamoly 05000209 */
|
||||||
R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits */
|
R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits */
|
||||||
R3.H = R4.L << 0 ; /* Save in extraction pattern for later deposit.*/
|
|
||||||
|
|
||||||
|
/* Save in extraction pattern for later deposit. */
|
||||||
|
R3.H = R4.L << 0;
|
||||||
|
|
||||||
/* So:
|
/* So:
|
||||||
* R0 = Page start
|
* R0 = Page start
|
||||||
|
@ -191,7 +191,7 @@ ieall: NOP;
|
||||||
* in the data cache.
|
* in the data cache.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
ENTRY(flush_data_cache)
|
ENTRY(_flush_data_cache)
|
||||||
[--SP] = ( R7:6, P5:4 );
|
[--SP] = ( R7:6, P5:4 );
|
||||||
LINK 12;
|
LINK 12;
|
||||||
SP += -12;
|
SP += -12;
|
||||||
|
@ -209,7 +209,7 @@ next: R0 = [P5++];
|
||||||
CC = R2;
|
CC = R2;
|
||||||
IF !CC JUMP skip; /* If not, ignore it.*/
|
IF !CC JUMP skip; /* If not, ignore it.*/
|
||||||
[--SP] = RETS;
|
[--SP] = RETS;
|
||||||
CALL dcplb_flush; /* R0 = page, R1 = data*/
|
CALL _dcplb_flush; /* R0 = page, R1 = data*/
|
||||||
RETS = [SP++];
|
RETS = [SP++];
|
||||||
skip: R6 += -1;
|
skip: R6 += -1;
|
||||||
CC = R6;
|
CC = R6;
|
||||||
|
@ -228,7 +228,7 @@ skip: R6 += -1;
|
||||||
*/
|
*/
|
||||||
|
|
||||||
.align 2
|
.align 2
|
||||||
ENTRY(dcplb_flush)
|
ENTRY(_dcplb_flush)
|
||||||
[--SP] = ( R7:0, P5:0 );
|
[--SP] = ( R7:0, P5:0 );
|
||||||
[--SP] = LC0;
|
[--SP] = LC0;
|
||||||
[--SP] = LT0;
|
[--SP] = LT0;
|
||||||
|
@ -290,7 +290,8 @@ bank_chosen:
|
||||||
R3 = ((12<<8)|2); /* Extraction pattern */
|
R3 = ((12<<8)|2); /* Extraction pattern */
|
||||||
nop; /*Anamoly 05000209*/
|
nop; /*Anamoly 05000209*/
|
||||||
R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits*/
|
R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits*/
|
||||||
R3.H = R4.L << 0 ; /* Save in extraction pattern for later deposit.*/
|
/* Save in extraction pattern for later deposit.*/
|
||||||
|
R3.H = R4.L << 0;
|
||||||
|
|
||||||
/* So:
|
/* So:
|
||||||
* R0 = Page start
|
* R0 = Page start
|
||||||
|
|
|
@ -0,0 +1,180 @@
|
||||||
|
#define ASSEMBLY
|
||||||
|
|
||||||
|
#include <linux/config.h>
|
||||||
|
#include <config.h>
|
||||||
|
#include <asm/blackfin.h>
|
||||||
|
#include <asm/mem_init.h>
|
||||||
|
.global init_sdram;
|
||||||
|
|
||||||
|
#if (CONFIG_CCLK_DIV == 1)
|
||||||
|
#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
|
||||||
|
#endif
|
||||||
|
#if (CONFIG_CCLK_DIV == 2)
|
||||||
|
#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
|
||||||
|
#endif
|
||||||
|
#if (CONFIG_CCLK_DIV == 4)
|
||||||
|
#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
|
||||||
|
#endif
|
||||||
|
#if (CONFIG_CCLK_DIV == 8)
|
||||||
|
#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
|
||||||
|
#endif
|
||||||
|
#ifndef CONFIG_CCLK_ACT_DIV
|
||||||
|
#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
|
||||||
|
#endif
|
||||||
|
|
||||||
|
init_sdram:
|
||||||
|
[--SP] = ASTAT;
|
||||||
|
[--SP] = RETS;
|
||||||
|
[--SP] = (R7:0);
|
||||||
|
[--SP] = (P5:0);
|
||||||
|
|
||||||
|
#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
|
||||||
|
p0.h = hi(SPI_BAUD);
|
||||||
|
p0.l = lo(SPI_BAUD);
|
||||||
|
r0.l = CONFIG_SPI_BAUD;
|
||||||
|
w[p0] = r0.l;
|
||||||
|
SSYNC;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
|
||||||
|
*/
|
||||||
|
p0.h = hi(PLL_LOCKCNT);
|
||||||
|
p0.l = lo(PLL_LOCKCNT);
|
||||||
|
r0 = 0x300(Z);
|
||||||
|
w[p0] = r0.l;
|
||||||
|
ssync;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Put SDRAM in self-refresh, incase anything is running
|
||||||
|
*/
|
||||||
|
P2.H = hi(EBIU_SDGCTL);
|
||||||
|
P2.L = lo(EBIU_SDGCTL);
|
||||||
|
R0 = [P2];
|
||||||
|
BITSET (R0, 24);
|
||||||
|
[P2] = R0;
|
||||||
|
SSYNC;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Set PLL_CTL with the value that we calculate in R0
|
||||||
|
* - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
|
||||||
|
* - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
|
||||||
|
* - [7] = output delay (add 200ps of delay to mem signals)
|
||||||
|
* - [6] = input delay (add 200ps of input delay to mem signals)
|
||||||
|
* - [5] = PDWN : 1=All Clocks off
|
||||||
|
* - [3] = STOPCK : 1=Core Clock off
|
||||||
|
* - [1] = PLL_OFF : 1=Disable Power to PLL
|
||||||
|
* - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
|
||||||
|
* all other bits set to zero
|
||||||
|
*/
|
||||||
|
|
||||||
|
r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
|
||||||
|
r0 = r0 << 9; /* Shift it over, */
|
||||||
|
r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
|
||||||
|
r0 = r1 | r0;
|
||||||
|
r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
|
||||||
|
r1 = r1 << 8; /* Shift it over */
|
||||||
|
r0 = r1 | r0; /* add them all together */
|
||||||
|
|
||||||
|
p0.h = hi(PLL_CTL);
|
||||||
|
p0.l = lo(PLL_CTL); /* Load the address */
|
||||||
|
cli r2; /* Disable interrupts */
|
||||||
|
ssync;
|
||||||
|
w[p0] = r0.l; /* Set the value */
|
||||||
|
idle; /* Wait for the PLL to stablize */
|
||||||
|
sti r2; /* Enable interrupts */
|
||||||
|
|
||||||
|
check_again:
|
||||||
|
p0.h = hi(PLL_STAT);
|
||||||
|
p0.l = lo(PLL_STAT);
|
||||||
|
R0 = W[P0](Z);
|
||||||
|
CC = BITTST(R0,5);
|
||||||
|
if ! CC jump check_again;
|
||||||
|
|
||||||
|
/* Configure SCLK & CCLK Dividers */
|
||||||
|
r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
|
||||||
|
p0.h = hi(PLL_DIV);
|
||||||
|
p0.l = lo(PLL_DIV);
|
||||||
|
w[p0] = r0.l;
|
||||||
|
ssync;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* We now are running at speed, time to set the Async mem bank wait states
|
||||||
|
* This will speed up execution, since we are normally running from FLASH.
|
||||||
|
*/
|
||||||
|
|
||||||
|
p2.h = (EBIU_AMBCTL1 >> 16);
|
||||||
|
p2.l = (EBIU_AMBCTL1 & 0xFFFF);
|
||||||
|
r0.h = (AMBCTL1VAL >> 16);
|
||||||
|
r0.l = (AMBCTL1VAL & 0xFFFF);
|
||||||
|
[p2] = r0;
|
||||||
|
ssync;
|
||||||
|
|
||||||
|
p2.h = (EBIU_AMBCTL0 >> 16);
|
||||||
|
p2.l = (EBIU_AMBCTL0 & 0xFFFF);
|
||||||
|
r0.h = (AMBCTL0VAL >> 16);
|
||||||
|
r0.l = (AMBCTL0VAL & 0xFFFF);
|
||||||
|
[p2] = r0;
|
||||||
|
ssync;
|
||||||
|
|
||||||
|
p2.h = (EBIU_AMGCTL >> 16);
|
||||||
|
p2.l = (EBIU_AMGCTL & 0xffff);
|
||||||
|
r0 = AMGCTLVAL;
|
||||||
|
w[p2] = r0;
|
||||||
|
ssync;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Now, Initialize the SDRAM,
|
||||||
|
* start with the SDRAM Refresh Rate Control Register
|
||||||
|
*/
|
||||||
|
p0.l = lo(EBIU_SDRRC);
|
||||||
|
p0.h = hi(EBIU_SDRRC);
|
||||||
|
r0 = mem_SDRRC;
|
||||||
|
w[p0] = r0.l;
|
||||||
|
ssync;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SDRAM Memory Bank Control Register - bank specific parameters
|
||||||
|
*/
|
||||||
|
p0.l = (EBIU_SDBCTL & 0xFFFF);
|
||||||
|
p0.h = (EBIU_SDBCTL >> 16);
|
||||||
|
r0 = mem_SDBCTL;
|
||||||
|
w[p0] = r0.l;
|
||||||
|
ssync;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SDRAM Global Control Register - global programmable parameters
|
||||||
|
* Disable self-refresh
|
||||||
|
*/
|
||||||
|
P2.H = hi(EBIU_SDGCTL);
|
||||||
|
P2.L = lo(EBIU_SDGCTL);
|
||||||
|
R0 = [P2];
|
||||||
|
BITCLR (R0, 24);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Check if SDRAM is already powered up, if it is, enable self-refresh
|
||||||
|
*/
|
||||||
|
p0.h = hi(EBIU_SDSTAT);
|
||||||
|
p0.l = lo(EBIU_SDSTAT);
|
||||||
|
r2.l = w[p0];
|
||||||
|
cc = bittst(r2,3);
|
||||||
|
if !cc jump skip;
|
||||||
|
NOP;
|
||||||
|
BITSET (R0, 23);
|
||||||
|
skip:
|
||||||
|
[P2] = R0;
|
||||||
|
SSYNC;
|
||||||
|
|
||||||
|
/* Write in the new value in the register */
|
||||||
|
R0.L = lo(mem_SDGCTL);
|
||||||
|
R0.H = hi(mem_SDGCTL);
|
||||||
|
[P2] = R0;
|
||||||
|
SSYNC;
|
||||||
|
nop;
|
||||||
|
|
||||||
|
(P5:0) = [SP++];
|
||||||
|
(R7:0) = [SP++];
|
||||||
|
RETS = [SP++];
|
||||||
|
ASTAT = [SP++];
|
||||||
|
RTS;
|
||||||
|
|
|
@ -0,0 +1,181 @@
|
||||||
|
#define ASSEMBLY
|
||||||
|
|
||||||
|
#include <linux/config.h>
|
||||||
|
#include <config.h>
|
||||||
|
#include <asm/blackfin.h>
|
||||||
|
#include <asm/mem_init.h>
|
||||||
|
.global init_sdram;
|
||||||
|
|
||||||
|
#if (CONFIG_CCLK_DIV == 1)
|
||||||
|
#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
|
||||||
|
#endif
|
||||||
|
#if (CONFIG_CCLK_DIV == 2)
|
||||||
|
#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
|
||||||
|
#endif
|
||||||
|
#if (CONFIG_CCLK_DIV == 4)
|
||||||
|
#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
|
||||||
|
#endif
|
||||||
|
#if (CONFIG_CCLK_DIV == 8)
|
||||||
|
#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
|
||||||
|
#endif
|
||||||
|
#ifndef CONFIG_CCLK_ACT_DIV
|
||||||
|
#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
|
||||||
|
#endif
|
||||||
|
|
||||||
|
init_sdram:
|
||||||
|
[--SP] = ASTAT;
|
||||||
|
[--SP] = RETS;
|
||||||
|
[--SP] = (R7:0);
|
||||||
|
[--SP] = (P5:0);
|
||||||
|
|
||||||
|
#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
|
||||||
|
p0.h = hi(SPI_BAUD);
|
||||||
|
p0.l = lo(SPI_BAUD);
|
||||||
|
r0.l = CONFIG_SPI_BAUD_INITBLOCK;
|
||||||
|
w[p0] = r0.l;
|
||||||
|
SSYNC;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
|
||||||
|
*/
|
||||||
|
p0.h = hi(PLL_LOCKCNT);
|
||||||
|
p0.l = lo(PLL_LOCKCNT);
|
||||||
|
r0 = 0x300(Z);
|
||||||
|
w[p0] = r0.l;
|
||||||
|
ssync;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Put SDRAM in self-refresh, incase anything is running
|
||||||
|
*/
|
||||||
|
P2.H = hi(EBIU_SDGCTL);
|
||||||
|
P2.L = lo(EBIU_SDGCTL);
|
||||||
|
R0 = [P2];
|
||||||
|
BITSET (R0, 24);
|
||||||
|
[P2] = R0;
|
||||||
|
SSYNC;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Set PLL_CTL with the value that we calculate in R0
|
||||||
|
* - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
|
||||||
|
* - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
|
||||||
|
* - [7] = output delay (add 200ps of delay to mem signals)
|
||||||
|
* - [6] = input delay (add 200ps of input delay to mem signals)
|
||||||
|
* - [5] = PDWN : 1=All Clocks off
|
||||||
|
* - [3] = STOPCK : 1=Core Clock off
|
||||||
|
* - [1] = PLL_OFF : 1=Disable Power to PLL
|
||||||
|
* - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
|
||||||
|
* all other bits set to zero
|
||||||
|
*/
|
||||||
|
|
||||||
|
r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
|
||||||
|
r0 = r0 << 9; /* Shift it over, */
|
||||||
|
r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
|
||||||
|
r0 = r1 | r0;
|
||||||
|
r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
|
||||||
|
r1 = r1 << 8; /* Shift it over */
|
||||||
|
r0 = r1 | r0; /* add them all together */
|
||||||
|
|
||||||
|
p0.h = hi(PLL_CTL);
|
||||||
|
p0.l = lo(PLL_CTL); /* Load the address */
|
||||||
|
cli r2; /* Disable interrupts */
|
||||||
|
ssync;
|
||||||
|
w[p0] = r0.l; /* Set the value */
|
||||||
|
idle; /* Wait for the PLL to stablize */
|
||||||
|
sti r2; /* Enable interrupts */
|
||||||
|
|
||||||
|
check_again:
|
||||||
|
p0.h = hi(PLL_STAT);
|
||||||
|
p0.l = lo(PLL_STAT);
|
||||||
|
R0 = W[P0](Z);
|
||||||
|
CC = BITTST(R0,5);
|
||||||
|
if ! CC jump check_again;
|
||||||
|
|
||||||
|
/* Configure SCLK & CCLK Dividers */
|
||||||
|
r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
|
||||||
|
p0.h = hi(PLL_DIV);
|
||||||
|
p0.l = lo(PLL_DIV);
|
||||||
|
w[p0] = r0.l;
|
||||||
|
ssync;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* We now are running at speed, time to set the Async mem bank wait states
|
||||||
|
* This will speed up execution, since we are normally running from FLASH.
|
||||||
|
*/
|
||||||
|
|
||||||
|
p2.h = (EBIU_AMBCTL1 >> 16);
|
||||||
|
p2.l = (EBIU_AMBCTL1 & 0xFFFF);
|
||||||
|
r0.h = (AMBCTL1VAL >> 16);
|
||||||
|
r0.l = (AMBCTL1VAL & 0xFFFF);
|
||||||
|
[p2] = r0;
|
||||||
|
ssync;
|
||||||
|
|
||||||
|
p2.h = (EBIU_AMBCTL0 >> 16);
|
||||||
|
p2.l = (EBIU_AMBCTL0 & 0xFFFF);
|
||||||
|
r0.h = (AMBCTL0VAL >> 16);
|
||||||
|
r0.l = (AMBCTL0VAL & 0xFFFF);
|
||||||
|
[p2] = r0;
|
||||||
|
ssync;
|
||||||
|
|
||||||
|
p2.h = (EBIU_AMGCTL >> 16);
|
||||||
|
p2.l = (EBIU_AMGCTL & 0xffff);
|
||||||
|
r0 = AMGCTLVAL;
|
||||||
|
w[p2] = r0;
|
||||||
|
ssync;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Now, Initialize the SDRAM,
|
||||||
|
* start with the SDRAM Refresh Rate Control Register
|
||||||
|
*/
|
||||||
|
p0.l = lo(EBIU_SDRRC);
|
||||||
|
p0.h = hi(EBIU_SDRRC);
|
||||||
|
r0 = mem_SDRRC;
|
||||||
|
w[p0] = r0.l;
|
||||||
|
ssync;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SDRAM Memory Bank Control Register - bank specific parameters
|
||||||
|
*/
|
||||||
|
p0.l = (EBIU_SDBCTL & 0xFFFF);
|
||||||
|
p0.h = (EBIU_SDBCTL >> 16);
|
||||||
|
r0 = mem_SDBCTL;
|
||||||
|
w[p0] = r0.l;
|
||||||
|
ssync;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SDRAM Global Control Register - global programmable parameters
|
||||||
|
* Disable self-refresh
|
||||||
|
*/
|
||||||
|
P2.H = hi(EBIU_SDGCTL);
|
||||||
|
P2.L = lo(EBIU_SDGCTL);
|
||||||
|
R0 = [P2];
|
||||||
|
BITCLR (R0, 24);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Check if SDRAM is already powered up, if it is, enable self-refresh
|
||||||
|
*/
|
||||||
|
p0.h = hi(EBIU_SDSTAT);
|
||||||
|
p0.l = lo(EBIU_SDSTAT);
|
||||||
|
r2.l = w[p0];
|
||||||
|
cc = bittst(r2,3);
|
||||||
|
if !cc jump skip;
|
||||||
|
NOP;
|
||||||
|
BITSET (R0, 23);
|
||||||
|
skip:
|
||||||
|
[P2] = R0;
|
||||||
|
SSYNC;
|
||||||
|
|
||||||
|
/* Write in the new value in the register */
|
||||||
|
R0.L = lo(mem_SDGCTL);
|
||||||
|
R0.H = hi(mem_SDGCTL);
|
||||||
|
[P2] = R0;
|
||||||
|
SSYNC;
|
||||||
|
nop;
|
||||||
|
|
||||||
|
|
||||||
|
(P5:0) = [SP++];
|
||||||
|
(R7:0) = [SP++];
|
||||||
|
RETS = [SP++];
|
||||||
|
ASTAT = [SP++];
|
||||||
|
RTS;
|
||||||
|
|
|
@ -40,203 +40,58 @@
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#define ASSEMBLY
|
#define ASSEMBLY
|
||||||
|
#include <config.h>
|
||||||
|
#include <asm/blackfin.h>
|
||||||
#include <asm/hw_irq.h>
|
#include <asm/hw_irq.h>
|
||||||
#include <asm/entry.h>
|
#include <asm/entry.h>
|
||||||
#include <asm/blackfin_defs.h>
|
#include <asm/blackfin_defs.h>
|
||||||
#include <asm/cpu/bf533_irq.h>
|
|
||||||
|
|
||||||
.global blackfin_irq_panic;
|
.global _blackfin_irq_panic;
|
||||||
|
|
||||||
.text
|
.text
|
||||||
.align 2
|
.align 2
|
||||||
|
|
||||||
#ifndef CONFIG_KGDB
|
#ifndef CONFIG_KGDB
|
||||||
.global evt_emulation
|
.global _evt_emulation
|
||||||
evt_emulation:
|
_evt_emulation:
|
||||||
SAVE_CONTEXT
|
SAVE_CONTEXT
|
||||||
r0 = IRQ_EMU;
|
r0 = IRQ_EMU;
|
||||||
r1 = seqstat;
|
r1 = seqstat;
|
||||||
sp += -12;
|
sp += -12;
|
||||||
call blackfin_irq_panic;
|
call _blackfin_irq_panic;
|
||||||
sp += 12;
|
sp += 12;
|
||||||
rte;
|
rte;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
.global evt_nmi
|
.global _evt_nmi
|
||||||
evt_nmi:
|
_evt_nmi:
|
||||||
SAVE_CONTEXT
|
SAVE_CONTEXT
|
||||||
r0 = IRQ_NMI;
|
r0 = IRQ_NMI;
|
||||||
r1 = RETN;
|
r1 = RETN;
|
||||||
sp += -12;
|
sp += -12;
|
||||||
call blackfin_irq_panic;
|
call _blackfin_irq_panic;
|
||||||
sp += 12;
|
sp += 12;
|
||||||
|
|
||||||
_evt_nmi_exit:
|
_evt_nmi_exit:
|
||||||
rtn;
|
rtn;
|
||||||
|
|
||||||
.global trap
|
.global _trap
|
||||||
trap:
|
_trap:
|
||||||
[--sp] = r0;
|
SAVE_ALL_SYS
|
||||||
[--sp] = r1;
|
r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
|
||||||
[--sp] = p0;
|
sp += -12;
|
||||||
[--sp] = p1;
|
call _trap_c
|
||||||
[--sp] = astat;
|
sp += 12;
|
||||||
r0 = seqstat;
|
RESTORE_ALL_SYS
|
||||||
R0 <<= 26;
|
rtx;
|
||||||
R0 >>= 26;
|
|
||||||
p0 = r0;
|
|
||||||
p1.l = EVTABLE;
|
|
||||||
p1.h = EVTABLE;
|
|
||||||
p0 = p1 + (p0 << 1);
|
|
||||||
r1 = W[p0] (Z);
|
|
||||||
p1 = r1;
|
|
||||||
jump (pc + p1);
|
|
||||||
|
|
||||||
.global _EVENT1
|
.global _evt_rst
|
||||||
_EVENT1:
|
_evt_rst:
|
||||||
RAISE 14;
|
|
||||||
JUMP.S _EXIT;
|
|
||||||
|
|
||||||
.global _EVENT2
|
|
||||||
_EVENT2:
|
|
||||||
RAISE 14;
|
|
||||||
JUMP.S _EXIT;
|
|
||||||
|
|
||||||
.global _EVENT3
|
|
||||||
_EVENT3:
|
|
||||||
RAISE 14;
|
|
||||||
JUMP.S _EXIT;
|
|
||||||
|
|
||||||
.global _EVENT4
|
|
||||||
_EVENT4:
|
|
||||||
RAISE 14;
|
|
||||||
JUMP.S _EXIT;
|
|
||||||
|
|
||||||
.global _EVENT5
|
|
||||||
_EVENT5:
|
|
||||||
RAISE 14;
|
|
||||||
JUMP.S _EXIT;
|
|
||||||
|
|
||||||
.global _EVENT6
|
|
||||||
_EVENT6:
|
|
||||||
RAISE 14;
|
|
||||||
JUMP.S _EXIT;
|
|
||||||
|
|
||||||
.global _EVENT7
|
|
||||||
_EVENT7:
|
|
||||||
RAISE 15;
|
|
||||||
JUMP.S _EXIT;
|
|
||||||
|
|
||||||
.global _EVENT8
|
|
||||||
_EVENT8:
|
|
||||||
RAISE 14;
|
|
||||||
JUMP.S _EXIT;
|
|
||||||
|
|
||||||
.global _EVENT9
|
|
||||||
_EVENT9:
|
|
||||||
RAISE 14;
|
|
||||||
JUMP.S _EXIT;
|
|
||||||
|
|
||||||
.global _EVENT10
|
|
||||||
_EVENT10:
|
|
||||||
RAISE 14;
|
|
||||||
JUMP.S _EXIT;
|
|
||||||
|
|
||||||
.global _EVENT11
|
|
||||||
_EVENT11:
|
|
||||||
RAISE 14;
|
|
||||||
JUMP.S _EXIT;
|
|
||||||
|
|
||||||
.global _EVENT12
|
|
||||||
_EVENT12:
|
|
||||||
RAISE 14;
|
|
||||||
JUMP.S _EXIT;
|
|
||||||
|
|
||||||
.global _EVENT13
|
|
||||||
_EVENT13:
|
|
||||||
RAISE 14;
|
|
||||||
JUMP.S _EXIT;
|
|
||||||
|
|
||||||
.global _EVENT14
|
|
||||||
_EVENT14:
|
|
||||||
/* RAISE 14; */
|
|
||||||
CALL _cplb_hdr;
|
|
||||||
JUMP.S _EXIT;
|
|
||||||
|
|
||||||
.global _EVENT19
|
|
||||||
_EVENT19:
|
|
||||||
RAISE 14;
|
|
||||||
JUMP.S _EXIT;
|
|
||||||
|
|
||||||
.global _EVENT20
|
|
||||||
_EVENT20:
|
|
||||||
RAISE 14;
|
|
||||||
JUMP.S _EXIT;
|
|
||||||
|
|
||||||
.global _EVENT21
|
|
||||||
_EVENT21:
|
|
||||||
RAISE 14;
|
|
||||||
JUMP.S _EXIT;
|
|
||||||
|
|
||||||
.global _EXIT
|
|
||||||
_EXIT:
|
|
||||||
ASTAT = [sp++];
|
|
||||||
p1 = [sp++];
|
|
||||||
p0 = [sp++];
|
|
||||||
r1 = [sp++];
|
|
||||||
r0 = [sp++];
|
|
||||||
RTX;
|
|
||||||
|
|
||||||
EVTABLE:
|
|
||||||
.byte2 0x0000;
|
|
||||||
.byte2 0x0000;
|
|
||||||
.byte2 0x0000;
|
|
||||||
.byte2 0x0000;
|
|
||||||
.byte2 0x0000;
|
|
||||||
.byte2 0x0000;
|
|
||||||
.byte2 0x0000;
|
|
||||||
.byte2 0x0000;
|
|
||||||
.byte2 0x0000;
|
|
||||||
.byte2 0x0000;
|
|
||||||
.byte2 0x0000;
|
|
||||||
.byte2 0x0000;
|
|
||||||
.byte2 0x0000;
|
|
||||||
.byte2 0x0000;
|
|
||||||
.byte2 0x0000;
|
|
||||||
.byte2 0x0000;
|
|
||||||
.byte2 0x003E;
|
|
||||||
.byte2 0x0042;
|
|
||||||
.byte4 0x0000;
|
|
||||||
.byte4 0x0000;
|
|
||||||
.byte4 0x0000;
|
|
||||||
.byte4 0x0000;
|
|
||||||
.byte4 0x0000;
|
|
||||||
.byte4 0x0000;
|
|
||||||
.byte4 0x0000;
|
|
||||||
.byte2 0x0000;
|
|
||||||
.byte2 0x001E;
|
|
||||||
.byte2 0x0022;
|
|
||||||
.byte2 0x0032;
|
|
||||||
.byte2 0x002e;
|
|
||||||
.byte2 0x0002;
|
|
||||||
.byte2 0x0036;
|
|
||||||
.byte2 0x002A;
|
|
||||||
.byte2 0x001A;
|
|
||||||
.byte2 0x0016;
|
|
||||||
.byte2 0x000A;
|
|
||||||
.byte2 0x000E;
|
|
||||||
.byte2 0x0012;
|
|
||||||
.byte2 0x0006;
|
|
||||||
.byte2 0x0026;
|
|
||||||
|
|
||||||
.global evt_rst
|
|
||||||
evt_rst:
|
|
||||||
SAVE_CONTEXT
|
SAVE_CONTEXT
|
||||||
r0 = IRQ_RST;
|
r0 = IRQ_RST;
|
||||||
r1 = RETN;
|
r1 = RETN;
|
||||||
sp += -12;
|
sp += -12;
|
||||||
call do_reset;
|
call _do_reset;
|
||||||
sp += 12;
|
sp += 12;
|
||||||
|
|
||||||
_evt_rst_exit:
|
_evt_rst_exit:
|
||||||
|
@ -246,19 +101,19 @@ irq_panic:
|
||||||
r0 = IRQ_EVX;
|
r0 = IRQ_EVX;
|
||||||
r1 = sp;
|
r1 = sp;
|
||||||
sp += -12;
|
sp += -12;
|
||||||
call blackfin_irq_panic;
|
call _blackfin_irq_panic;
|
||||||
sp += 12;
|
sp += 12;
|
||||||
|
|
||||||
.global evt_ivhw
|
.global _evt_ivhw
|
||||||
evt_ivhw:
|
_evt_ivhw:
|
||||||
SAVE_CONTEXT
|
SAVE_CONTEXT
|
||||||
RAISE 14;
|
RAISE 14;
|
||||||
|
|
||||||
_evt_ivhw_exit:
|
_evt_ivhw_exit:
|
||||||
rti;
|
rti;
|
||||||
|
|
||||||
.global evt_timer
|
.global _evt_timer
|
||||||
evt_timer:
|
_evt_timer:
|
||||||
SAVE_CONTEXT
|
SAVE_CONTEXT
|
||||||
r0 = IRQ_CORETMR;
|
r0 = IRQ_CORETMR;
|
||||||
sp += -12;
|
sp += -12;
|
||||||
|
@ -269,91 +124,91 @@ evt_timer:
|
||||||
rti;
|
rti;
|
||||||
nop;
|
nop;
|
||||||
|
|
||||||
.global evt_evt7
|
.global _evt_evt7
|
||||||
evt_evt7:
|
_evt_evt7:
|
||||||
SAVE_CONTEXT
|
SAVE_CONTEXT
|
||||||
r0 = 7;
|
r0 = 7;
|
||||||
sp += -12;
|
sp += -12;
|
||||||
call process_int;
|
call _process_int;
|
||||||
sp += 12;
|
sp += 12;
|
||||||
|
|
||||||
evt_evt7_exit:
|
evt_evt7_exit:
|
||||||
RESTORE_CONTEXT
|
RESTORE_CONTEXT
|
||||||
rti;
|
rti;
|
||||||
|
|
||||||
.global evt_evt8
|
.global _evt_evt8
|
||||||
evt_evt8:
|
_evt_evt8:
|
||||||
SAVE_CONTEXT
|
SAVE_CONTEXT
|
||||||
r0 = 8;
|
r0 = 8;
|
||||||
sp += -12;
|
sp += -12;
|
||||||
call process_int;
|
call _process_int;
|
||||||
sp += 12;
|
sp += 12;
|
||||||
|
|
||||||
evt_evt8_exit:
|
evt_evt8_exit:
|
||||||
RESTORE_CONTEXT
|
RESTORE_CONTEXT
|
||||||
rti;
|
rti;
|
||||||
|
|
||||||
.global evt_evt9
|
.global _evt_evt9
|
||||||
evt_evt9:
|
_evt_evt9:
|
||||||
SAVE_CONTEXT
|
SAVE_CONTEXT
|
||||||
r0 = 9;
|
r0 = 9;
|
||||||
sp += -12;
|
sp += -12;
|
||||||
call process_int;
|
call _process_int;
|
||||||
sp += 12;
|
sp += 12;
|
||||||
|
|
||||||
evt_evt9_exit:
|
evt_evt9_exit:
|
||||||
RESTORE_CONTEXT
|
RESTORE_CONTEXT
|
||||||
rti;
|
rti;
|
||||||
|
|
||||||
.global evt_evt10
|
.global _evt_evt10
|
||||||
evt_evt10:
|
_evt_evt10:
|
||||||
SAVE_CONTEXT
|
SAVE_CONTEXT
|
||||||
r0 = 10;
|
r0 = 10;
|
||||||
sp += -12;
|
sp += -12;
|
||||||
call process_int;
|
call _process_int;
|
||||||
sp += 12;
|
sp += 12;
|
||||||
|
|
||||||
evt_evt10_exit:
|
evt_evt10_exit:
|
||||||
RESTORE_CONTEXT
|
RESTORE_CONTEXT
|
||||||
rti;
|
rti;
|
||||||
|
|
||||||
.global evt_evt11
|
.global _evt_evt11
|
||||||
evt_evt11:
|
_evt_evt11:
|
||||||
SAVE_CONTEXT
|
SAVE_CONTEXT
|
||||||
r0 = 11;
|
r0 = 11;
|
||||||
sp += -12;
|
sp += -12;
|
||||||
call process_int;
|
call _process_int;
|
||||||
sp += 12;
|
sp += 12;
|
||||||
|
|
||||||
evt_evt11_exit:
|
evt_evt11_exit:
|
||||||
RESTORE_CONTEXT
|
RESTORE_CONTEXT
|
||||||
rti;
|
rti;
|
||||||
|
|
||||||
.global evt_evt12
|
.global _evt_evt12
|
||||||
evt_evt12:
|
_evt_evt12:
|
||||||
SAVE_CONTEXT
|
SAVE_CONTEXT
|
||||||
r0 = 12;
|
r0 = 12;
|
||||||
sp += -12;
|
sp += -12;
|
||||||
call process_int;
|
call _process_int;
|
||||||
sp += 12;
|
sp += 12;
|
||||||
evt_evt12_exit:
|
evt_evt12_exit:
|
||||||
RESTORE_CONTEXT
|
RESTORE_CONTEXT
|
||||||
rti;
|
rti;
|
||||||
|
|
||||||
.global evt_evt13
|
.global _evt_evt13
|
||||||
evt_evt13:
|
_evt_evt13:
|
||||||
SAVE_CONTEXT
|
SAVE_CONTEXT
|
||||||
r0 = 13;
|
r0 = 13;
|
||||||
sp += -12;
|
sp += -12;
|
||||||
call process_int;
|
call _process_int;
|
||||||
sp += 12;
|
sp += 12;
|
||||||
|
|
||||||
evt_evt13_exit:
|
evt_evt13_exit:
|
||||||
RESTORE_CONTEXT
|
RESTORE_CONTEXT
|
||||||
rti;
|
rti;
|
||||||
|
|
||||||
.global evt_system_call
|
.global _evt_system_call
|
||||||
evt_system_call:
|
_evt_system_call:
|
||||||
[--sp] = r0;
|
[--sp] = r0;
|
||||||
[--SP] = RETI;
|
[--SP] = RETI;
|
||||||
r0 = [sp++];
|
r0 = [sp++];
|
||||||
|
@ -363,7 +218,7 @@ evt_system_call:
|
||||||
r0 = [SP++];
|
r0 = [SP++];
|
||||||
SAVE_CONTEXT
|
SAVE_CONTEXT
|
||||||
sp += -12;
|
sp += -12;
|
||||||
call display_excp;
|
call _exception_handle;
|
||||||
sp += 12;
|
sp += 12;
|
||||||
RESTORE_CONTEXT
|
RESTORE_CONTEXT
|
||||||
RTI;
|
RTI;
|
||||||
|
@ -371,8 +226,8 @@ evt_system_call:
|
||||||
evt_system_call_exit:
|
evt_system_call_exit:
|
||||||
rti;
|
rti;
|
||||||
|
|
||||||
.global evt_soft_int1
|
.global _evt_soft_int1
|
||||||
evt_soft_int1:
|
_evt_soft_int1:
|
||||||
[--sp] = r0;
|
[--sp] = r0;
|
||||||
[--SP] = RETI;
|
[--SP] = RETI;
|
||||||
r0 = [sp++];
|
r0 = [sp++];
|
||||||
|
@ -382,7 +237,7 @@ evt_soft_int1:
|
||||||
r0 = [SP++];
|
r0 = [SP++];
|
||||||
SAVE_CONTEXT
|
SAVE_CONTEXT
|
||||||
sp += -12;
|
sp += -12;
|
||||||
call display_excp;
|
call _exception_handle;
|
||||||
sp += 12;
|
sp += 12;
|
||||||
RESTORE_CONTEXT
|
RESTORE_CONTEXT
|
||||||
RTI;
|
RTI;
|
||||||
|
|
|
@ -37,7 +37,8 @@
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <asm/machdep.h>
|
#include <asm/machdep.h>
|
||||||
#include <asm/irq.h>
|
#include <asm/irq.h>
|
||||||
#include <asm/cpu/defBF533.h>
|
#include <config.h>
|
||||||
|
#include <asm/blackfin.h>
|
||||||
#include "cpu.h"
|
#include "cpu.h"
|
||||||
|
|
||||||
static ulong timestamp;
|
static ulong timestamp;
|
||||||
|
@ -104,9 +105,9 @@ void udelay(unsigned long usec)
|
||||||
usec -= 1000;
|
usec -= 1000;
|
||||||
}
|
}
|
||||||
|
|
||||||
asm volatile (" %0 = CYCLES;": "=g"(start));
|
asm volatile (" %0 = CYCLES;":"=r" (start));
|
||||||
do {
|
do {
|
||||||
asm volatile (" %0 = CYCLES; ": "=g"(stop));
|
asm volatile (" %0 = CYCLES; ":"=r" (stop));
|
||||||
} while (stop - start < delay);
|
} while (stop - start < delay);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -146,9 +147,11 @@ ulong get_timer(ulong base)
|
||||||
/* Number of clocks elapsed */
|
/* Number of clocks elapsed */
|
||||||
ulong clocks = (MAX_TIM_LOAD - (*pTCOUNT));
|
ulong clocks = (MAX_TIM_LOAD - (*pTCOUNT));
|
||||||
|
|
||||||
/* Find if the TCOUNT is reset
|
/**
|
||||||
timestamp gives the number of times
|
* Find if the TCOUNT is reset
|
||||||
TCOUNT got reset */
|
* timestamp gives the number of times
|
||||||
|
* TCOUNT got reset
|
||||||
|
*/
|
||||||
if (clocks < last_time)
|
if (clocks < last_time)
|
||||||
timestamp++;
|
timestamp++;
|
||||||
last_time = clocks;
|
last_time = clocks;
|
||||||
|
@ -156,9 +159,10 @@ ulong get_timer(ulong base)
|
||||||
/* Get the number of milliseconds */
|
/* Get the number of milliseconds */
|
||||||
milisec = clocks / (CONFIG_CCLK_HZ / 1000);
|
milisec = clocks / (CONFIG_CCLK_HZ / 1000);
|
||||||
|
|
||||||
/* Find the number of millisonds
|
/**
|
||||||
that got elapsed before this TCOUNT
|
* Find the number of millisonds
|
||||||
cycle */
|
* that got elapsed before this TCOUNT cycle
|
||||||
|
*/
|
||||||
milisec += timestamp * (MAX_TIM_LOAD / (CONFIG_CCLK_HZ / 1000));
|
milisec += timestamp * (MAX_TIM_LOAD / (CONFIG_CCLK_HZ / 1000));
|
||||||
|
|
||||||
return (milisec - base);
|
return (milisec - base);
|
||||||
|
|
|
@ -101,6 +101,16 @@ void blackfin_init_IRQ(void)
|
||||||
asm("csync;");
|
asm("csync;");
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void exception_handle(void)
|
||||||
|
{
|
||||||
|
#if defined (CONFIG_PANIC_HANG)
|
||||||
|
display_excp();
|
||||||
|
#else
|
||||||
|
udelay(100000); /* allow messages to go out */
|
||||||
|
do_reset(NULL, 0, 0, NULL);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
void display_excp(void)
|
void display_excp(void)
|
||||||
{
|
{
|
||||||
printf("Exception!\n");
|
printf("Exception!\n");
|
||||||
|
|
|
@ -51,18 +51,17 @@
|
||||||
#include <asm/uaccess.h>
|
#include <asm/uaccess.h>
|
||||||
#include "bf533_serial.h"
|
#include "bf533_serial.h"
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
|
||||||
|
|
||||||
unsigned long pll_div_fact;
|
unsigned long pll_div_fact;
|
||||||
|
|
||||||
void calc_baud(void)
|
void calc_baud(void)
|
||||||
{
|
{
|
||||||
unsigned char i;
|
unsigned char i;
|
||||||
int temp;
|
int temp;
|
||||||
|
u_long sclk = get_sclk();
|
||||||
|
|
||||||
for (i = 0; i < sizeof(baud_table) / sizeof(int); i++) {
|
for (i = 0; i < sizeof(baud_table) / sizeof(int); i++) {
|
||||||
temp = CONFIG_SCLK_HZ/(baud_table[i]*8);
|
temp = sclk / (baud_table[i] * 8);
|
||||||
if ( temp && 0x1 == 1 ) {
|
if ((temp & 0x1) == 1) {
|
||||||
temp++;
|
temp++;
|
||||||
}
|
}
|
||||||
temp = temp / 2;
|
temp = temp / 2;
|
||||||
|
@ -74,6 +73,7 @@ void calc_baud(void)
|
||||||
void serial_setbrg(void)
|
void serial_setbrg(void)
|
||||||
{
|
{
|
||||||
int i;
|
int i;
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
calc_baud();
|
calc_baud();
|
||||||
|
|
||||||
|
@ -84,29 +84,29 @@ void serial_setbrg(void)
|
||||||
|
|
||||||
/* Enable UART */
|
/* Enable UART */
|
||||||
*pUART_GCTL |= UART_GCTL_UCEN;
|
*pUART_GCTL |= UART_GCTL_UCEN;
|
||||||
asm("ssync;");
|
__builtin_bfin_ssync();
|
||||||
|
|
||||||
/* Set DLAB in LCR to Access DLL and DLH */
|
/* Set DLAB in LCR to Access DLL and DLH */
|
||||||
ACCESS_LATCH;
|
ACCESS_LATCH;
|
||||||
asm("ssync;");
|
__builtin_bfin_ssync();
|
||||||
|
|
||||||
*pUART_DLL = hw_baud_table[i].dl_low;
|
*pUART_DLL = hw_baud_table[i].dl_low;
|
||||||
asm("ssync;");
|
__builtin_bfin_ssync();
|
||||||
*pUART_DLH = hw_baud_table[i].dl_high;
|
*pUART_DLH = hw_baud_table[i].dl_high;
|
||||||
asm("ssync;");
|
__builtin_bfin_ssync();
|
||||||
|
|
||||||
/* Clear DLAB in LCR to Access THR RBR IER */
|
/* Clear DLAB in LCR to Access THR RBR IER */
|
||||||
ACCESS_PORT_IER;
|
ACCESS_PORT_IER;
|
||||||
asm("ssync;");
|
__builtin_bfin_ssync();
|
||||||
|
|
||||||
/* Enable ERBFI and ELSI interrupts
|
/* Enable ERBFI and ELSI interrupts
|
||||||
* to poll SIC_ISR register*/
|
* to poll SIC_ISR register*/
|
||||||
*pUART_IER = UART_IER_ELSI | UART_IER_ERBFI | UART_IER_ETBEI;
|
*pUART_IER = UART_IER_ELSI | UART_IER_ERBFI | UART_IER_ETBEI;
|
||||||
asm("ssync;");
|
__builtin_bfin_ssync();
|
||||||
|
|
||||||
/* Set LCR to Word Lengh 8-bit word select */
|
/* Set LCR to Word Lengh 8-bit word select */
|
||||||
*pUART_LCR = UART_LCR_WLS8;
|
*pUART_LCR = UART_LCR_WLS8;
|
||||||
asm("ssync;");
|
__builtin_bfin_ssync();
|
||||||
|
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
@ -119,8 +119,7 @@ int serial_init(void)
|
||||||
|
|
||||||
void serial_putc(const char c)
|
void serial_putc(const char c)
|
||||||
{
|
{
|
||||||
if ((*pUART_LSR) & UART_LSR_TEMT)
|
if ((*pUART_LSR) & UART_LSR_TEMT) {
|
||||||
{
|
|
||||||
if (c == '\n')
|
if (c == '\n')
|
||||||
serial_putc('\r');
|
serial_putc('\r');
|
||||||
|
|
||||||
|
@ -148,7 +147,8 @@ int serial_getc(void)
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
/* Poll for RX Interrupt */
|
/* Poll for RX Interrupt */
|
||||||
while (!((isr_val = *(volatile unsigned long *)SIC_ISR) & IRQ_UART_RX_BIT));
|
while (!((isr_val =
|
||||||
|
*(volatile unsigned long *)SIC_ISR) & IRQ_UART_RX_BIT)) ;
|
||||||
asm("csync;");
|
asm("csync;");
|
||||||
|
|
||||||
uart_lsr_val = *pUART_LSR; /* Clear status bit */
|
uart_lsr_val = *pUART_LSR; /* Clear status bit */
|
||||||
|
@ -156,9 +156,7 @@ int serial_getc(void)
|
||||||
|
|
||||||
if (isr_val & IRQ_UART_ERROR_BIT) {
|
if (isr_val & IRQ_UART_ERROR_BIT) {
|
||||||
ret = -1;
|
ret = -1;
|
||||||
}
|
} else {
|
||||||
else
|
|
||||||
{
|
|
||||||
ret = uart_rbr_val & 0xff;
|
ret = uart_rbr_val & 0xff;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
/*
|
/*
|
||||||
* U-boot - start.S Startup file of u-boot for BF533
|
* U-boot - start.S Startup file of u-boot for BF533/BF561
|
||||||
*
|
*
|
||||||
* Copyright (c) 2005 blackfin.uclinux.org
|
* Copyright (c) 2005 blackfin.uclinux.org
|
||||||
*
|
*
|
||||||
|
@ -38,9 +38,23 @@
|
||||||
#define ASSEMBLY
|
#define ASSEMBLY
|
||||||
|
|
||||||
#include <linux/config.h>
|
#include <linux/config.h>
|
||||||
#include <asm/blackfin.h>
|
|
||||||
#include <config.h>
|
#include <config.h>
|
||||||
#include <asm/mem_init.h>
|
#include <asm/blackfin.h>
|
||||||
|
|
||||||
|
.global _stext;
|
||||||
|
.global __bss_start;
|
||||||
|
.global start;
|
||||||
|
.global _start;
|
||||||
|
.global _rambase;
|
||||||
|
.global _ramstart;
|
||||||
|
.global _ramend;
|
||||||
|
.global _bf533_data_dest;
|
||||||
|
.global _bf533_data_size;
|
||||||
|
.global edata;
|
||||||
|
.global _initialize;
|
||||||
|
.global _exit;
|
||||||
|
.global flashdataend;
|
||||||
|
.global init_sdram;
|
||||||
|
|
||||||
#if (CONFIG_CCLK_DIV == 1)
|
#if (CONFIG_CCLK_DIV == 1)
|
||||||
#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
|
#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
|
||||||
|
@ -58,26 +72,12 @@
|
||||||
#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
|
#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
.global _stext;
|
|
||||||
.global __bss_start;
|
|
||||||
.global start;
|
|
||||||
.global _start;
|
|
||||||
.global _rambase;
|
|
||||||
.global _ramstart;
|
|
||||||
.global _ramend;
|
|
||||||
.global _bf533_data_dest;
|
|
||||||
.global _bf533_data_size;
|
|
||||||
.global edata;
|
|
||||||
.global _initialize;
|
|
||||||
.global _exit;
|
|
||||||
.global flashdataend;
|
|
||||||
|
|
||||||
.text
|
.text
|
||||||
_start:
|
_start:
|
||||||
start:
|
start:
|
||||||
_stext:
|
_stext:
|
||||||
|
|
||||||
R0 = 0x30;
|
R0 = 0x32;
|
||||||
SYSCFG = R0;
|
SYSCFG = R0;
|
||||||
SSYNC;
|
SSYNC;
|
||||||
|
|
||||||
|
@ -120,8 +120,9 @@ _stext:
|
||||||
/* Set loop counters to zero, to make sure that
|
/* Set loop counters to zero, to make sure that
|
||||||
* hw loops are disabled.
|
* hw loops are disabled.
|
||||||
*/
|
*/
|
||||||
lc0 = 0;
|
r0 = 0;
|
||||||
lc1 = 0;
|
lc0 = r0;
|
||||||
|
lc1 = r0;
|
||||||
|
|
||||||
SSYNC;
|
SSYNC;
|
||||||
|
|
||||||
|
@ -150,105 +151,40 @@ no_soft_reset:
|
||||||
LSETUP(4,4) lc0 = p1;
|
LSETUP(4,4) lc0 = p1;
|
||||||
[ p0 ++ ] = r1;
|
[ p0 ++ ] = r1;
|
||||||
|
|
||||||
/*
|
p0.h = hi(SIC_IWR);
|
||||||
* Set PLL_CTL
|
p0.l = lo(SIC_IWR);
|
||||||
* - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
|
r0.l = 0x1;
|
||||||
* - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
|
|
||||||
* - [7] = output delay (add 200ps of delay to mem signals)
|
|
||||||
* - [6] = input delay (add 200ps of input delay to mem signals)
|
|
||||||
* - [5] = PDWN : 1=All Clocks off
|
|
||||||
* - [3] = STOPCK : 1=Core Clock off
|
|
||||||
* - [1] = PLL_OFF : 1=Disable Power to PLL
|
|
||||||
* - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
|
|
||||||
* all other bits set to zero
|
|
||||||
*/
|
|
||||||
|
|
||||||
r0 = CONFIG_VCO_MULT; /* Load the VCO multiplier */
|
|
||||||
r0 = r0 << 9; /* Shift it over */
|
|
||||||
r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2? */
|
|
||||||
r0 = r1 | r0;
|
|
||||||
r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
|
|
||||||
r1 = r1 << 8; /* Shift it over */
|
|
||||||
r0 = r1 | r0; /* add them all together */
|
|
||||||
|
|
||||||
p0.h = (PLL_CTL >> 16);
|
|
||||||
p0.l = (PLL_CTL & 0xFFFF); /* Load the address */
|
|
||||||
cli r2; /* Disable interrupts */
|
|
||||||
w[p0] = r0; /* Set the value */
|
|
||||||
idle; /* Wait for the PLL to stablize */
|
|
||||||
sti r2; /* Enable interrupts */
|
|
||||||
ssync;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Turn on the CYCLES COUNTER
|
|
||||||
*/
|
|
||||||
r2 = SYSCFG;
|
|
||||||
BITSET (r2,1);
|
|
||||||
SYSCFG = r2;
|
|
||||||
|
|
||||||
/* Configure SCLK & CCLK Dividers */
|
|
||||||
r0 = CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV;
|
|
||||||
p0.h = (PLL_DIV >> 16);
|
|
||||||
p0.l = (PLL_DIV & 0xFFFF);
|
|
||||||
w[p0] = r0;
|
|
||||||
ssync;
|
|
||||||
|
|
||||||
wait_for_pll_stab:
|
|
||||||
p0.h = (PLL_STAT >> 16);
|
|
||||||
p0.l = (PLL_STAT & 0xFFFF);
|
|
||||||
r0.l = w[p0];
|
|
||||||
cc = bittst(r0,5);
|
|
||||||
if !cc jump wait_for_pll_stab;
|
|
||||||
|
|
||||||
/* Configure SDRAM if SDRAM is already not enabled */
|
|
||||||
p0.l = (EBIU_SDSTAT & 0xFFFF);
|
|
||||||
p0.h = (EBIU_SDSTAT >> 16);
|
|
||||||
r0.l = w[p0];
|
|
||||||
cc = bittst(r0, 3);
|
|
||||||
if !cc jump skip_sdram_enable;
|
|
||||||
|
|
||||||
/* SDRAM initialization */
|
|
||||||
p0.l = (EBIU_SDGCTL & 0xFFFF);
|
|
||||||
p0.h = (EBIU_SDGCTL >> 16); /* SDRAM Memory Global Control Register */
|
|
||||||
r0.h = (mem_SDGCTL >> 16);
|
|
||||||
r0.l = (mem_SDGCTL & 0xFFFF);
|
|
||||||
[p0] = r0;
|
|
||||||
ssync;
|
|
||||||
|
|
||||||
p0.l = (EBIU_SDBCTL & 0xFFFF);
|
|
||||||
p0.h = (EBIU_SDBCTL >> 16); /* SDRAM Memory Bank Control Register */
|
|
||||||
r0 = mem_SDBCTL;
|
|
||||||
w[p0] = r0.l;
|
w[p0] = r0.l;
|
||||||
ssync;
|
SSYNC;
|
||||||
|
|
||||||
p0.l = (EBIU_SDRRC & 0xFFFF);
|
sp.l = (0xffb01000 & 0xFFFF);
|
||||||
p0.h = (EBIU_SDRRC >> 16); /* SDRAM Refresh Rate Control Register */
|
sp.h = (0xffb01000 >> 16);
|
||||||
r0 = mem_SDRRC;
|
|
||||||
w[p0] = r0.l;
|
|
||||||
ssync;
|
|
||||||
|
|
||||||
skip_sdram_enable:
|
call init_sdram;
|
||||||
nop;
|
|
||||||
|
|
||||||
#ifndef CFG_NO_FLASH
|
|
||||||
/* relocate into to RAM */
|
/* relocate into to RAM */
|
||||||
p1.l = (CFG_FLASH_BASE & 0xffff);
|
call get_pc;
|
||||||
p1.h = (CFG_FLASH_BASE >> 16);
|
offset:
|
||||||
|
r2.l = offset;
|
||||||
|
r2.h = offset;
|
||||||
|
r3.l = start;
|
||||||
|
r3.h = start;
|
||||||
|
r1 = r2 - r3;
|
||||||
|
|
||||||
|
r0 = r0 - r1;
|
||||||
|
p1 = r0;
|
||||||
|
|
||||||
p2.l = (CFG_MONITOR_BASE & 0xffff);
|
p2.l = (CFG_MONITOR_BASE & 0xffff);
|
||||||
p2.h = (CFG_MONITOR_BASE >> 16);
|
p2.h = (CFG_MONITOR_BASE >> 16);
|
||||||
r0.l = (CFG_MONITOR_LEN & 0xffff);
|
|
||||||
r0.h = (CFG_MONITOR_LEN >> 16);
|
p3 = 0x04;
|
||||||
|
p4.l = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) & 0xffff);
|
||||||
|
p4.h = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) >> 16);
|
||||||
loop1:
|
loop1:
|
||||||
r1 = [p1];
|
r1 = [p1 ++ p3];
|
||||||
[p2] = r1;
|
[p2 ++ p3] = r1;
|
||||||
p3=0x4;
|
cc=p2==p4;
|
||||||
p1=p1+p3;
|
|
||||||
p2=p2+p3;
|
|
||||||
r2=0x4;
|
|
||||||
r0=r0-r2;
|
|
||||||
cc=r0==0x0;
|
|
||||||
if !cc jump loop1;
|
if !cc jump loop1;
|
||||||
#endif
|
|
||||||
/*
|
/*
|
||||||
* configure STACK
|
* configure STACK
|
||||||
*/
|
*/
|
||||||
|
@ -273,7 +209,8 @@ loop1:
|
||||||
|
|
||||||
p0.l = (IMASK & 0xFFFF);
|
p0.l = (IMASK & 0xFFFF);
|
||||||
p0.h = (IMASK >> 16);
|
p0.h = (IMASK >> 16);
|
||||||
r0 = IVG15_POS;
|
r0.l = LO(IVG15_POS);
|
||||||
|
r0.h = HI(IVG15_POS);
|
||||||
[p0] = r0;
|
[p0] = r0;
|
||||||
raise 15;
|
raise 15;
|
||||||
p0.l = WAIT_HERE;
|
p0.l = WAIT_HERE;
|
||||||
|
@ -288,37 +225,10 @@ WAIT_HERE:
|
||||||
_real_start:
|
_real_start:
|
||||||
[ -- sp ] = reti;
|
[ -- sp ] = reti;
|
||||||
|
|
||||||
#ifdef CONFIG_EZKIT533
|
|
||||||
p0.l = (WDOG_CTL & 0xFFFF);
|
|
||||||
p0.h = (WDOG_CTL >> 16);
|
|
||||||
r0 = WATCHDOG_DISABLE(z);
|
|
||||||
w[p0] = r0;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Code for initializing Async mem banks */
|
|
||||||
p2.h = (EBIU_AMBCTL1 >> 16);
|
|
||||||
p2.l = (EBIU_AMBCTL1 & 0xFFFF);
|
|
||||||
r0.h = (AMBCTL1VAL >> 16);
|
|
||||||
r0.l = (AMBCTL1VAL & 0xFFFF);
|
|
||||||
[p2] = r0;
|
|
||||||
ssync;
|
|
||||||
|
|
||||||
p2.h = (EBIU_AMBCTL0 >> 16);
|
|
||||||
p2.l = (EBIU_AMBCTL0 & 0xFFFF);
|
|
||||||
r0.h = (AMBCTL0VAL >> 16);
|
|
||||||
r0.l = (AMBCTL0VAL & 0xFFFF);
|
|
||||||
[p2] = r0;
|
|
||||||
ssync;
|
|
||||||
|
|
||||||
p2.h = (EBIU_AMGCTL >> 16);
|
|
||||||
p2.l = (EBIU_AMGCTL & 0xffff);
|
|
||||||
r0 = AMGCTLVAL;
|
|
||||||
w[p2] = r0;
|
|
||||||
ssync;
|
|
||||||
|
|
||||||
/* DMA reset code to Hi of L1 SRAM */
|
/* DMA reset code to Hi of L1 SRAM */
|
||||||
copy:
|
copy:
|
||||||
P1.H = hi(SYSMMR_BASE); /* P1 Points to the beginning of SYSTEM MMR Space */
|
/* P1 Points to the beginning of SYSTEM MMR Space */
|
||||||
|
P1.H = hi(SYSMMR_BASE);
|
||||||
P1.L = lo(SYSMMR_BASE);
|
P1.L = lo(SYSMMR_BASE);
|
||||||
|
|
||||||
R0.H = reset_start; /* Source Address (high) */
|
R0.H = reset_start; /* Source Address (high) */
|
||||||
|
@ -329,7 +239,8 @@ copy:
|
||||||
R1.H = hi(L1_ISRAM); /* Destination Address (high) */
|
R1.H = hi(L1_ISRAM); /* Destination Address (high) */
|
||||||
R1.L = lo(L1_ISRAM); /* Destination Address (low) */
|
R1.L = lo(L1_ISRAM); /* Destination Address (low) */
|
||||||
R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
|
R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
|
||||||
R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */
|
/* Destination DMAConfig Value (8-bit words) */
|
||||||
|
R4.L = (DI_EN | WNR | DMAEN);
|
||||||
|
|
||||||
DMA:
|
DMA:
|
||||||
R6 = 0x1 (Z);
|
R6 = 0x1 (Z);
|
||||||
|
@ -342,57 +253,24 @@ DMA:
|
||||||
Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
|
Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
|
||||||
W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
|
W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
|
||||||
|
|
||||||
[P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */
|
/* Set Destination Base Address */
|
||||||
|
[P1+OFFSET_(MDMA_D0_START_ADDR)] = R1;
|
||||||
W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
|
W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
|
||||||
/* Set Destination DMAConfig = DMA Enable,
|
/* Set Destination DMAConfig = DMA Enable,
|
||||||
Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
|
Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
|
||||||
W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
|
W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
|
||||||
|
|
||||||
IDLE; /* Wait for DMA to Complete */
|
WAIT_DMA_DONE:
|
||||||
|
p0.h = hi(MDMA_D0_IRQ_STATUS);
|
||||||
|
p0.l = lo(MDMA_D0_IRQ_STATUS);
|
||||||
|
R0 = W[P0](Z);
|
||||||
|
CC = BITTST(R0, 0);
|
||||||
|
if ! CC jump WAIT_DMA_DONE
|
||||||
|
|
||||||
R0 = 0x1;
|
R0 = 0x1;
|
||||||
W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
|
|
||||||
|
|
||||||
/* DMA reset code to DATA BANK A which uses this port
|
/* Write 1 to clear DMA interrupt */
|
||||||
* to avoid following problem
|
W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0;
|
||||||
* " Data from a Data Cache fill can be corrupoted after or during
|
|
||||||
* instruction DMA if certain core stalls exist"
|
|
||||||
*/
|
|
||||||
|
|
||||||
copy_as_data:
|
|
||||||
R0.H = reset_start; /* Source Address (high) */
|
|
||||||
R0.L = reset_start; /* Source Address (low) */
|
|
||||||
R1.H = reset_end;
|
|
||||||
R1.L = reset_end;
|
|
||||||
R2 = R1 - R0; /* Count */
|
|
||||||
R1.H = hi(DATA_BANKA_SRAM); /* Destination Address (high) */
|
|
||||||
R1.L = lo(DATA_BANKA_SRAM); /* Destination Address (low) */
|
|
||||||
R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
|
|
||||||
R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */
|
|
||||||
|
|
||||||
DMA_DATA:
|
|
||||||
R6 = 0x1 (Z);
|
|
||||||
W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
|
|
||||||
W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
|
|
||||||
|
|
||||||
[P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
|
|
||||||
W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */
|
|
||||||
/* Set Source DMAConfig = DMA Enable,
|
|
||||||
Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
|
|
||||||
W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
|
|
||||||
|
|
||||||
[P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */
|
|
||||||
W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
|
|
||||||
/* Set Destination DMAConfig = DMA Enable,
|
|
||||||
Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
|
|
||||||
W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
|
|
||||||
|
|
||||||
IDLE; /* Wait for DMA to Complete */
|
|
||||||
|
|
||||||
R0 = 0x1;
|
|
||||||
W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
|
|
||||||
|
|
||||||
copy_end: nop;
|
|
||||||
|
|
||||||
/* Initialize BSS Section with 0 s */
|
/* Initialize BSS Section with 0 s */
|
||||||
p1.l = __bss_start;
|
p1.l = __bss_start;
|
||||||
|
@ -433,3 +311,6 @@ reset_end: nop;
|
||||||
|
|
||||||
_exit:
|
_exit:
|
||||||
jump.s _exit;
|
jump.s _exit;
|
||||||
|
get_pc:
|
||||||
|
r0 = rets;
|
||||||
|
rts;
|
||||||
|
|
|
@ -24,8 +24,8 @@
|
||||||
|
|
||||||
#define ASSEMBLY
|
#define ASSEMBLY
|
||||||
#include <linux/config.h>
|
#include <linux/config.h>
|
||||||
#include <asm/blackfin.h>
|
|
||||||
#include <config.h>
|
#include <config.h>
|
||||||
|
#include <asm/blackfin.h>
|
||||||
|
|
||||||
.global start1;
|
.global start1;
|
||||||
.global _start1;
|
.global _start1;
|
||||||
|
@ -34,5 +34,5 @@
|
||||||
_start1:
|
_start1:
|
||||||
start1:
|
start1:
|
||||||
sp += -12;
|
sp += -12;
|
||||||
call board_init_f;
|
call _board_init_f;
|
||||||
sp += 12;
|
sp += 12;
|
||||||
|
|
|
@ -42,6 +42,18 @@
|
||||||
#include <asm/page.h>
|
#include <asm/page.h>
|
||||||
#include <asm/machdep.h>
|
#include <asm/machdep.h>
|
||||||
#include "cpu.h"
|
#include "cpu.h"
|
||||||
|
#include <asm/arch/anomaly.h>
|
||||||
|
#include <asm/cplb.h>
|
||||||
|
|
||||||
|
#ifdef DEBUG
|
||||||
|
#define pr_debug(fmt,arg...) printf(fmt,##arg)
|
||||||
|
#else
|
||||||
|
static inline int
|
||||||
|
__attribute__ ((format(printf, 1, 2))) pr_debug(const char *fmt, ...)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
void init_IRQ(void)
|
void init_IRQ(void)
|
||||||
{
|
{
|
||||||
|
@ -51,23 +63,188 @@ void init_IRQ(void)
|
||||||
|
|
||||||
void process_int(unsigned long vec, struct pt_regs *fp)
|
void process_int(unsigned long vec, struct pt_regs *fp)
|
||||||
{
|
{
|
||||||
|
printf("interrupt\n");
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
extern unsigned int icplb_table[page_descriptor_table_size][2];
|
||||||
|
extern unsigned int dcplb_table[page_descriptor_table_size][2];
|
||||||
|
|
||||||
|
unsigned long last_cplb_fault_retx;
|
||||||
|
|
||||||
|
static unsigned int cplb_sizes[4] =
|
||||||
|
{ 1024, 4 * 1024, 1024 * 1024, 4 * 1024 * 1024 };
|
||||||
|
|
||||||
|
void trap_c(struct pt_regs *regs)
|
||||||
|
{
|
||||||
|
unsigned int addr;
|
||||||
|
unsigned long trapnr = (regs->seqstat) & SEQSTAT_EXCAUSE;
|
||||||
|
unsigned int i, j, size, *I0, *I1;
|
||||||
|
unsigned short data = 0;
|
||||||
|
|
||||||
|
switch (trapnr) {
|
||||||
|
/* 0x26 - Data CPLB Miss */
|
||||||
|
case VEC_CPLB_M:
|
||||||
|
|
||||||
|
#ifdef ANOMALY_05000261
|
||||||
|
/*
|
||||||
|
* Work around an anomaly: if we see a new DCPLB fault,
|
||||||
|
* return without doing anything. Then,
|
||||||
|
* if we get the same fault again, handle it.
|
||||||
|
*/
|
||||||
|
addr = last_cplb_fault_retx;
|
||||||
|
last_cplb_fault_retx = regs->retx;
|
||||||
|
printf("this time, curr = 0x%08x last = 0x%08x\n",
|
||||||
|
addr, last_cplb_fault_retx);
|
||||||
|
if (addr != last_cplb_fault_retx)
|
||||||
|
goto trap_c_return;
|
||||||
|
#endif
|
||||||
|
data = 1;
|
||||||
|
|
||||||
|
case VEC_CPLB_I_M:
|
||||||
|
|
||||||
|
if (data) {
|
||||||
|
addr = *pDCPLB_FAULT_ADDR;
|
||||||
|
} else {
|
||||||
|
addr = *pICPLB_FAULT_ADDR;
|
||||||
|
}
|
||||||
|
for (i = 0; i < page_descriptor_table_size; i++) {
|
||||||
|
if (data) {
|
||||||
|
size = cplb_sizes[dcplb_table[i][1] >> 16];
|
||||||
|
j = dcplb_table[i][0];
|
||||||
|
} else {
|
||||||
|
size = cplb_sizes[icplb_table[i][1] >> 16];
|
||||||
|
j = icplb_table[i][0];
|
||||||
|
}
|
||||||
|
if ((j <= addr) && ((j + size) > addr)) {
|
||||||
|
pr_debug("found %i 0x%08x\n", i, j);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
if (i == page_descriptor_table_size) {
|
||||||
|
printf("something is really wrong\n");
|
||||||
|
do_reset(NULL, 0, 0, NULL);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Turn the cache off */
|
||||||
|
if (data) {
|
||||||
|
__builtin_bfin_ssync();
|
||||||
|
asm(" .align 8; ");
|
||||||
|
*(unsigned int *)DMEM_CONTROL &=
|
||||||
|
~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
|
||||||
|
__builtin_bfin_ssync();
|
||||||
|
} else {
|
||||||
|
__builtin_bfin_ssync();
|
||||||
|
asm(" .align 8; ");
|
||||||
|
*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
|
||||||
|
__builtin_bfin_ssync();
|
||||||
|
}
|
||||||
|
|
||||||
|
if (data) {
|
||||||
|
I0 = (unsigned int *)DCPLB_ADDR0;
|
||||||
|
I1 = (unsigned int *)DCPLB_DATA0;
|
||||||
|
} else {
|
||||||
|
I0 = (unsigned int *)ICPLB_ADDR0;
|
||||||
|
I1 = (unsigned int *)ICPLB_DATA0;
|
||||||
|
}
|
||||||
|
|
||||||
|
j = 0;
|
||||||
|
while (*I1 & CPLB_LOCK) {
|
||||||
|
pr_debug("skipping %i %08p - %08x\n", j, I1, *I1);
|
||||||
|
*I0++;
|
||||||
|
*I1++;
|
||||||
|
j++;
|
||||||
|
}
|
||||||
|
|
||||||
|
pr_debug("remove %i 0x%08x 0x%08x\n", j, *I0, *I1);
|
||||||
|
|
||||||
|
for (; j < 15; j++) {
|
||||||
|
pr_debug("replace %i 0x%08x 0x%08x\n", j, I0, I0 + 1);
|
||||||
|
*I0++ = *(I0 + 1);
|
||||||
|
*I1++ = *(I1 + 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (data) {
|
||||||
|
*I0 = dcplb_table[i][0];
|
||||||
|
*I1 = dcplb_table[i][1];
|
||||||
|
I0 = (unsigned int *)DCPLB_ADDR0;
|
||||||
|
I1 = (unsigned int *)DCPLB_DATA0;
|
||||||
|
} else {
|
||||||
|
*I0 = icplb_table[i][0];
|
||||||
|
*I1 = icplb_table[i][1];
|
||||||
|
I0 = (unsigned int *)ICPLB_ADDR0;
|
||||||
|
I1 = (unsigned int *)ICPLB_DATA0;
|
||||||
|
}
|
||||||
|
|
||||||
|
for (j = 0; j < 16; j++) {
|
||||||
|
pr_debug("%i 0x%08x 0x%08x\n", j, *I0++, *I1++);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Turn the cache back on */
|
||||||
|
if (data) {
|
||||||
|
j = *(unsigned int *)DMEM_CONTROL;
|
||||||
|
__builtin_bfin_ssync();
|
||||||
|
asm(" .align 8; ");
|
||||||
|
*(unsigned int *)DMEM_CONTROL =
|
||||||
|
ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | j;
|
||||||
|
__builtin_bfin_ssync();
|
||||||
|
} else {
|
||||||
|
__builtin_bfin_ssync();
|
||||||
|
asm(" .align 8; ");
|
||||||
|
*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
|
||||||
|
__builtin_bfin_ssync();
|
||||||
|
}
|
||||||
|
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
/* All traps come here */
|
||||||
|
printf("code=[0x%x], ", (unsigned int)(regs->seqstat & 0x3f));
|
||||||
|
printf("stack frame=0x%x, ", (unsigned int)regs);
|
||||||
|
printf("bad PC=0x%04x\n", (unsigned int)regs->pc);
|
||||||
|
dump(regs);
|
||||||
|
printf("\n\n");
|
||||||
|
|
||||||
|
printf("Unhandled IRQ or exceptions!\n");
|
||||||
|
printf("Please reset the board \n");
|
||||||
|
do_reset(NULL, 0, 0, NULL);
|
||||||
|
}
|
||||||
|
|
||||||
|
trap_c_return:
|
||||||
|
return;
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
void dump(struct pt_regs *fp)
|
void dump(struct pt_regs *fp)
|
||||||
{
|
{
|
||||||
printf("PC: %08lx\n", fp->pc);
|
pr_debug("RETE: %08lx RETN: %08lx RETX: %08lx RETS: %08lx\n",
|
||||||
printf("SEQSTAT: %08lx SP: %08lx\n", (long) fp->seqstat,
|
fp->rete, fp->retn, fp->retx, fp->rets);
|
||||||
(long) fp);
|
pr_debug("IPEND: %04lx SYSCFG: %04lx\n", fp->ipend, fp->syscfg);
|
||||||
printf("R0: %08lx R1: %08lx R2: %08lx R3: %08lx\n",
|
pr_debug("SEQSTAT: %08lx SP: %08lx\n", (long)fp->seqstat, (long)fp);
|
||||||
|
pr_debug("R0: %08lx R1: %08lx R2: %08lx R3: %08lx\n",
|
||||||
fp->r0, fp->r1, fp->r2, fp->r3);
|
fp->r0, fp->r1, fp->r2, fp->r3);
|
||||||
printf("R4: %08lx R5: %08lx R6: %08lx R7: %08lx\n",
|
pr_debug("R4: %08lx R5: %08lx R6: %08lx R7: %08lx\n",
|
||||||
fp->r4, fp->r5, fp->r6, fp->r7);
|
fp->r4, fp->r5, fp->r6, fp->r7);
|
||||||
printf("P0: %08lx P1: %08lx P2: %08lx P3: %08lx\n",
|
pr_debug("P0: %08lx P1: %08lx P2: %08lx P3: %08lx\n",
|
||||||
fp->p0, fp->p1, fp->p2, fp->p3);
|
fp->p0, fp->p1, fp->p2, fp->p3);
|
||||||
printf("P4: %08lx P5: %08lx FP: %08lx\n", fp->p4, fp->p5,
|
pr_debug("P4: %08lx P5: %08lx FP: %08lx\n",
|
||||||
fp->fp);
|
fp->p4, fp->p5, fp->fp);
|
||||||
printf("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
|
pr_debug("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
|
||||||
fp->a0w, fp->a0x, fp->a1w, fp->a1x);
|
fp->a0w, fp->a0x, fp->a1w, fp->a1x);
|
||||||
printf("\n");
|
|
||||||
|
pr_debug("LB0: %08lx LT0: %08lx LC0: %08lx\n",
|
||||||
|
fp->lb0, fp->lt0, fp->lc0);
|
||||||
|
pr_debug("LB1: %08lx LT1: %08lx LC1: %08lx\n",
|
||||||
|
fp->lb1, fp->lt1, fp->lc1);
|
||||||
|
pr_debug("B0: %08lx L0: %08lx M0: %08lx I0: %08lx\n",
|
||||||
|
fp->b0, fp->l0, fp->m0, fp->i0);
|
||||||
|
pr_debug("B1: %08lx L1: %08lx M1: %08lx I1: %08lx\n",
|
||||||
|
fp->b1, fp->l1, fp->m1, fp->i1);
|
||||||
|
pr_debug("B2: %08lx L2: %08lx M2: %08lx I2: %08lx\n",
|
||||||
|
fp->b2, fp->l2, fp->m2, fp->i2);
|
||||||
|
pr_debug("B3: %08lx L3: %08lx M3: %08lx I3: %08lx\n",
|
||||||
|
fp->b3, fp->l3, fp->m3, fp->i3);
|
||||||
|
|
||||||
|
pr_debug("DCPLB_FAULT_ADDR=%p\n", *pDCPLB_FAULT_ADDR);
|
||||||
|
pr_debug("ICPLB_FAULT_ADDR=%p\n", *pICPLB_FAULT_ADDR);
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
|
@ -0,0 +1,194 @@
|
||||||
|
/*
|
||||||
|
* (C) Copyright 2000
|
||||||
|
* Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
|
||||||
|
* (C) Copyright 2002
|
||||||
|
* Wolfgang Denk, wd@denx.de
|
||||||
|
* (C) Copyright 2006
|
||||||
|
* Aubrey Li, aubrey.li@analog.com
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <stdarg.h>
|
||||||
|
#include <common.h>
|
||||||
|
#include <config.h>
|
||||||
|
#include <asm/blackfin.h>
|
||||||
|
#include <i2c.h>
|
||||||
|
#include <linux/types.h>
|
||||||
|
#include <devices.h>
|
||||||
|
|
||||||
|
#ifdef CONFIG_VIDEO
|
||||||
|
#define NTSC_FRAME_ADDR 0x06000000
|
||||||
|
#include "video.h"
|
||||||
|
|
||||||
|
/* NTSC OUTPUT SIZE 720 * 240 */
|
||||||
|
#define VERTICAL 2
|
||||||
|
#define HORIZONTAL 4
|
||||||
|
|
||||||
|
int is_vblank_line(const int line)
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
* This array contains a single bit for each line in
|
||||||
|
* an NTSC frame.
|
||||||
|
*/
|
||||||
|
if ((line <= 18) || (line >= 264 && line <= 281) || (line == 528))
|
||||||
|
return true;
|
||||||
|
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
int NTSC_framebuffer_init(char *base_address)
|
||||||
|
{
|
||||||
|
const int NTSC_frames = 1;
|
||||||
|
const int NTSC_lines = 525;
|
||||||
|
char *dest = base_address;
|
||||||
|
int frame_num, line_num;
|
||||||
|
|
||||||
|
for (frame_num = 0; frame_num < NTSC_frames; ++frame_num) {
|
||||||
|
for (line_num = 1; line_num <= NTSC_lines; ++line_num) {
|
||||||
|
unsigned int code;
|
||||||
|
int offset = 0;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
if (is_vblank_line(line_num))
|
||||||
|
offset++;
|
||||||
|
|
||||||
|
if (line_num > 266 || line_num < 3)
|
||||||
|
offset += 2;
|
||||||
|
|
||||||
|
/* Output EAV code */
|
||||||
|
code = SystemCodeMap[offset].EAV;
|
||||||
|
write_dest_byte((char)(code >> 24) & 0xff);
|
||||||
|
write_dest_byte((char)(code >> 16) & 0xff);
|
||||||
|
write_dest_byte((char)(code >> 8) & 0xff);
|
||||||
|
write_dest_byte((char)(code) & 0xff);
|
||||||
|
|
||||||
|
/* Output horizontal blanking */
|
||||||
|
for (i = 0; i < 67 * 2; ++i) {
|
||||||
|
write_dest_byte(0x80);
|
||||||
|
write_dest_byte(0x10);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Output SAV */
|
||||||
|
code = SystemCodeMap[offset].SAV;
|
||||||
|
write_dest_byte((char)(code >> 24) & 0xff);
|
||||||
|
write_dest_byte((char)(code >> 16) & 0xff);
|
||||||
|
write_dest_byte((char)(code >> 8) & 0xff);
|
||||||
|
write_dest_byte((char)(code) & 0xff);
|
||||||
|
|
||||||
|
/* Output empty horizontal data */
|
||||||
|
for (i = 0; i < 360 * 2; ++i) {
|
||||||
|
write_dest_byte(0x80);
|
||||||
|
write_dest_byte(0x10);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return dest - base_address;
|
||||||
|
}
|
||||||
|
|
||||||
|
void fill_frame(char *Frame, int Value)
|
||||||
|
{
|
||||||
|
int *OddPtr32;
|
||||||
|
int OddLine;
|
||||||
|
int *EvenPtr32;
|
||||||
|
int EvenLine;
|
||||||
|
int i;
|
||||||
|
int *data;
|
||||||
|
int m, n;
|
||||||
|
|
||||||
|
/* fill odd and even frames */
|
||||||
|
for (OddLine = 22, EvenLine = 285; OddLine < 263; OddLine++, EvenLine++) {
|
||||||
|
OddPtr32 = (int *)((Frame + (OddLine * 1716)) + 276);
|
||||||
|
EvenPtr32 = (int *)((Frame + (EvenLine * 1716)) + 276);
|
||||||
|
for (i = 0; i < 360; i++, OddPtr32++, EvenPtr32++) {
|
||||||
|
*OddPtr32 = Value;
|
||||||
|
*EvenPtr32 = Value;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
for (m = 0; m < VERTICAL; m++) {
|
||||||
|
data = (int *)u_boot_logo.data;
|
||||||
|
for (OddLine = (22 + m), EvenLine = (285 + m);
|
||||||
|
OddLine < (u_boot_logo.height * VERTICAL) + (22 + m);
|
||||||
|
OddLine += VERTICAL, EvenLine += VERTICAL) {
|
||||||
|
OddPtr32 = (int *)((Frame + ((OddLine) * 1716)) + 276);
|
||||||
|
EvenPtr32 =
|
||||||
|
(int *)((Frame + ((EvenLine) * 1716)) + 276);
|
||||||
|
for (i = 0; i < u_boot_logo.width / 2; i++) {
|
||||||
|
/* enlarge one pixel to m x n */
|
||||||
|
for (n = 0; n < HORIZONTAL; n++) {
|
||||||
|
*OddPtr32++ = *data;
|
||||||
|
*EvenPtr32++ = *data;
|
||||||
|
}
|
||||||
|
data++;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void video_putc(const char c)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
void video_puts(const char *s)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
static int video_init(void)
|
||||||
|
{
|
||||||
|
char *NTSCFrame;
|
||||||
|
NTSCFrame = (char *)NTSC_FRAME_ADDR;
|
||||||
|
NTSC_framebuffer_init(NTSCFrame);
|
||||||
|
fill_frame(NTSCFrame, BLUE);
|
||||||
|
|
||||||
|
*pPPI_CONTROL = 0x0082;
|
||||||
|
*pPPI_FRAME = 0x020D;
|
||||||
|
|
||||||
|
*pDMA0_START_ADDR = NTSCFrame;
|
||||||
|
*pDMA0_X_COUNT = 0x035A;
|
||||||
|
*pDMA0_X_MODIFY = 0x0002;
|
||||||
|
*pDMA0_Y_COUNT = 0x020D;
|
||||||
|
*pDMA0_Y_MODIFY = 0x0002;
|
||||||
|
*pDMA0_CONFIG = 0x1015;
|
||||||
|
*pPPI_CONTROL = 0x0083;
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int drv_video_init(void)
|
||||||
|
{
|
||||||
|
int error, devices = 1;
|
||||||
|
|
||||||
|
device_t videodev;
|
||||||
|
|
||||||
|
video_init(); /* Video initialization */
|
||||||
|
|
||||||
|
memset(&videodev, 0, sizeof(videodev));
|
||||||
|
|
||||||
|
strcpy(videodev.name, "video");
|
||||||
|
videodev.ext = DEV_EXT_VIDEO; /* Video extensions */
|
||||||
|
videodev.flags = DEV_FLAGS_OUTPUT; /* Output only */
|
||||||
|
videodev.putc = video_putc; /* 'putc' function */
|
||||||
|
videodev.puts = video_puts; /* 'puts' function */
|
||||||
|
|
||||||
|
error = device_register(&videodev);
|
||||||
|
|
||||||
|
return (error == 0) ? devices : error;
|
||||||
|
}
|
||||||
|
#endif
|
|
@ -0,0 +1,25 @@
|
||||||
|
#include <video_logo.h>
|
||||||
|
#define write_dest_byte(val) {*dest++=val;}
|
||||||
|
#define BLACK (0x01800180) /* black pixel pattern */
|
||||||
|
#define BLUE (0x296E29F0) /* blue pixel pattern */
|
||||||
|
#define RED (0x51F0515A) /* red pixel pattern */
|
||||||
|
#define MAGENTA (0x6ADE6ACA) /* magenta pixel pattern */
|
||||||
|
#define GREEN (0x91229136) /* green pixel pattern */
|
||||||
|
#define CYAN (0xAA10AAA6) /* cyan pixel pattern */
|
||||||
|
#define YELLOW (0xD292D210) /* yellow pixel pattern */
|
||||||
|
#define WHITE (0xFE80FE80) /* white pixel pattern */
|
||||||
|
|
||||||
|
#define true 1
|
||||||
|
#define false 0
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
unsigned int SAV;
|
||||||
|
unsigned int EAV;
|
||||||
|
} SystemCodeType;
|
||||||
|
|
||||||
|
const SystemCodeType SystemCodeMap[4] = {
|
||||||
|
{0xFF000080, 0xFF00009D},
|
||||||
|
{0xFF0000AB, 0xFF0000B6},
|
||||||
|
{0xFF0000C7, 0xFF0000DA},
|
||||||
|
{0xFF0000EC, 0xFF0000F1}
|
||||||
|
};
|
|
@ -0,0 +1,172 @@
|
||||||
|
/*
|
||||||
|
* File: include/asm-blackfin/arch-bf533/anomaly.h
|
||||||
|
* Based on:
|
||||||
|
* Author:
|
||||||
|
*
|
||||||
|
* Created:
|
||||||
|
* Description:
|
||||||
|
*
|
||||||
|
* Rev:
|
||||||
|
*
|
||||||
|
* Modified:
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2, or (at your option)
|
||||||
|
* any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; see the file COPYING.
|
||||||
|
* If not, write to the Free Software Foundation,
|
||||||
|
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* This file shoule be up to date with:
|
||||||
|
* - Revision U, May 17, 2006; ADSP-BF533 Blackfin Processor Anomaly List
|
||||||
|
* - Revision Y, May 17, 2006; ADSP-BF532 Blackfin Processor Anomaly List
|
||||||
|
* - Revision T, May 17, 2006; ADSP-BF531 Blackfin Processor Anomaly List
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _MACH_ANOMALY_H_
|
||||||
|
#define _MACH_ANOMALY_H_
|
||||||
|
|
||||||
|
/* We do not support 0.1 or 0.2 silicon - sorry */
|
||||||
|
#if (defined(CONFIG_BF_REV_0_1) || defined(CONFIG_BF_REV_0_2))
|
||||||
|
#error Kernel will not work on BF533 Version 0.1 or 0.2
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Issues that are common to 0.5, 0.4, and 0.3 silicon */
|
||||||
|
#if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3))
|
||||||
|
#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
|
||||||
|
slot1 and store of a P register in slot 2 is not
|
||||||
|
supported */
|
||||||
|
#define ANOMALY_05000105 /* Watchpoint Status Register (WPSTAT) bits are set on
|
||||||
|
every corresponding match */
|
||||||
|
#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
|
||||||
|
Channel DMA stops */
|
||||||
|
#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
|
||||||
|
registers. */
|
||||||
|
#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out
|
||||||
|
upper bits*/
|
||||||
|
#define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */
|
||||||
|
#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
|
||||||
|
syncs */
|
||||||
|
#define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not
|
||||||
|
functional */
|
||||||
|
#define ANOMALY_05000219 /* NMI event at boot time results in unpredictable
|
||||||
|
state */
|
||||||
|
#define ANOMALY_05000229 /* SPI Slave Boot Mode modifies registers */
|
||||||
|
#define ANOMALY_05000272 /* Certain data cache write through modes fail for
|
||||||
|
VDDint <=0.9V */
|
||||||
|
#define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */
|
||||||
|
#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
|
||||||
|
an edge is detected may clear interrupt */
|
||||||
|
#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
|
||||||
|
DMA system instability */
|
||||||
|
#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
|
||||||
|
not restored */
|
||||||
|
#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
|
||||||
|
control */
|
||||||
|
#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
|
||||||
|
killed in a particular stage*/
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* These issues only occur on 0.3 or 0.4 BF533 */
|
||||||
|
#if (defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3))
|
||||||
|
#define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not
|
||||||
|
updated at the same time. */
|
||||||
|
#define ANOMALY_05000158 /* Boot fails when data cache enabled: Data from a Data
|
||||||
|
Cache Fill can be corrupted after or during
|
||||||
|
Instruction DMA if certain core stalls exist */
|
||||||
|
#define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General
|
||||||
|
Purpose TX or RX modes */
|
||||||
|
#define ANOMALY_05000198 /* Failing SYSTEM MMR accesses when stalled by
|
||||||
|
preceding memory read */
|
||||||
|
#define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during
|
||||||
|
inactive channels in certain conditions */
|
||||||
|
#define ANOMALY_05000202 /* Possible infinite stall with specific dual dag
|
||||||
|
situation */
|
||||||
|
#define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */
|
||||||
|
#define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */
|
||||||
|
#define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect
|
||||||
|
data*/
|
||||||
|
#define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate
|
||||||
|
Differences in certain Conditions */
|
||||||
|
#define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */
|
||||||
|
#define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to
|
||||||
|
hardware reset */
|
||||||
|
#define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or
|
||||||
|
IDLE around a Change of Control causes
|
||||||
|
unpredictable results */
|
||||||
|
#define ANOMALY_05000245 /* Spurious Hardware Error from an access in the
|
||||||
|
shadow of a conditional branch */
|
||||||
|
#define ANOMALY_05000246 /* Data CPLB's should prevent spurious hardware
|
||||||
|
errors */
|
||||||
|
#define ANOMALY_05000253 /* Maximum external clock speed for Timers */
|
||||||
|
#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event
|
||||||
|
interrupt not functional */
|
||||||
|
#define ANOMALY_05000257 /* An interrupt or exception during short Hardware
|
||||||
|
loops may cause the instruction fetch unit to
|
||||||
|
malfunction */
|
||||||
|
#define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of
|
||||||
|
the ICPLB Data registers differ */
|
||||||
|
#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
|
||||||
|
#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
|
||||||
|
#define ANOMALY_05000262 /* Stores to data cache may be lost */
|
||||||
|
#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */
|
||||||
|
#define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE
|
||||||
|
instruction will cause an infinite stall in the
|
||||||
|
second to last instruction in a hardware loop */
|
||||||
|
#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
|
||||||
|
SPORT external receive and transmit clocks. */
|
||||||
|
#define ANOMALY_05000269 /* High I/O activity causes the output voltage of the
|
||||||
|
internal voltage regulator (VDDint) to increase. */
|
||||||
|
#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the
|
||||||
|
internal voltage regulator (VDDint) to decrease */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* These issues are only on 0.4 silicon */
|
||||||
|
#if (defined(CONFIG_BF_REV_0_4))
|
||||||
|
#define ANOMALY_05000234 /* Incorrect Revision Number in DSPID Register */
|
||||||
|
#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
|
||||||
|
(TDM) */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* These issues are only on 0.3 silicon */
|
||||||
|
#if defined(CONFIG_BF_REV_0_3)
|
||||||
|
#define ANOMALY_05000183 /* Timer Pin limitations for PPI TX Modes with
|
||||||
|
External Frame Syncs */
|
||||||
|
#define ANOMALY_05000189 /* False Protection Exceptions caused by Speculative
|
||||||
|
Instruction or Data Fetches, or by Fetches at the
|
||||||
|
boundary of reserved memory space */
|
||||||
|
#define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs
|
||||||
|
when polarity setting is changed */
|
||||||
|
#define ANOMALY_05000194 /* Sport Restarting in specific modes may cause data
|
||||||
|
corruption */
|
||||||
|
#define ANOMALY_05000199 /* DMA current address shows wrong value during carry
|
||||||
|
fix */
|
||||||
|
#define ANOMALY_05000201 /* Receive frame sync not ignored during active
|
||||||
|
frames in sport MCM */
|
||||||
|
#define ANOMALY_05000203 /* Specific sequence that can cause DMA error or DMA
|
||||||
|
stopping */
|
||||||
|
#if defined(CONFIG_BF533)
|
||||||
|
#define ANOMALY_05000204 /* Incorrect data read with write-through cache and
|
||||||
|
allocate cache lines on reads only mode */
|
||||||
|
#endif /* CONFIG_BF533 */
|
||||||
|
#define ANOMALY_05000207 /* Recovery from "brown-out" condition */
|
||||||
|
#define ANOMALY_05000209 /* Speed-Path in computational unit affects certain
|
||||||
|
instructions */
|
||||||
|
#define ANOMALY_05000233 /* PPI_FS3 is not driven in 2 or 3 internal Frame
|
||||||
|
Sync Transmit Mode */
|
||||||
|
#define ANOMALY_05000271 /* Spontaneous reset of Internal Voltage Regulator */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* _MACH_ANOMALY_H_ */
|
|
@ -22,7 +22,6 @@
|
||||||
* MA 02111-1307 USA
|
* MA 02111-1307 USA
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
|
||||||
#ifndef _BF533_SERIAL_H_
|
#ifndef _BF533_SERIAL_H_
|
||||||
#define _BF533_SERIAL_H_
|
#define _BF533_SERIAL_H_
|
||||||
|
|
|
@ -19,6 +19,6 @@
|
||||||
#ifndef _CDEFBF531_H
|
#ifndef _CDEFBF531_H
|
||||||
#define _CDEFBF531_H
|
#define _CDEFBF531_H
|
||||||
|
|
||||||
#include <cdefBF532.h>
|
#include <asm/arch-bf533/cdefBF532.h>
|
||||||
|
|
||||||
#endif /* _CDEFBF531_H */
|
#endif /* _CDEFBF531_H */
|
|
@ -26,10 +26,10 @@
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* include all Core registers and bit definitions */
|
/* include all Core registers and bit definitions */
|
||||||
#include <asm/cpu/defBF532.h>
|
#include <asm/arch-bf533/defBF532.h>
|
||||||
|
|
||||||
/* include core specific register pointer definitions */
|
/* include core specific register pointer definitions */
|
||||||
#include <asm/cpu/cdef_LPBlackfin.h>
|
#include <asm/arch-common/cdef_LPBlackfin.h>
|
||||||
|
|
||||||
/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
|
/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
|
||||||
#define pPLL_CTL ((volatile unsigned short *)PLL_CTL)
|
#define pPLL_CTL ((volatile unsigned short *)PLL_CTL)
|
|
@ -19,6 +19,6 @@
|
||||||
#ifndef _CDEFBF533_H
|
#ifndef _CDEFBF533_H
|
||||||
#define _CDEFBF533_H
|
#define _CDEFBF533_H
|
||||||
|
|
||||||
#include <asm/cpu/cdefBF532.h>
|
#include <asm/arch-bf533/cdefBF532.h>
|
||||||
|
|
||||||
#endif /* _CDEFBF533_H */
|
#endif /* _CDEFBF533_H */
|
|
@ -0,0 +1,482 @@
|
||||||
|
/*This file is subject to the terms and conditions of the GNU General Public
|
||||||
|
* License.
|
||||||
|
*
|
||||||
|
* Blackfin BF533/2.6 support : LG Soft India
|
||||||
|
* Updated : Ashutosh Singh / Jahid Khan : Rrap Software Pvt Ltd
|
||||||
|
* Updated : 1. SDRAM_KERNEL, SDRAM_DKENEL are added as initial cplb's
|
||||||
|
* shouldn't be victimized. cplbmgr.S search logic is corrected
|
||||||
|
* to findout the appropriate victim.
|
||||||
|
* 2. SDRAM_IGENERIC in dpdt_table is replaced with SDRAM_DGENERIC
|
||||||
|
* : LG Soft India
|
||||||
|
*/
|
||||||
|
#include <config.h>
|
||||||
|
|
||||||
|
#ifndef __ARCH_BFINNOMMU_CPLBTAB_H
|
||||||
|
#define __ARCH_BFINNOMMU_CPLBTAB_H
|
||||||
|
|
||||||
|
/*************************************************************************
|
||||||
|
* ICPLB TABLE
|
||||||
|
*************************************************************************/
|
||||||
|
|
||||||
|
.data
|
||||||
|
/* This table is configurable */
|
||||||
|
.align 4;
|
||||||
|
|
||||||
|
/* Data Attibutes*/
|
||||||
|
|
||||||
|
#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
|
||||||
|
#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
|
||||||
|
#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
|
||||||
|
#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
|
||||||
|
|
||||||
|
/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
|
||||||
|
|
||||||
|
#define ANOMALY_05000158 0x200
|
||||||
|
#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
|
||||||
|
#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
|
||||||
|
#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
|
||||||
|
#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
|
||||||
|
#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
|
||||||
|
#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
|
||||||
|
|
||||||
|
#else /*Write Through */
|
||||||
|
#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
|
||||||
|
#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
|
||||||
|
#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
|
||||||
|
#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
|
||||||
|
#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
.align 4;
|
||||||
|
.global _ipdt_table _ipdt_table:.byte4 0x00000000;
|
||||||
|
.byte4(SDRAM_IKERNEL); /*SDRAM_Page0 */
|
||||||
|
.byte4 0x00400000;
|
||||||
|
.byte4(SDRAM_IKERNEL); /*SDRAM_Page1 */
|
||||||
|
.byte4 0x00800000;
|
||||||
|
.byte4(SDRAM_IGENERIC); /*SDRAM_Page2 */
|
||||||
|
.byte4 0x00C00000;
|
||||||
|
.byte4(SDRAM_IGENERIC); /*SDRAM_Page3 */
|
||||||
|
.byte4 0x01000000;
|
||||||
|
.byte4(SDRAM_IGENERIC); /*SDRAM_Page4 */
|
||||||
|
.byte4 0x01400000;
|
||||||
|
.byte4(SDRAM_IGENERIC); /*SDRAM_Page5 */
|
||||||
|
.byte4 0x01800000;
|
||||||
|
.byte4(SDRAM_IGENERIC); /*SDRAM_Page6 */
|
||||||
|
.byte4 0x01C00000;
|
||||||
|
.byte4(SDRAM_IGENERIC); /*SDRAM_Page7 */
|
||||||
|
#ifndef CONFIG_EZKIT /*STAMP Memory regions */
|
||||||
|
.byte4 0x02000000;
|
||||||
|
.byte4(SDRAM_IGENERIC); /*SDRAM_Page8 */
|
||||||
|
.byte4 0x02400000;
|
||||||
|
.byte4(SDRAM_IGENERIC); /*SDRAM_Page9 */
|
||||||
|
.byte4 0x02800000;
|
||||||
|
.byte4(SDRAM_IGENERIC); /*SDRAM_Page10 */
|
||||||
|
.byte4 0x02C00000;
|
||||||
|
.byte4(SDRAM_IGENERIC); /*SDRAM_Page11 */
|
||||||
|
.byte4 0x03000000;
|
||||||
|
.byte4(SDRAM_IGENERIC); /*SDRAM_Page12 */
|
||||||
|
.byte4 0x03400000;
|
||||||
|
.byte4(SDRAM_IGENERIC); /*SDRAM_Page13 */
|
||||||
|
.byte4 0x03800000;
|
||||||
|
.byte4(SDRAM_IGENERIC); /*SDRAM_Page14 */
|
||||||
|
.byte4 0x03C00000;
|
||||||
|
.byte4(SDRAM_IGENERIC); /*SDRAM_Page15 */
|
||||||
|
#endif
|
||||||
|
.byte4 0x20000000;
|
||||||
|
.byte4(SDRAM_EBIU); /* Async Memory Bank 2 (Secnd) */
|
||||||
|
|
||||||
|
#ifdef CONFIG_STAMP
|
||||||
|
.byte4 0x04000000;
|
||||||
|
.byte4(SDRAM_IGENERIC);
|
||||||
|
.byte4 0x04400000;
|
||||||
|
.byte4(SDRAM_IGENERIC);
|
||||||
|
.byte4 0x04800000;
|
||||||
|
.byte4(SDRAM_IGENERIC);
|
||||||
|
.byte4 0x04C00000;
|
||||||
|
.byte4(SDRAM_IGENERIC);
|
||||||
|
.byte4 0x05000000;
|
||||||
|
.byte4(SDRAM_IGENERIC);
|
||||||
|
.byte4 0x05400000;
|
||||||
|
.byte4(SDRAM_IGENERIC);
|
||||||
|
.byte4 0x05800000;
|
||||||
|
.byte4(SDRAM_IGENERIC);
|
||||||
|
.byte4 0x05C00000;
|
||||||
|
.byte4(SDRAM_IGENERIC);
|
||||||
|
.byte4 0x06000000;
|
||||||
|
.byte4(SDRAM_IGENERIC); /*SDRAM_Page25 */
|
||||||
|
.byte4 0x06400000;
|
||||||
|
.byte4(SDRAM_IGENERIC); /*SDRAM_Page26 */
|
||||||
|
.byte4 0x06800000;
|
||||||
|
.byte4(SDRAM_IGENERIC); /*SDRAM_Page27 */
|
||||||
|
.byte4 0x06C00000;
|
||||||
|
.byte4(SDRAM_IGENERIC); /*SDRAM_Page28 */
|
||||||
|
.byte4 0x07000000;
|
||||||
|
.byte4(SDRAM_IGENERIC); /*SDRAM_Page29 */
|
||||||
|
.byte4 0x07400000;
|
||||||
|
.byte4(SDRAM_IGENERIC); /*SDRAM_Page30 */
|
||||||
|
.byte4 0x07800000;
|
||||||
|
.byte4(SDRAM_IGENERIC); /*SDRAM_Page31 */
|
||||||
|
.byte4 0x07C00000;
|
||||||
|
.byte4(SDRAM_IKERNEL); /*SDRAM_Page32 */
|
||||||
|
#endif
|
||||||
|
.byte4 0xffffffff; /* end of section - termination */
|
||||||
|
|
||||||
|
/**********************************************************************
|
||||||
|
* PAGE DESCRIPTOR TABLE
|
||||||
|
*
|
||||||
|
**********************************************************************/
|
||||||
|
|
||||||
|
/* Till here we are discussing about the static memory management model.
|
||||||
|
* However, the operating envoronments commonly define more CPLB
|
||||||
|
* descriptors to cover the entire addressable memory than will fit into
|
||||||
|
* the available on-chip 16 CPLB MMRs. When this happens, the below table
|
||||||
|
* will be used which will hold all the potentially required CPLB descriptors
|
||||||
|
*
|
||||||
|
* This is how Page descriptor Table is implemented in uClinux/Blackfin.
|
||||||
|
*/
|
||||||
|
.global _dpdt_table _dpdt_table:.byte4 0x00000000;
|
||||||
|
.byte4(SDRAM_DKERNEL); /*SDRAM_Page0 */
|
||||||
|
.byte4 0x00400000;
|
||||||
|
.byte4(SDRAM_DKERNEL); /*SDRAM_Page1 */
|
||||||
|
.byte4 0x00800000;
|
||||||
|
.byte4(SDRAM_DGENERIC); /*SDRAM_Page2 */
|
||||||
|
.byte4 0x00C00000;
|
||||||
|
.byte4(SDRAM_DGENERIC); /*SDRAM_Page3 */
|
||||||
|
.byte4 0x01000000;
|
||||||
|
.byte4(SDRAM_DGENERIC); /*SDRAM_Page4 */
|
||||||
|
.byte4 0x01400000;
|
||||||
|
.byte4(SDRAM_DGENERIC); /*SDRAM_Page5 */
|
||||||
|
.byte4 0x01800000;
|
||||||
|
.byte4(SDRAM_DGENERIC); /*SDRAM_Page6 */
|
||||||
|
.byte4 0x01C00000;
|
||||||
|
.byte4(SDRAM_DGENERIC); /*SDRAM_Page7 */
|
||||||
|
|
||||||
|
#ifndef CONFIG_EZKIT
|
||||||
|
.byte4 0x02000000;
|
||||||
|
.byte4(SDRAM_DGENERIC); /*SDRAM_Page8 */
|
||||||
|
.byte4 0x02400000;
|
||||||
|
.byte4(SDRAM_DGENERIC); /*SDRAM_Page9 */
|
||||||
|
.byte4 0x02800000;
|
||||||
|
.byte4(SDRAM_DGENERIC); /*SDRAM_Page10 */
|
||||||
|
.byte4 0x02C00000;
|
||||||
|
.byte4(SDRAM_DGENERIC); /*SDRAM_Page11 */
|
||||||
|
.byte4 0x03000000;
|
||||||
|
.byte4(SDRAM_DGENERIC); /*SDRAM_Page12 */
|
||||||
|
.byte4 0x03400000;
|
||||||
|
.byte4(SDRAM_DGENERIC); /*SDRAM_Page13 */
|
||||||
|
.byte4 0x03800000;
|
||||||
|
.byte4(SDRAM_DGENERIC); /*SDRAM_Page14 */
|
||||||
|
.byte4 0x03C00000;
|
||||||
|
.byte4(SDRAM_DGENERIC); /*SDRAM_Page15 */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_STAMP
|
||||||
|
.byte4 0x04000000;
|
||||||
|
.byte4(SDRAM_DGENERIC);
|
||||||
|
.byte4 0x04400000;
|
||||||
|
.byte4(SDRAM_DGENERIC);
|
||||||
|
.byte4 0x04800000;
|
||||||
|
.byte4(SDRAM_DGENERIC);
|
||||||
|
.byte4 0x04C00000;
|
||||||
|
.byte4(SDRAM_DGENERIC);
|
||||||
|
.byte4 0x05000000;
|
||||||
|
.byte4(SDRAM_DGENERIC);
|
||||||
|
.byte4 0x05400000;
|
||||||
|
.byte4(SDRAM_DGENERIC);
|
||||||
|
.byte4 0x05800000;
|
||||||
|
.byte4(SDRAM_DGENERIC);
|
||||||
|
.byte4 0x05C00000;
|
||||||
|
.byte4(SDRAM_DGENERIC);
|
||||||
|
.byte4 0x06000000;
|
||||||
|
.byte4(SDRAM_DGENERIC); /*SDRAM_Page25 */
|
||||||
|
.byte4 0x06400000;
|
||||||
|
.byte4(SDRAM_DGENERIC); /*SDRAM_Page26 */
|
||||||
|
.byte4 0x06800000;
|
||||||
|
.byte4(SDRAM_DGENERIC); /*SDRAM_Page27 */
|
||||||
|
.byte4 0x06C00000;
|
||||||
|
.byte4(SDRAM_DGENERIC); /*SDRAM_Page28 */
|
||||||
|
.byte4 0x07000000;
|
||||||
|
.byte4(SDRAM_DGENERIC); /*SDRAM_Page29 */
|
||||||
|
.byte4 0x07400000;
|
||||||
|
.byte4(SDRAM_DGENERIC); /*SDRAM_Page30 */
|
||||||
|
.byte4 0x07800000;
|
||||||
|
.byte4(SDRAM_DGENERIC); /*SDRAM_Page31 */
|
||||||
|
.byte4 0x07C00000;
|
||||||
|
.byte4(SDRAM_DKERNEL); /*SDRAM_Page32 */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
.byte4 0x20000000;
|
||||||
|
.byte4(SDRAM_EBIU); /* Async Memory Bank 0 (Prim A) */
|
||||||
|
|
||||||
|
#if (BFIN_CPU == ADSP_BF533)
|
||||||
|
.byte4 0xFF800000;
|
||||||
|
.byte4(L1_DMEMORY);
|
||||||
|
.byte4 0xFF801000;
|
||||||
|
.byte4(L1_DMEMORY);
|
||||||
|
.byte4 0xFF802000;
|
||||||
|
.byte4(L1_DMEMORY);
|
||||||
|
.byte4 0xFF803000;
|
||||||
|
.byte4(L1_DMEMORY);
|
||||||
|
#endif
|
||||||
|
.byte4 0xFF804000;
|
||||||
|
.byte4(L1_DMEMORY);
|
||||||
|
.byte4 0xFF805000;
|
||||||
|
.byte4(L1_DMEMORY);
|
||||||
|
.byte4 0xFF806000;
|
||||||
|
.byte4(L1_DMEMORY);
|
||||||
|
.byte4 0xFF807000;
|
||||||
|
.byte4(L1_DMEMORY);
|
||||||
|
#if (BFIN_CPU == ADSP_BF533)
|
||||||
|
.byte4 0xFF900000;
|
||||||
|
.byte4(L1_DMEMORY);
|
||||||
|
.byte4 0xFF901000;
|
||||||
|
.byte4(L1_DMEMORY);
|
||||||
|
.byte4 0xFF902000;
|
||||||
|
.byte4(L1_DMEMORY);
|
||||||
|
.byte4 0xFF903000;
|
||||||
|
.byte4(L1_DMEMORY);
|
||||||
|
#endif
|
||||||
|
#if ((BFIN_CPU == ADSP_BF532) || (BFIN_CPU == ADSP_BF533))
|
||||||
|
.byte4 0xFF904000;
|
||||||
|
.byte4(L1_DMEMORY);
|
||||||
|
.byte4 0xFF905000;
|
||||||
|
.byte4(L1_DMEMORY);
|
||||||
|
.byte4 0xFF906000;
|
||||||
|
.byte4(L1_DMEMORY);
|
||||||
|
.byte4 0xFF907000;
|
||||||
|
.byte4(L1_DMEMORY);
|
||||||
|
#endif
|
||||||
|
.byte4 0xFFB00000;
|
||||||
|
.byte4(L1_DMEMORY);
|
||||||
|
|
||||||
|
.byte4 0xffffffff; /*end of section - termination */
|
||||||
|
|
||||||
|
#ifdef CONFIG_CPLB_INFO
|
||||||
|
.global _ipdt_swapcount_table; /* swapin count first, then swapout count */
|
||||||
|
_ipdt_swapcount_table:
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000; /* 10 */
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000; /* 20 */
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000; /* 30 */
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000; /* 40 */
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000; /* 50 */
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000; /* 60 */
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000; /* 70 */
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000; /* 80 */
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000; /* 90 */
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000; /* 100 */
|
||||||
|
|
||||||
|
.global _dpdt_swapcount_table; /* swapin count first, then swapout count */
|
||||||
|
_dpdt_swapcount_table:
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000; /* 10 */
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000; /* 20 */
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000; /* 30 */
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000; /* 40 */
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000; /* 50 */
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000; /* 60 */
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000; /* 70 */
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000; /* 80 */
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000; /* 80 */
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000; /* 100 */
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000; /* 110 */
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000;
|
||||||
|
.byte4 0x00000000; /* 120 */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /*__ARCH_BFINNOMMU_CPLBTAB_H*/
|
|
@ -28,7 +28,7 @@
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* include all Core registers and bit definitions */
|
/* include all Core registers and bit definitions */
|
||||||
#include <asm/cpu/def_LPBlackfin.h>
|
#include <asm/arch-common/def_LPBlackfin.h>
|
||||||
|
|
||||||
/* Helper macros
|
/* Helper macros
|
||||||
* usage:
|
* usage:
|
|
@ -19,9 +19,10 @@
|
||||||
#ifndef _DEF_BF533_EXTN_H
|
#ifndef _DEF_BF533_EXTN_H
|
||||||
#define _DEF_BF533_EXTN_H
|
#define _DEF_BF533_EXTN_H
|
||||||
|
|
||||||
#define OFFSET_( x ) ((x) & 0x0000FFFF) /* define macro for offset */
|
/* define macro for offset */
|
||||||
|
#define OFFSET_( x ) ((x) & 0x0000FFFF)
|
||||||
/* Delay inserted for PLL transition */
|
/* Delay inserted for PLL transition */
|
||||||
#define DELAY 0x1000
|
#define PLL_DELAY 0x1000
|
||||||
|
|
||||||
#define L1_ISRAM 0xFFA00000
|
#define L1_ISRAM 0xFFA00000
|
||||||
#define L1_ISRAM_END 0xFFA10000
|
#define L1_ISRAM_END 0xFFA10000
|
|
@ -0,0 +1,46 @@
|
||||||
|
/*
|
||||||
|
* U-boot - bf533_rtc.h
|
||||||
|
*
|
||||||
|
* Copyright (c) 2005 blackfin.uclinux.org
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _BF533_RTC_H_
|
||||||
|
#define _BF533_RTC_H_
|
||||||
|
|
||||||
|
void rtc_init(void);
|
||||||
|
void wait_for_complete(void);
|
||||||
|
void rtc_reset(void);
|
||||||
|
|
||||||
|
#define MIN_TO_SECS(_x_) (60 * _x_)
|
||||||
|
#define HRS_TO_SECS(_x_) (60 * 60 * _x_)
|
||||||
|
#define DAYS_TO_SECS(_x_) (24 * 60 * 60 * _x_)
|
||||||
|
|
||||||
|
#define NUM_SECS_IN_DAY (24 * 3600)
|
||||||
|
#define NUM_SECS_IN_HOUR (3600)
|
||||||
|
#define NUM_SECS_IN_MIN (60)
|
||||||
|
|
||||||
|
/* Shift values for RTC_STAT register */
|
||||||
|
#define DAY_BITS_OFF 17
|
||||||
|
#define HOUR_BITS_OFF 12
|
||||||
|
#define MIN_BITS_OFF 6
|
||||||
|
#define SEC_BITS_OFF 0
|
||||||
|
|
||||||
|
#endif
|
|
@ -0,0 +1,40 @@
|
||||||
|
/************************************************************************
|
||||||
|
*
|
||||||
|
* cdefBF53x.h
|
||||||
|
*
|
||||||
|
* (c) Copyright 2002-2003 Analog Devices, Inc. All rights reserved.
|
||||||
|
*
|
||||||
|
************************************************************************/
|
||||||
|
|
||||||
|
#ifndef _CDEFBF53x_H
|
||||||
|
#define _CDEFBF53x_H
|
||||||
|
|
||||||
|
#if defined(__ADSPBF531__)
|
||||||
|
#include <asm/arch-bf533/cdefBF531.h>
|
||||||
|
#elif defined(__ADSPBF532__)
|
||||||
|
#include <asm/arch-bf533/cdefBF532.h>
|
||||||
|
#elif defined(__ADSPBF533__)
|
||||||
|
#include <asm/arch-bf533/cdefBF533.h>
|
||||||
|
#include <asm/arch-bf533/defBF533_extn.h>
|
||||||
|
#include <asm/arch-bf533/bf533_serial.h>
|
||||||
|
#elif defined(__ADSPBF537__)
|
||||||
|
#include <asm/arch-bf537/cdefBF537.h>
|
||||||
|
#include <asm/arch-bf537/defBF537_extn.h>
|
||||||
|
#include <asm/arch-bf537/bf537_serial.h>
|
||||||
|
#elif defined(__ADSPBF561__)
|
||||||
|
#include <asm/arch-bf561/cdefBF561.h>
|
||||||
|
#include <asm/arch-bf561/defBF561_extn.h>
|
||||||
|
#include <asm/arch-bf561/bf561_serial.h>
|
||||||
|
#elif defined(__ADSPBF535__)
|
||||||
|
#include <asm/cpu/cdefBF5d35.h>
|
||||||
|
#elif defined(__AD6532__)
|
||||||
|
#include <asm/cpu/cdefAD6532.h>
|
||||||
|
#else
|
||||||
|
#if defined(__ADSPLPBLACKFIN__)
|
||||||
|
#include <asm/arch-bf533/cdefBF532.h>
|
||||||
|
#else
|
||||||
|
#include <asm/arch-bf533/cdefBF535.h>
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* _CDEFBF53x_H */
|
|
@ -1,38 +1,27 @@
|
||||||
/*
|
/************************************************************************
|
||||||
|
*
|
||||||
* cdef_LPBlackfin.h
|
* cdef_LPBlackfin.h
|
||||||
*
|
*
|
||||||
* This file is subject to the terms and conditions of the GNU Public
|
* (c) Copyright 2002-2003 Analog Devices, Inc. All rights reserved.
|
||||||
* License. See the file "COPYING" in the main directory of this archive
|
|
||||||
* for more details.
|
|
||||||
*
|
*
|
||||||
* Non-GPL License also available as part of VisualDSP++
|
************************************************************************/
|
||||||
*
|
|
||||||
* http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
|
|
||||||
*
|
|
||||||
* (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
|
|
||||||
*
|
|
||||||
* This file under source code control, please send bugs or changes to:
|
|
||||||
* dsptools.support@analog.com
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _CDEF_LPBLACKFIN_H
|
#ifndef _CDEF_LPBLACKFIN_H
|
||||||
#define _CDEF_LPBLACKFIN_H
|
#define _CDEF_LPBLACKFIN_H
|
||||||
|
|
||||||
/*
|
#if !defined(__ADSPLPBLACKFIN__)
|
||||||
* #if !defined(__ADSPLPBLACKFIN__)
|
#warning cdef_LPBlackfin.h should only be included for 532 compatible chips.
|
||||||
* #warning cdef_LPBlackfin.h should only be included for 532 compatible chips.
|
#endif
|
||||||
* #endif
|
#include <asm/arch-common/def_LPBlackfin.h>
|
||||||
*/
|
|
||||||
#include <asm/cpu/def_LPBlackfin.h>
|
|
||||||
|
|
||||||
/* Cache & SRAM Memory */
|
// Cache & SRAM Memory
|
||||||
#define pSRAM_BASE_ADDRESS ((volatile void **)SRAM_BASE_ADDRESS)
|
#define pSRAM_BASE_ADDRESS ((volatile void **)SRAM_BASE_ADDRESS)
|
||||||
#define pDMEM_CONTROL ((volatile unsigned long *)DMEM_CONTROL)
|
#define pDMEM_CONTROL ((volatile unsigned long *)DMEM_CONTROL)
|
||||||
#define pDCPLB_STATUS ((volatile unsigned long *)DCPLB_STATUS)
|
#define pDCPLB_STATUS ((volatile unsigned long *)DCPLB_STATUS)
|
||||||
#define pDCPLB_FAULT_ADDR ((volatile void **)DCPLB_FAULT_ADDR)
|
#define pDCPLB_FAULT_ADDR ((volatile void **)DCPLB_FAULT_ADDR)
|
||||||
|
/*
|
||||||
/* #define MMR_TIMEOUT 0xFFE00010 */ /* Memory-Mapped Register Timeout Register */
|
#define MMR_TIMEOUT 0xFFE00010 // Memory-Mapped Register Timeout Register
|
||||||
|
*/
|
||||||
#define pDCPLB_ADDR0 ((volatile void **)DCPLB_ADDR0)
|
#define pDCPLB_ADDR0 ((volatile void **)DCPLB_ADDR0)
|
||||||
#define pDCPLB_ADDR1 ((volatile void **)DCPLB_ADDR1)
|
#define pDCPLB_ADDR1 ((volatile void **)DCPLB_ADDR1)
|
||||||
#define pDCPLB_ADDR2 ((volatile void **)DCPLB_ADDR2)
|
#define pDCPLB_ADDR2 ((volatile void **)DCPLB_ADDR2)
|
||||||
|
@ -66,14 +55,14 @@
|
||||||
#define pDCPLB_DATA14 ((volatile unsigned long *)DCPLB_DATA14)
|
#define pDCPLB_DATA14 ((volatile unsigned long *)DCPLB_DATA14)
|
||||||
#define pDCPLB_DATA15 ((volatile unsigned long *)DCPLB_DATA15)
|
#define pDCPLB_DATA15 ((volatile unsigned long *)DCPLB_DATA15)
|
||||||
#define pDTEST_COMMAND ((volatile unsigned long *)DTEST_COMMAND)
|
#define pDTEST_COMMAND ((volatile unsigned long *)DTEST_COMMAND)
|
||||||
|
/*
|
||||||
/* #define DTEST_INDEX 0xFFE00304 */ /* Data Test Index Register */
|
#define DTEST_INDEX 0xFFE00304 // Data Test Index Register
|
||||||
|
*/
|
||||||
#define pDTEST_DATA0 ((volatile unsigned long *)DTEST_DATA0)
|
#define pDTEST_DATA0 ((volatile unsigned long *)DTEST_DATA0)
|
||||||
#define pDTEST_DATA1 ((volatile unsigned long *)DTEST_DATA1)
|
#define pDTEST_DATA1 ((volatile unsigned long *)DTEST_DATA1)
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* # define DTEST_DATA2 0xFFE00408 Data Test Data Register
|
#define DTEST_DATA2 0xFFE00408 // Data Test Data Register
|
||||||
* #define DTEST_DATA3 0xFFE0040C Data Test Data Register
|
#define DTEST_DATA3 0xFFE0040C // Data Test Data Register
|
||||||
*/
|
*/
|
||||||
#define pIMEM_CONTROL ((volatile unsigned long *)IMEM_CONTROL)
|
#define pIMEM_CONTROL ((volatile unsigned long *)IMEM_CONTROL)
|
||||||
#define pICPLB_STATUS ((volatile unsigned long *)ICPLB_STATUS)
|
#define pICPLB_STATUS ((volatile unsigned long *)ICPLB_STATUS)
|
||||||
|
@ -111,12 +100,13 @@
|
||||||
#define pICPLB_DATA14 ((volatile unsigned long *)ICPLB_DATA14)
|
#define pICPLB_DATA14 ((volatile unsigned long *)ICPLB_DATA14)
|
||||||
#define pICPLB_DATA15 ((volatile unsigned long *)ICPLB_DATA15)
|
#define pICPLB_DATA15 ((volatile unsigned long *)ICPLB_DATA15)
|
||||||
#define pITEST_COMMAND ((volatile unsigned long *)ITEST_COMMAND)
|
#define pITEST_COMMAND ((volatile unsigned long *)ITEST_COMMAND)
|
||||||
|
/*
|
||||||
/* #define ITEST_INDEX 0xFFE01304 */ /* Instruction Test Index Register */
|
#define ITEST_INDEX 0xFFE01304 // Instruction Test Index Register
|
||||||
|
*/
|
||||||
#define pITEST_DATA0 ((volatile unsigned long *)ITEST_DATA0)
|
#define pITEST_DATA0 ((volatile unsigned long *)ITEST_DATA0)
|
||||||
#define pITEST_DATA1 ((volatile unsigned long *)ITEST_DATA1)
|
#define pITEST_DATA1 ((volatile unsigned long *)ITEST_DATA1)
|
||||||
|
|
||||||
/* Event/Interrupt Registers */
|
// Event/Interrupt Registers
|
||||||
#define pEVT0 ((volatile void **)EVT0)
|
#define pEVT0 ((volatile void **)EVT0)
|
||||||
#define pEVT1 ((volatile void **)EVT1)
|
#define pEVT1 ((volatile void **)EVT1)
|
||||||
#define pEVT2 ((volatile void **)EVT2)
|
#define pEVT2 ((volatile void **)EVT2)
|
||||||
|
@ -137,24 +127,24 @@
|
||||||
#define pIPEND ((volatile unsigned long *)IPEND)
|
#define pIPEND ((volatile unsigned long *)IPEND)
|
||||||
#define pILAT ((volatile unsigned long *)ILAT)
|
#define pILAT ((volatile unsigned long *)ILAT)
|
||||||
|
|
||||||
/* Core Timer Registers */
|
// Core Timer Registers
|
||||||
#define pTCNTL ((volatile unsigned long *)TCNTL)
|
#define pTCNTL ((volatile unsigned long *)TCNTL)
|
||||||
#define pTPERIOD ((volatile unsigned long *)TPERIOD)
|
#define pTPERIOD ((volatile unsigned long *)TPERIOD)
|
||||||
#define pTSCALE ((volatile unsigned long *)TSCALE)
|
#define pTSCALE ((volatile unsigned long *)TSCALE)
|
||||||
#define pTCOUNT ((volatile unsigned long *)TCOUNT)
|
#define pTCOUNT ((volatile unsigned long *)TCOUNT)
|
||||||
|
|
||||||
/* Debug/MP/Emulation Registers */
|
// Debug/MP/Emulation Registers
|
||||||
#define pDSPID ((volatile unsigned long *)DSPID)
|
#define pDSPID ((volatile unsigned long *)DSPID)
|
||||||
#define pDBGCTL ((volatile unsigned long *)DBGCTL)
|
#define pDBGCTL ((volatile unsigned long *)DBGCTL)
|
||||||
#define pDBGSTAT ((volatile unsigned long *)DBGSTAT)
|
#define pDBGSTAT ((volatile unsigned long *)DBGSTAT)
|
||||||
#define pEMUDAT ((volatile unsigned long *)EMUDAT)
|
#define pEMUDAT ((volatile unsigned long *)EMUDAT)
|
||||||
|
|
||||||
/* Trace Buffer Registers */
|
// Trace Buffer Registers
|
||||||
#define pTBUFCTL ((volatile unsigned long *)TBUFCTL)
|
#define pTBUFCTL ((volatile unsigned long *)TBUFCTL)
|
||||||
#define pTBUFSTAT ((volatile unsigned long *)TBUFSTAT)
|
#define pTBUFSTAT ((volatile unsigned long *)TBUFSTAT)
|
||||||
#define pTBUF ((volatile void **)TBUF)
|
#define pTBUF ((volatile void **)TBUF)
|
||||||
|
|
||||||
/* Watch Point Control Registers */
|
// Watch Point Control Registers
|
||||||
#define pWPIACTL ((volatile unsigned long *)WPIACTL)
|
#define pWPIACTL ((volatile unsigned long *)WPIACTL)
|
||||||
#define pWPIA0 ((volatile void **)WPIA0)
|
#define pWPIA0 ((volatile void **)WPIA0)
|
||||||
#define pWPIA1 ((volatile void **)WPIA1)
|
#define pWPIA1 ((volatile void **)WPIA1)
|
||||||
|
@ -175,11 +165,13 @@
|
||||||
#define pWPDACNT1 ((volatile unsigned long *)WPDACNT1)
|
#define pWPDACNT1 ((volatile unsigned long *)WPDACNT1)
|
||||||
#define pWPSTAT ((volatile unsigned long *)WPSTAT)
|
#define pWPSTAT ((volatile unsigned long *)WPSTAT)
|
||||||
|
|
||||||
/* Performance Monitor Registers */
|
// Performance Monitor Registers
|
||||||
#define pPFCTL ((volatile unsigned long *)PFCTL)
|
#define pPFCTL ((volatile unsigned long *)PFCTL)
|
||||||
#define pPFCNTR0 ((volatile unsigned long *)PFCNTR0)
|
#define pPFCNTR0 ((volatile unsigned long *)PFCNTR0)
|
||||||
#define pPFCNTR1 ((volatile unsigned long *)PFCNTR1)
|
#define pPFCNTR1 ((volatile unsigned long *)PFCNTR1)
|
||||||
|
|
||||||
/* #define IPRIO 0xFFE02110 */ /* Core Interrupt Priority Register */
|
/*
|
||||||
|
#define IPRIO 0xFFE02110 // Core Interrupt Priority Register
|
||||||
|
*/
|
||||||
|
|
||||||
#endif /* _CDEF_LPBLACKFIN_H */
|
#endif /* _CDEF_LPBLACKFIN_H */
|
|
@ -92,13 +92,13 @@
|
||||||
|
|
||||||
/* ** Masks */
|
/* ** Masks */
|
||||||
/* Exception cause */
|
/* Exception cause */
|
||||||
#define SEQSTAT_EXCAUSE MK_BMSK_(SEQSTAT_EXCAUSE0_P ) | \
|
#define SEQSTAT_EXCAUSE ( MK_BMSK_(SEQSTAT_EXCAUSE0_P ) | \
|
||||||
MK_BMSK_(SEQSTAT_EXCAUSE1_P ) | \
|
MK_BMSK_(SEQSTAT_EXCAUSE1_P ) | \
|
||||||
MK_BMSK_(SEQSTAT_EXCAUSE2_P ) | \
|
MK_BMSK_(SEQSTAT_EXCAUSE2_P ) | \
|
||||||
MK_BMSK_(SEQSTAT_EXCAUSE3_P ) | \
|
MK_BMSK_(SEQSTAT_EXCAUSE3_P ) | \
|
||||||
MK_BMSK_(SEQSTAT_EXCAUSE4_P ) | \
|
MK_BMSK_(SEQSTAT_EXCAUSE4_P ) | \
|
||||||
MK_BMSK_(SEQSTAT_EXCAUSE5_P ) | \
|
MK_BMSK_(SEQSTAT_EXCAUSE5_P ) | \
|
||||||
0
|
0 )
|
||||||
|
|
||||||
/* Indicates whether the last reset was a software reset (=1) */
|
/* Indicates whether the last reset was a software reset (=1) */
|
||||||
#define SEQSTAT_SFTRESET MK_BMSK_(SEQSTAT_SFTRESET_P )
|
#define SEQSTAT_SFTRESET MK_BMSK_(SEQSTAT_SFTRESET_P )
|
|
@ -208,8 +208,7 @@ static __inline__ int __test_and_change_bit(int nr, volatile void *addr)
|
||||||
/*
|
/*
|
||||||
* This routine doesn't need to be atomic.
|
* This routine doesn't need to be atomic.
|
||||||
*/
|
*/
|
||||||
static __inline__ int __constant_test_bit(int nr,
|
static __inline__ int __constant_test_bit(int nr, const volatile void *addr)
|
||||||
const volatile void *addr)
|
|
||||||
{
|
{
|
||||||
return ((1UL << (nr & 31)) &
|
return ((1UL << (nr & 31)) &
|
||||||
(((const volatile unsigned int *)addr)[nr >> 5])) != 0;
|
(((const volatile unsigned int *)addr)[nr >> 5])) != 0;
|
||||||
|
@ -331,8 +330,7 @@ static __inline__ int ext2_test_bit(int nr, const volatile void *addr)
|
||||||
|
|
||||||
static __inline__ unsigned long ext2_find_next_zero_bit(void *addr,
|
static __inline__ unsigned long ext2_find_next_zero_bit(void *addr,
|
||||||
unsigned long size,
|
unsigned long size,
|
||||||
unsigned long
|
unsigned long offset)
|
||||||
offset)
|
|
||||||
{
|
{
|
||||||
unsigned long *p = ((unsigned long *)addr) + (offset >> 5);
|
unsigned long *p = ((unsigned long *)addr) + (offset >> 5);
|
||||||
unsigned long result = offset & ~31UL;
|
unsigned long result = offset & ~31UL;
|
||||||
|
|
|
@ -25,22 +25,16 @@
|
||||||
#ifndef _BLACKFIN_H_
|
#ifndef _BLACKFIN_H_
|
||||||
#define _BLACKFIN_H_
|
#define _BLACKFIN_H_
|
||||||
|
|
||||||
#include <asm/cpu/defBF533.h>
|
#if !(defined(__ASSEMBLY__) || defined(ASSEMBLY))
|
||||||
#include <asm/cpu/bf533_serial.h>
|
|
||||||
|
|
||||||
#ifndef __ASSEMBLY__
|
|
||||||
#ifndef ASSEMBLY
|
|
||||||
|
|
||||||
# ifdef SHARED_RESOURCES
|
# ifdef SHARED_RESOURCES
|
||||||
# include <asm/shared_resources.h>
|
# include <asm/shared_resources.h>
|
||||||
# endif
|
# endif
|
||||||
#include <asm/cpu/cdefBF53x.h>
|
|
||||||
|
|
||||||
#endif
|
# include <linux/types.h>
|
||||||
|
|
||||||
|
extern u_long get_sclk(void);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#include <asm/cpu/defBF533.h>
|
#include <asm/arch-common/cdefBF5xx.h>
|
||||||
#include <asm/cpu/defBF533_extn.h>
|
|
||||||
#include <asm/cpu/bf533_serial.h>
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -7,10 +7,11 @@
|
||||||
************************************************************************/
|
************************************************************************/
|
||||||
|
|
||||||
/* Defines necessary for cplb initialisation routines. */
|
/* Defines necessary for cplb initialisation routines. */
|
||||||
|
|
||||||
#ifndef _CPLB_H
|
#ifndef _CPLB_H
|
||||||
#define _CPLB_H
|
#define _CPLB_H
|
||||||
|
|
||||||
|
#define CONFIG_BLKFIN_WT
|
||||||
|
|
||||||
#define CPLB_ENABLE_ICACHE_P 0
|
#define CPLB_ENABLE_ICACHE_P 0
|
||||||
#define CPLB_ENABLE_DCACHE_P 1
|
#define CPLB_ENABLE_DCACHE_P 1
|
||||||
#define CPLB_ENABLE_DCACHE2_P 2
|
#define CPLB_ENABLE_DCACHE2_P 2
|
||||||
|
@ -45,4 +46,35 @@
|
||||||
#define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID
|
#define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID
|
||||||
#define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL
|
#define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL
|
||||||
|
|
||||||
|
/* Data Attibutes*/
|
||||||
|
|
||||||
|
#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
|
||||||
|
#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
|
||||||
|
#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
|
||||||
|
#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
|
||||||
|
|
||||||
|
/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
|
||||||
|
|
||||||
|
#define ANOMALY_05000158 0x200
|
||||||
|
|
||||||
|
#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
|
||||||
|
#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
|
||||||
|
#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
|
||||||
|
#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
|
||||||
|
#define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
|
||||||
|
#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
|
||||||
|
|
||||||
|
#else /*Write Through */
|
||||||
|
#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
|
||||||
|
#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
|
||||||
|
#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
|
||||||
|
#define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
|
||||||
|
#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_BF561)
|
||||||
|
#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 2) /* SDRAM +L1 + ASYNC_Memory */
|
||||||
|
#else
|
||||||
|
#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 1 + 3) /* SDRAM + L1 + ASYNC_Memory */
|
||||||
|
#endif
|
||||||
#endif /* _CPLB_H */
|
#endif /* _CPLB_H */
|
||||||
|
|
|
@ -1,572 +0,0 @@
|
||||||
/*This file is subject to the terms and conditions of the GNU General Public
|
|
||||||
* License.
|
|
||||||
*
|
|
||||||
* Blackfin BF533/2.6 support : LG Soft India
|
|
||||||
* Updated : Ashutosh Singh / Jahid Khan : Rrap Software Pvt Ltd
|
|
||||||
* Updated : 1. SDRAM_KERNEL, SDRAM_DKENEL are added as initial cplb's
|
|
||||||
* shouldn't be victimized. cplbmgr.S search logic is corrected
|
|
||||||
* to findout the appropriate victim.
|
|
||||||
* 2. SDRAM_IGENERIC in dpdt_table is replaced with SDRAM_DGENERIC
|
|
||||||
* : LG Soft India
|
|
||||||
*/
|
|
||||||
#include <config.h>
|
|
||||||
|
|
||||||
#ifndef __ARCH_BFINNOMMU_CPLBTAB_H
|
|
||||||
#define __ARCH_BFINNOMMU_CPLBTAB_H
|
|
||||||
|
|
||||||
/*************************************************************************
|
|
||||||
* ICPLB TABLE
|
|
||||||
*************************************************************************/
|
|
||||||
|
|
||||||
.data
|
|
||||||
|
|
||||||
/* This table is configurable */
|
|
||||||
|
|
||||||
.align 4;
|
|
||||||
|
|
||||||
/* Data Attibutes*/
|
|
||||||
|
|
||||||
#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
|
|
||||||
#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
|
|
||||||
#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
|
|
||||||
#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
|
|
||||||
|
|
||||||
/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
|
|
||||||
|
|
||||||
#define ANOMALY_05000158 0x200
|
|
||||||
#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
|
|
||||||
#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
|
|
||||||
#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
|
|
||||||
#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
|
|
||||||
#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
|
|
||||||
#define SDRAM_EBIU (PAGE_SIZE_1MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
|
|
||||||
|
|
||||||
#else /*Write Through*/
|
|
||||||
#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
|
|
||||||
#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
|
|
||||||
#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
|
|
||||||
#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
|
|
||||||
#define SDRAM_EBIU (PAGE_SIZE_1MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
.global icplb_table
|
|
||||||
icplb_table:
|
|
||||||
.byte4 0xFFA00000;
|
|
||||||
.byte4 (L1_IMEMORY);
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 (SDRAM_IKERNEL); /*SDRAM_Page1*/
|
|
||||||
.byte4 0x00400000;
|
|
||||||
.byte4 (SDRAM_IKERNEL); /*SDRAM_Page1*/
|
|
||||||
.byte4 0x07C00000;
|
|
||||||
.byte4 (SDRAM_IKERNEL); /*SDRAM_Page14*/
|
|
||||||
.byte4 0x00800000;
|
|
||||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page2*/
|
|
||||||
.byte4 0x00C00000;
|
|
||||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page2*/
|
|
||||||
.byte4 0x01000000;
|
|
||||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page4*/
|
|
||||||
.byte4 0x01400000;
|
|
||||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page5*/
|
|
||||||
.byte4 0x01800000;
|
|
||||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page6*/
|
|
||||||
.byte4 0x01C00000;
|
|
||||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page7*/
|
|
||||||
#ifndef CONFIG_EZKIT /*STAMP Memory regions*/
|
|
||||||
.byte4 0x02000000;
|
|
||||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page8*/
|
|
||||||
.byte4 0x02400000;
|
|
||||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page9*/
|
|
||||||
.byte4 0x02800000;
|
|
||||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page10*/
|
|
||||||
.byte4 0x02C00000;
|
|
||||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page11*/
|
|
||||||
.byte4 0x03000000;
|
|
||||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page12*/
|
|
||||||
.byte4 0x03400000;
|
|
||||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page13*/
|
|
||||||
#endif
|
|
||||||
.byte4 0xffffffff; /* end of section - termination*/
|
|
||||||
|
|
||||||
.align 4;
|
|
||||||
.global ipdt_table
|
|
||||||
ipdt_table:
|
|
||||||
#ifdef CONFIG_CPLB_INFO
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 (SDRAM_IKERNEL); /*SDRAM_Page0*/
|
|
||||||
.byte4 0x00400000;
|
|
||||||
.byte4 (SDRAM_IKERNEL); /*SDRAM_Page1*/
|
|
||||||
#endif
|
|
||||||
.byte4 0x00800000;
|
|
||||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page2*/
|
|
||||||
.byte4 0x00C00000;
|
|
||||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page3*/
|
|
||||||
.byte4 0x01000000;
|
|
||||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page4*/
|
|
||||||
.byte4 0x01400000;
|
|
||||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page5*/
|
|
||||||
.byte4 0x01800000;
|
|
||||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page6*/
|
|
||||||
.byte4 0x01C00000;
|
|
||||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page7*/
|
|
||||||
#ifndef CONFIG_EZKIT /*STAMP Memory regions*/
|
|
||||||
.byte4 0x02000000;
|
|
||||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page8*/
|
|
||||||
.byte4 0x02400000;
|
|
||||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page9*/
|
|
||||||
.byte4 0x02800000;
|
|
||||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page10*/
|
|
||||||
.byte4 0x02C00000;
|
|
||||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page11*/
|
|
||||||
.byte4 0x03000000;
|
|
||||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page12*/
|
|
||||||
.byte4 0x03400000;
|
|
||||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page13*/
|
|
||||||
.byte4 0x03800000;
|
|
||||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page14*/
|
|
||||||
.byte4 0x03C00000;
|
|
||||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page15*/
|
|
||||||
#endif
|
|
||||||
.byte4 0x20200000;
|
|
||||||
.byte4 (SDRAM_EBIU); /* Async Memory Bank 2 (Secnd)*/
|
|
||||||
.byte4 0x20100000;
|
|
||||||
.byte4 (SDRAM_EBIU); /* Async Memory Bank 1 (Prim B)*/
|
|
||||||
.byte4 0x20000000;
|
|
||||||
.byte4 (SDRAM_EBIU); /* Async Memory Bank 0 (Prim A)*/
|
|
||||||
.byte4 0x20300000; /*Fix for Network*/
|
|
||||||
.byte4 (SDRAM_EBIU); /*Async Memory bank 3*/
|
|
||||||
|
|
||||||
#ifdef CONFIG_STAMP
|
|
||||||
.byte4 0x04000000;
|
|
||||||
.byte4 (SDRAM_IGENERIC);
|
|
||||||
.byte4 0x04400000;
|
|
||||||
.byte4 (SDRAM_IGENERIC);
|
|
||||||
.byte4 0x04800000;
|
|
||||||
.byte4 (SDRAM_IGENERIC);
|
|
||||||
.byte4 0x04C00000;
|
|
||||||
.byte4 (SDRAM_IGENERIC);
|
|
||||||
.byte4 0x05000000;
|
|
||||||
.byte4 (SDRAM_IGENERIC);
|
|
||||||
.byte4 0x05400000;
|
|
||||||
.byte4 (SDRAM_IGENERIC);
|
|
||||||
.byte4 0x05800000;
|
|
||||||
.byte4 (SDRAM_IGENERIC);
|
|
||||||
.byte4 0x05C00000;
|
|
||||||
.byte4 (SDRAM_IGENERIC);
|
|
||||||
.byte4 0x06000000;
|
|
||||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page25*/
|
|
||||||
.byte4 0x06400000;
|
|
||||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page26*/
|
|
||||||
.byte4 0x06800000;
|
|
||||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page27*/
|
|
||||||
.byte4 0x06C00000;
|
|
||||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page28*/
|
|
||||||
.byte4 0x07000000;
|
|
||||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page29*/
|
|
||||||
.byte4 0x07400000;
|
|
||||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page30*/
|
|
||||||
.byte4 0x07800000;
|
|
||||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page31*/
|
|
||||||
#ifdef CONFIG_CPLB_INFO
|
|
||||||
.byte4 0x07C00000;
|
|
||||||
.byte4 (SDRAM_IKERNEL); /*SDRAM_Page32*/
|
|
||||||
#endif
|
|
||||||
#endif
|
|
||||||
.byte4 0xffffffff; /* end of section - termination*/
|
|
||||||
|
|
||||||
/*********************************************************************
|
|
||||||
* DCPLB TABLE
|
|
||||||
********************************************************************/
|
|
||||||
|
|
||||||
.global dcplb_table
|
|
||||||
dcplb_table:
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 (SDRAM_DKERNEL); /*SDRAM_Page1*/
|
|
||||||
.byte4 0x00400000;
|
|
||||||
.byte4 (SDRAM_DKERNEL); /*SDRAM_Page1*/
|
|
||||||
.byte4 0x07C00000;
|
|
||||||
.byte4 (SDRAM_DKERNEL); /*SDRAM_Page15*/
|
|
||||||
.byte4 0x00800000;
|
|
||||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page2*/
|
|
||||||
.byte4 0x00C00000;
|
|
||||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page3*/
|
|
||||||
.byte4 0x01000000;
|
|
||||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page4*/
|
|
||||||
.byte4 0x01400000;
|
|
||||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page5*/
|
|
||||||
.byte4 0x01800000;
|
|
||||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page6*/
|
|
||||||
.byte4 0x01C00000;
|
|
||||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page7*/
|
|
||||||
#ifndef CONFIG_EZKIT
|
|
||||||
.byte4 0x02000000;
|
|
||||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page8*/
|
|
||||||
.byte4 0x02400000;
|
|
||||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page9*/
|
|
||||||
.byte4 0x02800000;
|
|
||||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page10*/
|
|
||||||
.byte4 0x02C00000;
|
|
||||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page11*/
|
|
||||||
.byte4 0x03000000;
|
|
||||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page12*/
|
|
||||||
.byte4 0x03400000;
|
|
||||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page13*/
|
|
||||||
.byte4 0x03800000;
|
|
||||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page14*/
|
|
||||||
#endif
|
|
||||||
.byte4 0xffffffff; /*end of section - termination*/
|
|
||||||
|
|
||||||
/**********************************************************************
|
|
||||||
* PAGE DESCRIPTOR TABLE
|
|
||||||
*
|
|
||||||
**********************************************************************/
|
|
||||||
|
|
||||||
/* Till here we are discussing about the static memory management model.
|
|
||||||
* However, the operating envoronments commonly define more CPLB
|
|
||||||
* descriptors to cover the entire addressable memory than will fit into
|
|
||||||
* the available on-chip 16 CPLB MMRs. When this happens, the below table
|
|
||||||
* will be used which will hold all the potentially required CPLB descriptors
|
|
||||||
*
|
|
||||||
* This is how Page descriptor Table is implemented in uClinux/Blackfin.
|
|
||||||
*/
|
|
||||||
.global dpdt_table
|
|
||||||
dpdt_table:
|
|
||||||
#ifdef CONFIG_CPLB_INFO
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 (SDRAM_DKERNEL); /*SDRAM_Page0*/
|
|
||||||
.byte4 0x00400000;
|
|
||||||
.byte4 (SDRAM_DKERNEL); /*SDRAM_Page1*/
|
|
||||||
#endif
|
|
||||||
.byte4 0x00800000;
|
|
||||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page2*/
|
|
||||||
.byte4 0x00C00000;
|
|
||||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page3*/
|
|
||||||
.byte4 0x01000000;
|
|
||||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page4*/
|
|
||||||
.byte4 0x01400000;
|
|
||||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page5*/
|
|
||||||
.byte4 0x01800000;
|
|
||||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page6*/
|
|
||||||
.byte4 0x01C00000;
|
|
||||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page7*/
|
|
||||||
|
|
||||||
#ifndef CONFIG_EZKIT
|
|
||||||
.byte4 0x02000000;
|
|
||||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page8*/
|
|
||||||
.byte4 0x02400000;
|
|
||||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page9*/
|
|
||||||
.byte4 0x02800000;
|
|
||||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page10*/
|
|
||||||
.byte4 0x02C00000;
|
|
||||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page11*/
|
|
||||||
.byte4 0x03000000;
|
|
||||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page12*/
|
|
||||||
.byte4 0x03400000;
|
|
||||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page13*/
|
|
||||||
.byte4 0x03800000;
|
|
||||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page14*/
|
|
||||||
.byte4 0x03C00000;
|
|
||||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page15*/
|
|
||||||
#endif
|
|
||||||
.byte4 0x20200000;
|
|
||||||
.byte4 (SDRAM_EBIU); /* Async Memory Bank 2 (Secnd)*/
|
|
||||||
.byte4 0x20100000;
|
|
||||||
.byte4 (SDRAM_EBIU); /* Async Memory Bank 1 (Prim B)*/
|
|
||||||
.byte4 0x20000000;
|
|
||||||
.byte4 (SDRAM_EBIU); /* Async Memory Bank 0 (Prim A)*/
|
|
||||||
.byte4 0x20300000; /*Fix for Network*/
|
|
||||||
.byte4 (SDRAM_EBIU); /*Async Memory bank 3*/
|
|
||||||
|
|
||||||
#ifdef CONFIG_STAMP
|
|
||||||
.byte4 0x04000000;
|
|
||||||
.byte4 (SDRAM_DGENERIC);
|
|
||||||
.byte4 0x04400000;
|
|
||||||
.byte4 (SDRAM_DGENERIC);
|
|
||||||
.byte4 0x04800000;
|
|
||||||
.byte4 (SDRAM_DGENERIC);
|
|
||||||
.byte4 0x04C00000;
|
|
||||||
.byte4 (SDRAM_DGENERIC);
|
|
||||||
.byte4 0x05000000;
|
|
||||||
.byte4 (SDRAM_DGENERIC);
|
|
||||||
.byte4 0x05400000;
|
|
||||||
.byte4 (SDRAM_DGENERIC);
|
|
||||||
.byte4 0x05800000;
|
|
||||||
.byte4 (SDRAM_DGENERIC);
|
|
||||||
.byte4 0x05C00000;
|
|
||||||
.byte4 (SDRAM_DGENERIC);
|
|
||||||
.byte4 0x06000000;
|
|
||||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page25*/
|
|
||||||
.byte4 0x06400000;
|
|
||||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page26*/
|
|
||||||
.byte4 0x06800000;
|
|
||||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page27*/
|
|
||||||
.byte4 0x06C00000;
|
|
||||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page28*/
|
|
||||||
.byte4 0x07000000;
|
|
||||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page29*/
|
|
||||||
.byte4 0x07400000;
|
|
||||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page30*/
|
|
||||||
.byte4 0x07800000;
|
|
||||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page31*/
|
|
||||||
#ifdef CONFIG_CPLB_INFO
|
|
||||||
.byte4 0x07C00000;
|
|
||||||
.byte4 (SDRAM_DKERNEL); /*SDRAM_Page32*/
|
|
||||||
#endif
|
|
||||||
#endif
|
|
||||||
|
|
||||||
.byte4 0xFF900000;
|
|
||||||
.byte4 (L1_DMEMORY);
|
|
||||||
.byte4 0xFF901000;
|
|
||||||
.byte4 (L1_DMEMORY);
|
|
||||||
.byte4 0xFF902000;
|
|
||||||
.byte4 (L1_DMEMORY);
|
|
||||||
.byte4 0xFF903000;
|
|
||||||
.byte4 (L1_DMEMORY);
|
|
||||||
.byte4 0xFF904000;
|
|
||||||
.byte4 (L1_DMEMORY);
|
|
||||||
.byte4 0xFF905000;
|
|
||||||
.byte4 (L1_DMEMORY);
|
|
||||||
.byte4 0xFF906000;
|
|
||||||
.byte4 (L1_DMEMORY);
|
|
||||||
.byte4 0xFF907000;
|
|
||||||
.byte4 (L1_DMEMORY);
|
|
||||||
.byte4 0xFF800000;
|
|
||||||
.byte4 (L1_DMEMORY);
|
|
||||||
.byte4 0xFF801000;
|
|
||||||
.byte4 (L1_DMEMORY);
|
|
||||||
.byte4 0xFF802000;
|
|
||||||
.byte4 (L1_DMEMORY);
|
|
||||||
.byte4 0xFF803000;
|
|
||||||
.byte4 (L1_DMEMORY);
|
|
||||||
|
|
||||||
.byte4 0xffffffff; /*end of section - termination*/
|
|
||||||
|
|
||||||
#ifdef CONFIG_CPLB_INFO
|
|
||||||
.global ipdt_swapcount_table; /* swapin count first, then swapout count*/
|
|
||||||
ipdt_swapcount_table:
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000; /* 10 */
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000; /* 20 */
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000; /* 30 */
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000; /* 40 */
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000; /* 50 */
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000; /* 60 */
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000; /* 70 */
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000; /* 80 */
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000; /* 90 */
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000; /* 100 */
|
|
||||||
|
|
||||||
.global dpdt_swapcount_table; /* swapin count first, then swapout count*/
|
|
||||||
dpdt_swapcount_table:
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000; /* 10 */
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000; /* 20 */
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000; /* 30 */
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000; /* 40 */
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000; /* 50 */
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000; /* 60 */
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000; /* 70 */
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000; /* 80 */
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000; /* 80 */
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000; /* 100 */
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000; /* 110 */
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000;
|
|
||||||
.byte4 0x00000000; /* 120 */
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /*__ARCH_BFINNOMMU_CPLBTAB_H*/
|
|
|
@ -1,32 +0,0 @@
|
||||||
/************************************************************************
|
|
||||||
*
|
|
||||||
* cdefBF53x.h
|
|
||||||
*
|
|
||||||
* (c) Copyright 2002-2003 Analog Devices, Inc. All rights reserved.
|
|
||||||
*
|
|
||||||
************************************************************************/
|
|
||||||
|
|
||||||
#ifndef _CDEFBF53x_H
|
|
||||||
#define _CDEFBF53x_H
|
|
||||||
|
|
||||||
#if defined(__ADSPBF531__)
|
|
||||||
#include <asm/cpu/cdefBF531.h>
|
|
||||||
#elif defined(__ADSPBF532__)
|
|
||||||
#include <asm/cpu/cdefBF532.h>
|
|
||||||
#elif defined(__ADSPBF533__)
|
|
||||||
#include <asm/cpu/cdefBF533.h>
|
|
||||||
#elif defined(__ADSPBF561__)
|
|
||||||
#include <asm/cpu/cdefBF561.h>
|
|
||||||
#elif defined(__ADSPBF535__)
|
|
||||||
#include <asm/cpu/cdefBF535.h>
|
|
||||||
#elif defined(__AD6532__)
|
|
||||||
#include <sam/cpu/cdefAD6532.h>
|
|
||||||
#else
|
|
||||||
#if defined(__ADSPLPBLACKFIN__)
|
|
||||||
#include <asm/cpu/cdefBF532.h>
|
|
||||||
#else
|
|
||||||
#include <asm/cpu/cdefBF535.h>
|
|
||||||
#endif
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* _CDEFBF53x_H */
|
|
|
@ -370,16 +370,12 @@
|
||||||
#define STR1(X) #X
|
#define STR1(X) #X
|
||||||
|
|
||||||
#if defined(NEW_PT_REGS)
|
#if defined(NEW_PT_REGS)
|
||||||
|
|
||||||
#define PT_OFF_ORIG_R0 208
|
#define PT_OFF_ORIG_R0 208
|
||||||
#define PT_OFF_SR 8
|
#define PT_OFF_SR 8
|
||||||
|
|
||||||
#else
|
#else
|
||||||
|
|
||||||
#define PT_OFF_ORIG_R0 0x54
|
#define PT_OFF_ORIG_R0 0x54
|
||||||
#define PT_OFF_SR 0x38 /* seqstat in pt_regs */
|
#define PT_OFF_SR 0x38 /* seqstat in pt_regs */
|
||||||
|
|
||||||
#endif
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
#endif
|
||||||
|
|
|
@ -49,6 +49,11 @@ typedef struct global_data {
|
||||||
unsigned long reloc_off; /* Relocation Offset */
|
unsigned long reloc_off; /* Relocation Offset */
|
||||||
unsigned long env_addr; /* Address of Environment struct */
|
unsigned long env_addr; /* Address of Environment struct */
|
||||||
unsigned long env_valid; /* Checksum of Environment valid? */
|
unsigned long env_valid; /* Checksum of Environment valid? */
|
||||||
|
#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
|
||||||
|
unsigned long post_log_word; /* Record POST activities */
|
||||||
|
unsigned long post_init_f_time; /* When post_init_f started */
|
||||||
|
#endif
|
||||||
|
|
||||||
void **jt; /* jump table */
|
void **jt; /* jump table */
|
||||||
} gd_t;
|
} gd_t;
|
||||||
|
|
||||||
|
@ -59,6 +64,6 @@ typedef struct global_data {
|
||||||
#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
|
#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
|
||||||
#define GD_FLG_SILENT 0x00004 /* Silent mode */
|
#define GD_FLG_SILENT 0x00004 /* Silent mode */
|
||||||
|
|
||||||
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("P5")
|
#define DECLARE_GLOBAL_DATA_PTR register gd_t * volatile gd asm ("P5")
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -30,8 +30,14 @@
|
||||||
|
|
||||||
#include <linux/config.h>
|
#include <linux/config.h>
|
||||||
#ifdef CONFIG_EZKIT533
|
#ifdef CONFIG_EZKIT533
|
||||||
#include <asm/board/bf533_irq.h>
|
#include <asm/arch-bf533/irq.h>
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_EZKIT561
|
||||||
|
#include <asm/arch-bf561/irq.h>
|
||||||
#endif
|
#endif
|
||||||
#ifdef CONFIG_STAMP
|
#ifdef CONFIG_STAMP
|
||||||
#include <asm/board/bf533_irq.h>
|
#include <asm/arch-bf533/irq.h>
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_BF537
|
||||||
|
#include <asm/arch-bf537/irq.h>
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -87,7 +87,8 @@
|
||||||
#define IOMAP_WRITETHROUGH 3
|
#define IOMAP_WRITETHROUGH 3
|
||||||
|
|
||||||
#ifndef __ASSEMBLY__
|
#ifndef __ASSEMBLY__
|
||||||
extern void *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag);
|
extern void *__ioremap(unsigned long physaddr, unsigned long size,
|
||||||
|
int cacheflag);
|
||||||
extern void __iounmap(void *addr, unsigned long size);
|
extern void __iounmap(void *addr, unsigned long size);
|
||||||
extern inline void *ioremap(unsigned long physaddr, unsigned long size)
|
extern inline void *ioremap(unsigned long physaddr, unsigned long size)
|
||||||
{
|
{
|
||||||
|
@ -97,11 +98,13 @@ extern inline void *ioremap_nocache(unsigned long physaddr, unsigned long size)
|
||||||
{
|
{
|
||||||
return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
|
return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
|
||||||
}
|
}
|
||||||
extern inline void *ioremap_writethrough(unsigned long physaddr, unsigned long size)
|
extern inline void *ioremap_writethrough(unsigned long physaddr,
|
||||||
|
unsigned long size)
|
||||||
{
|
{
|
||||||
return __ioremap(physaddr, size, IOMAP_WRITETHROUGH);
|
return __ioremap(physaddr, size, IOMAP_WRITETHROUGH);
|
||||||
}
|
}
|
||||||
extern inline void *ioremap_fullcache(unsigned long physaddr, unsigned long size)
|
extern inline void *ioremap_fullcache(unsigned long physaddr,
|
||||||
|
unsigned long size)
|
||||||
{
|
{
|
||||||
return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
|
return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
|
||||||
}
|
}
|
||||||
|
|
|
@ -25,11 +25,6 @@
|
||||||
#ifndef _BLACKFIN_IO_H
|
#ifndef _BLACKFIN_IO_H
|
||||||
#define _BLACKFIN_IO_H
|
#define _BLACKFIN_IO_H
|
||||||
|
|
||||||
static inline void sync(void)
|
|
||||||
{
|
|
||||||
__asm__ __volatile__ asm("ssync" : : : "memory");
|
|
||||||
}
|
|
||||||
|
|
||||||
#ifdef __KERNEL__
|
#ifdef __KERNEL__
|
||||||
|
|
||||||
#include <linux/config.h>
|
#include <linux/config.h>
|
||||||
|
@ -40,6 +35,10 @@ extern void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words);
|
||||||
extern unsigned char cf_inb(volatile unsigned char *addr);
|
extern unsigned char cf_inb(volatile unsigned char *addr);
|
||||||
extern void cf_outb(unsigned char val, volatile unsigned char *addr);
|
extern void cf_outb(unsigned char val, volatile unsigned char *addr);
|
||||||
|
|
||||||
|
static inline void sync(void)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* These are for ISA/PCI shared memory _only_ and should never be used
|
* These are for ISA/PCI shared memory _only_ and should never be used
|
||||||
* on any other type of memory, including Zorro memory. They are meant to
|
* on any other type of memory, including Zorro memory. They are meant to
|
||||||
|
@ -51,7 +50,6 @@ extern void cf_outb(unsigned char val, volatile unsigned char* addr);
|
||||||
* memory location directly.
|
* memory location directly.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
|
||||||
#define readb(addr) ({ unsigned char __v = (*(volatile unsigned char *) (addr));asm("ssync;"); __v; })
|
#define readb(addr) ({ unsigned char __v = (*(volatile unsigned char *) (addr));asm("ssync;"); __v; })
|
||||||
#define readw(addr) ({ unsigned short __v = (*(volatile unsigned short *) (addr)); asm("ssync;");__v; })
|
#define readw(addr) ({ unsigned short __v = (*(volatile unsigned short *) (addr)); asm("ssync;");__v; })
|
||||||
#define readl(addr) ({ unsigned int __v = (*(volatile unsigned int *) (addr));asm("ssync;"); __v; })
|
#define readl(addr) ({ unsigned int __v = (*(volatile unsigned int *) (addr));asm("ssync;"); __v; })
|
||||||
|
@ -100,8 +98,7 @@ extern inline void *ioremap(unsigned long physaddr, unsigned long size)
|
||||||
{
|
{
|
||||||
return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
|
return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
|
||||||
}
|
}
|
||||||
extern inline void *ioremap_nocache(unsigned long physaddr,
|
extern inline void *ioremap_nocache(unsigned long physaddr, unsigned long size)
|
||||||
unsigned long size)
|
|
||||||
{
|
{
|
||||||
return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
|
return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
|
||||||
}
|
}
|
||||||
|
|
|
@ -39,7 +39,7 @@
|
||||||
#define _BLACKFIN_IRQ_H_
|
#define _BLACKFIN_IRQ_H_
|
||||||
|
|
||||||
#include <linux/config.h>
|
#include <linux/config.h>
|
||||||
#include <asm/cpu/bf533_irq.h>
|
#include <asm/hw_irq.h>
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* On the Blackfin, the interrupt structure allows remmapping of the hardware
|
* On the Blackfin, the interrupt structure allows remmapping of the hardware
|
||||||
|
|
|
@ -39,7 +39,8 @@ struct hwclk_time;
|
||||||
struct gendisk;
|
struct gendisk;
|
||||||
struct buffer_head;
|
struct buffer_head;
|
||||||
|
|
||||||
extern void (*mach_sched_init) (void (*handler) (int, void *, struct pt_regs *));
|
extern
|
||||||
|
void (*mach_sched_init) (void (*handler) (int, void *, struct pt_regs *));
|
||||||
|
|
||||||
/* machine dependent keyboard functions */
|
/* machine dependent keyboard functions */
|
||||||
extern int (*mach_keyb_init) (void);
|
extern int (*mach_keyb_init) (void);
|
||||||
|
|
|
@ -22,7 +22,13 @@
|
||||||
* MA 02111-1307 USA
|
* MA 02111-1307 USA
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if ( CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E )
|
#if (CONFIG_MEM_MT48LC16M16A2TG_75 || \
|
||||||
|
CONFIG_MEM_MT48LC64M4A2FB_7E || \
|
||||||
|
CONFIG_MEM_MT48LC16M8A2TG_75 || \
|
||||||
|
CONFIG_MEM_MT48LC8M16A2TG_7E || \
|
||||||
|
CONFIG_MEM_MT48LC8M32B2B5_7 || \
|
||||||
|
CONFIG_MEM_MT48LC32M8A2_75)
|
||||||
|
|
||||||
#if ( CONFIG_SCLK_HZ > 119402985 )
|
#if ( CONFIG_SCLK_HZ > 119402985 )
|
||||||
#define SDRAM_tRP TRP_2
|
#define SDRAM_tRP TRP_2
|
||||||
#define SDRAM_tRP_num 2
|
#define SDRAM_tRP_num 2
|
||||||
|
@ -66,7 +72,7 @@
|
||||||
#if ( CONFIG_SCLK_HZ > 59701493 ) && ( CONFIG_SCLK_HZ <= 66666667 )
|
#if ( CONFIG_SCLK_HZ > 59701493 ) && ( CONFIG_SCLK_HZ <= 66666667 )
|
||||||
#define SDRAM_tRP TRP_1
|
#define SDRAM_tRP TRP_1
|
||||||
#define SDRAM_tRP_num 1
|
#define SDRAM_tRP_num 1
|
||||||
#define SDRAM_tRAS TRAS_4
|
#define SDRAM_tRAS TRAS_3
|
||||||
#define SDRAM_tRAS_num 3
|
#define SDRAM_tRAS_num 3
|
||||||
#define SDRAM_tRCD TRCD_1
|
#define SDRAM_tRCD TRCD_1
|
||||||
#define SDRAM_tWR TWR_2
|
#define SDRAM_tWR TWR_2
|
||||||
|
@ -111,6 +117,34 @@
|
||||||
#define SDRAM_CL CL_2
|
#define SDRAM_CL CL_2
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if (CONFIG_MEM_MT48LC16M8A2TG_75)
|
||||||
|
/*SDRAM INFORMATION: */
|
||||||
|
#define SDRAM_Tref 64 /* Refresh period in milliseconds */
|
||||||
|
#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
|
||||||
|
#define SDRAM_CL CL_3
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CONFIG_MEM_MT48LC32M8A2_75)
|
||||||
|
/*SDRAM INFORMATION: */
|
||||||
|
#define SDRAM_Tref 64 /* Refresh period in milliseconds */
|
||||||
|
#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
|
||||||
|
#define SDRAM_CL CL_3
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CONFIG_MEM_MT48LC8M16A2TG_7E)
|
||||||
|
/*SDRAM INFORMATION: */
|
||||||
|
#define SDRAM_Tref 64 /* Refresh period in milliseconds */
|
||||||
|
#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
|
||||||
|
#define SDRAM_CL CL_2
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CONFIG_MEM_MT48LC8M32B2B5_7)
|
||||||
|
/*SDRAM INFORMATION: */
|
||||||
|
#define SDRAM_Tref 64 /* Refresh period in milliseconds */
|
||||||
|
#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
|
||||||
|
#define SDRAM_CL CL_3
|
||||||
|
#endif
|
||||||
|
|
||||||
#if ( CONFIG_MEM_SIZE == 128 )
|
#if ( CONFIG_MEM_SIZE == 128 )
|
||||||
#define SDRAM_SIZE EBSZ_128
|
#define SDRAM_SIZE EBSZ_128
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -112,11 +112,6 @@ extern __inline__ int get_order(unsigned long size)
|
||||||
#define virt_to_page(addr) (mem_map + (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT))
|
#define virt_to_page(addr) (mem_map + (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT))
|
||||||
#define VALID_PAGE(page) ((page - mem_map) < max_mapnr)
|
#define VALID_PAGE(page) ((page - mem_map) < max_mapnr)
|
||||||
|
|
||||||
#define BUG() do { \
|
|
||||||
\
|
|
||||||
while (1); /* dead-loop */ \
|
|
||||||
} while (0)
|
|
||||||
|
|
||||||
#define PAGE_BUG(page) do { \
|
#define PAGE_BUG(page) do { \
|
||||||
BUG(); \
|
BUG(); \
|
||||||
} while (0)
|
} while (0)
|
||||||
|
|
|
@ -126,8 +126,7 @@ static inline void release_thread(struct task_struct *dead_task)
|
||||||
{
|
{
|
||||||
}
|
}
|
||||||
|
|
||||||
extern int kernel_thread(int (*fn) (void *), void *arg,
|
extern int kernel_thread(int (*fn) (void *), void *arg, unsigned long flags);
|
||||||
unsigned long flags);
|
|
||||||
|
|
||||||
#define copy_segments(tsk, mm) do { } while (0)
|
#define copy_segments(tsk, mm) do { } while (0)
|
||||||
#define release_segments(mm) do { } while (0)
|
#define release_segments(mm) do { } while (0)
|
||||||
|
|
|
@ -75,12 +75,13 @@ extern unsigned long vme_brdtype;
|
||||||
|
|
||||||
extern int blackfin_num_memory; /* # of memory blocks found (and used) */
|
extern int blackfin_num_memory; /* # of memory blocks found (and used) */
|
||||||
extern int blackfin_realnum_memory; /* real # of memory blocks found */
|
extern int blackfin_realnum_memory; /* real # of memory blocks found */
|
||||||
extern struct mem_info blackfin_memory[NUM_MEMINFO]; /* memory description */
|
|
||||||
|
|
||||||
struct mem_info {
|
struct mem_info {
|
||||||
unsigned long addr; /* physical address of memory chunk */
|
unsigned long addr; /* physical address of memory chunk */
|
||||||
unsigned long size; /* length of memory chunk (in bytes) */
|
unsigned long size; /* length of memory chunk (in bytes) */
|
||||||
};
|
};
|
||||||
|
|
||||||
|
extern struct mem_info blackfin_memory[NUM_MEMINFO]; /* memory description */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -31,13 +31,17 @@
|
||||||
|
|
||||||
#include <asm/setup.h>
|
#include <asm/setup.h>
|
||||||
#include <asm/page.h>
|
#include <asm/page.h>
|
||||||
#include <asm/cpu/defBF533.h>
|
#include <config.h>
|
||||||
|
#include <asm/blackfin.h>
|
||||||
|
|
||||||
#define __HAVE_ARCH_STRCPY
|
#define __HAVE_ARCH_STRCPY
|
||||||
#define __HAVE_ARCH_STRNCPY
|
#define __HAVE_ARCH_STRNCPY
|
||||||
#define __HAVE_ARCH_STRCMP
|
#define __HAVE_ARCH_STRCMP
|
||||||
#define __HAVE_ARCH_STRNCMP
|
#define __HAVE_ARCH_STRNCMP
|
||||||
#define __HAVE_ARCH_MEMCPY
|
#define __HAVE_ARCH_MEMCPY
|
||||||
|
#define __HAVE_ARCH_MEMCMP
|
||||||
|
#define __HAVE_ARCH_MEMSET
|
||||||
|
#define __HAVE_ARCH_MEMMOVE
|
||||||
|
|
||||||
extern char *strcpy(char *dest, const char *src);
|
extern char *strcpy(char *dest, const char *src);
|
||||||
extern char *strncpy(char *dest, const char *src, size_t n);
|
extern char *strncpy(char *dest, const char *src, size_t n);
|
||||||
|
@ -46,6 +50,7 @@ extern int strncmp(const char *cs, const char *ct, size_t count);
|
||||||
extern void *memcpy(void *dest, const void *src, size_t count);
|
extern void *memcpy(void *dest, const void *src, size_t count);
|
||||||
extern void *memset(void *s, int c, size_t count);
|
extern void *memset(void *s, int c, size_t count);
|
||||||
extern int memcmp(const void *, const void *, __kernel_size_t);
|
extern int memcmp(const void *, const void *, __kernel_size_t);
|
||||||
|
extern void *memmove(void *dest, const void *src, size_t count);
|
||||||
|
|
||||||
#else /* KERNEL */
|
#else /* KERNEL */
|
||||||
|
|
||||||
|
|
|
@ -44,8 +44,7 @@ static inline int access_ok(int type, const void *addr, unsigned long size)
|
||||||
return ((unsigned long)addr < 0x10f00000); /* need final decision - Tony */
|
return ((unsigned long)addr < 0x10f00000); /* need final decision - Tony */
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline int verify_area(int type, const void *addr,
|
static inline int verify_area(int type, const void *addr, unsigned long size)
|
||||||
unsigned long size)
|
|
||||||
{
|
{
|
||||||
return access_ok(type, addr, size) ? 0 : -EFAULT;
|
return access_ok(type, addr, size) ? 0 : -EFAULT;
|
||||||
}
|
}
|
||||||
|
@ -173,8 +172,7 @@ static inline int bad_user_access_length(void)
|
||||||
* Copy a null terminated string from userspace.
|
* Copy a null terminated string from userspace.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
static inline long strncpy_from_user(char *dst, const char *src,
|
static inline long strncpy_from_user(char *dst, const char *src, long count)
|
||||||
long count)
|
|
||||||
{
|
{
|
||||||
char *tmp;
|
char *tmp;
|
||||||
strncpy(dst, src, count);
|
strncpy(dst, src, count);
|
||||||
|
|
|
@ -0,0 +1,228 @@
|
||||||
|
/*
|
||||||
|
* U-boot - Configuration file for BF533 EZKIT board
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CONFIG_EZKIT533_H__
|
||||||
|
#define __CONFIG_EZKIT533_H__
|
||||||
|
|
||||||
|
#define CONFIG_BAUDRATE 57600
|
||||||
|
#define CONFIG_STAMP 1
|
||||||
|
|
||||||
|
#define CONFIG_BOOTDELAY 5
|
||||||
|
#define CFG_AUTOLOAD "no" /*rarpb, bootp or dhcp commands will perform only a */
|
||||||
|
|
||||||
|
#define CFG_LONGHELP 1
|
||||||
|
#define CONFIG_CMDLINE_EDITING 1
|
||||||
|
#define CONFIG_LOADADDR 0x01000000 /* default load address */
|
||||||
|
#define CONFIG_BOOTCOMMAND "tftp $(loadaddr) linux"
|
||||||
|
//#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw"
|
||||||
|
|
||||||
|
#define CONFIG_DRIVER_SMC91111 1
|
||||||
|
#define CONFIG_SMC91111_BASE 0x20310300
|
||||||
|
|
||||||
|
#if 0
|
||||||
|
#define CONFIG_MII
|
||||||
|
#define CFG_DISCOVER_PHY
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define CONFIG_RTC_BFIN 1
|
||||||
|
#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Boot Mode Set
|
||||||
|
* Blackfin can support several boot modes
|
||||||
|
*/
|
||||||
|
#define BF533_BYPASS_BOOT 0x0001 /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */
|
||||||
|
#define BF533_PARA_BOOT 0x0002 /* Bootmode 1: Boot from 8-bit or 16-bit flash */
|
||||||
|
#define BF533_SPI_BOOT 0x0004 /* Bootmode 3: Boot from SPI flash */
|
||||||
|
/* Define the boot mode */
|
||||||
|
#define BFIN_BOOT_MODE BF533_BYPASS_BOOT
|
||||||
|
//#define BFIN_BOOT_MODE BF533_SPI_BOOT
|
||||||
|
|
||||||
|
#define CONFIG_PANIC_HANG 1
|
||||||
|
|
||||||
|
#define ADSP_BF531 0x31
|
||||||
|
#define ADSP_BF532 0x32
|
||||||
|
#define ADSP_BF533 0x33
|
||||||
|
#define BFIN_CPU ADSP_BF533
|
||||||
|
|
||||||
|
/* This sets the default state of the cache on U-Boot's boot */
|
||||||
|
#define CONFIG_ICACHE_ON
|
||||||
|
#define CONFIG_DCACHE_ON
|
||||||
|
|
||||||
|
/* Define where the uboot will be loaded by on-chip boot rom */
|
||||||
|
#define APP_ENTRY 0x00001000
|
||||||
|
|
||||||
|
/* CONFIG_CLKIN_HZ is any value in Hz */
|
||||||
|
#define CONFIG_CLKIN_HZ 27000000
|
||||||
|
/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
|
||||||
|
/* 1=CLKIN/2 */
|
||||||
|
#define CONFIG_CLKIN_HALF 0
|
||||||
|
/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
|
||||||
|
/* 1=bypass PLL */
|
||||||
|
#define CONFIG_PLL_BYPASS 0
|
||||||
|
/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */
|
||||||
|
/* Values can range from 1-64 */
|
||||||
|
#define CONFIG_VCO_MULT 22
|
||||||
|
/* CONFIG_CCLK_DIV controls what the core clock divider is */
|
||||||
|
/* Values can be 1, 2, 4, or 8 ONLY */
|
||||||
|
#define CONFIG_CCLK_DIV 1
|
||||||
|
/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
|
||||||
|
/* Values can range from 1-15 */
|
||||||
|
#define CONFIG_SCLK_DIV 5
|
||||||
|
/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
|
||||||
|
/* Values can range from 2-65535 */
|
||||||
|
/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
|
||||||
|
#define CONFIG_SPI_BAUD 2
|
||||||
|
#define CONFIG_SPI_BAUD_INITBLOCK 4
|
||||||
|
|
||||||
|
#if ( CONFIG_CLKIN_HALF == 0 )
|
||||||
|
#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
|
||||||
|
#else
|
||||||
|
#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CONFIG_PLL_BYPASS == 0)
|
||||||
|
#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
|
||||||
|
#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
|
||||||
|
#else
|
||||||
|
#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
|
||||||
|
#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define CONFIG_MEM_SIZE 32 /* 128, 64, 32, 16 */
|
||||||
|
#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */
|
||||||
|
#define CONFIG_MEM_MT48LC16M16A2TG_75 1
|
||||||
|
|
||||||
|
#define CONFIG_LOADS_ECHO 1
|
||||||
|
|
||||||
|
|
||||||
|
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
|
||||||
|
CFG_CMD_PING | \
|
||||||
|
CFG_CMD_ELF | \
|
||||||
|
CFG_CMD_I2C | \
|
||||||
|
CFG_CMD_JFFS2 | \
|
||||||
|
CFG_CMD_DATE)
|
||||||
|
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 ip=192.168.0.15:192.168.0.2:192.168.0.1:255.255.255.0:ezkit:eth0:off console=ttyBF0,57600"
|
||||||
|
|
||||||
|
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||||
|
#include <cmd_confdefs.h>
|
||||||
|
|
||||||
|
#define CFG_PROMPT "ezkit> " /* Monitor Command Prompt */
|
||||||
|
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||||
|
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||||
|
#else
|
||||||
|
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||||
|
#endif
|
||||||
|
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||||
|
#define CFG_MAXARGS 16 /* max number of command args */
|
||||||
|
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||||
|
#define CFG_MEMTEST_START 0x00000000 /* memtest works on */
|
||||||
|
#define CFG_MEMTEST_END ( (CONFIG_MEM_SIZE - 1) * 1024 * 1024) /* 1 ... 31 MB in DRAM */
|
||||||
|
#define CFG_LOAD_ADDR 0x01000000 /* default load address */
|
||||||
|
#define CFG_HZ 1000 /* decrementer freq: 10 ms ticks */
|
||||||
|
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||||
|
#define CFG_SDRAM_BASE 0x00000000
|
||||||
|
#define CFG_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 * 1024)
|
||||||
|
#define CFG_FLASH_BASE 0x20000000
|
||||||
|
|
||||||
|
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
||||||
|
#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
|
||||||
|
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
||||||
|
#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
|
||||||
|
#define CFG_GBL_DATA_SIZE 0x4000
|
||||||
|
#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
|
||||||
|
#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4)
|
||||||
|
|
||||||
|
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||||
|
#define CFG_FLASH0_BASE 0x20000000
|
||||||
|
#define CFG_FLASH1_BASE 0x20200000
|
||||||
|
#define CFG_FLASH2_BASE 0x20280000
|
||||||
|
#define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */
|
||||||
|
#define CFG_MAX_FLASH_SECT 40 /* max number of sectors on one chip */
|
||||||
|
|
||||||
|
#define CFG_ENV_IS_IN_FLASH 1
|
||||||
|
#define CFG_ENV_ADDR 0x20020000
|
||||||
|
#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */
|
||||||
|
|
||||||
|
/* JFFS Partition offset set */
|
||||||
|
#define CFG_JFFS2_FIRST_BANK 0
|
||||||
|
#define CFG_JFFS2_NUM_BANKS 1
|
||||||
|
/* 512k reserved for u-boot */
|
||||||
|
#define CFG_JFFS2_FIRST_SECTOR 11
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Stack sizes
|
||||||
|
*/
|
||||||
|
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
|
||||||
|
|
||||||
|
#define POLL_MODE 1
|
||||||
|
#define FLASH_TOT_SECT 40
|
||||||
|
#define FLASH_SIZE 0x220000
|
||||||
|
#define CFG_FLASH_SIZE 0x220000
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Initialize PSD4256 registers for using I2C
|
||||||
|
*/
|
||||||
|
#define CONFIG_MISC_INIT_R
|
||||||
|
|
||||||
|
/*
|
||||||
|
* I2C settings
|
||||||
|
* By default PF1 is used as SDA and PF0 as SCL on the Stamp board
|
||||||
|
*/
|
||||||
|
#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
|
||||||
|
/*
|
||||||
|
* Software (bit-bang) I2C driver configuration
|
||||||
|
*/
|
||||||
|
#define PF_SCL PF0
|
||||||
|
#define PF_SDA PF1
|
||||||
|
|
||||||
|
#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;")
|
||||||
|
#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
|
||||||
|
#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
|
||||||
|
#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
|
||||||
|
#define I2C_SDA(bit) if(bit) { \
|
||||||
|
*pFIO_FLAG_S = PF_SDA; \
|
||||||
|
asm("ssync;"); \
|
||||||
|
} \
|
||||||
|
else { \
|
||||||
|
*pFIO_FLAG_C = PF_SDA; \
|
||||||
|
asm("ssync;"); \
|
||||||
|
}
|
||||||
|
#define I2C_SCL(bit) if(bit) { \
|
||||||
|
*pFIO_FLAG_S = PF_SCL; \
|
||||||
|
asm("ssync;"); \
|
||||||
|
} \
|
||||||
|
else { \
|
||||||
|
*pFIO_FLAG_C = PF_SCL; \
|
||||||
|
asm("ssync;"); \
|
||||||
|
}
|
||||||
|
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
|
||||||
|
|
||||||
|
#define CFG_I2C_SPEED 50000
|
||||||
|
#define CFG_I2C_SLAVE 0xFE
|
||||||
|
|
||||||
|
#define CFG_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */
|
||||||
|
|
||||||
|
/* 0xFF, 0x7BB07BB0, 0x22547BB0 */
|
||||||
|
/* #define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
|
||||||
|
#define AMBCTL0VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \
|
||||||
|
~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN)
|
||||||
|
#define AMBCTL1VAL (B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \
|
||||||
|
B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN)
|
||||||
|
*/
|
||||||
|
#define AMGCTLVAL 0xFF
|
||||||
|
#define AMBCTL0VAL 0x7BB07BB0
|
||||||
|
#define AMBCTL1VAL 0xFFC27BB0
|
||||||
|
|
||||||
|
#define CONFIG_VDSP 1
|
||||||
|
|
||||||
|
#ifdef CONFIG_VDSP
|
||||||
|
#define ET_EXEC_VDSP 0x8
|
||||||
|
#define SHT_STRTAB_VDSP 0x1
|
||||||
|
#define ELFSHDRSIZE_VDSP 0x2C
|
||||||
|
#define VDSP_ENTRY_ADDR 0xFFA00000
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
|
@ -0,0 +1,475 @@
|
||||||
|
/*
|
||||||
|
* U-boot - Configuration file for BF533 STAMP board
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CONFIG_STAMP_H__
|
||||||
|
#define __CONFIG_STAMP_H__
|
||||||
|
|
||||||
|
#define CONFIG_STAMP 1
|
||||||
|
#define CONFIG_RTC_BFIN 1
|
||||||
|
#define CONFIG_BF533 1
|
||||||
|
/*
|
||||||
|
* Boot Mode Set
|
||||||
|
* Blackfin can support several boot modes
|
||||||
|
*/
|
||||||
|
#define BF533_BYPASS_BOOT 0x0001 /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */
|
||||||
|
#define BF533_PARA_BOOT 0x0002 /* Bootmode 1: Boot from 8-bit or 16-bit flash */
|
||||||
|
#define BF533_SPI_BOOT 0x0004 /* Bootmode 3: Boot from SPI flash */
|
||||||
|
/* Define the boot mode */
|
||||||
|
#define BFIN_BOOT_MODE BF533_BYPASS_BOOT
|
||||||
|
//#define BFIN_BOOT_MODE BF533_SPI_BOOT
|
||||||
|
|
||||||
|
#define CONFIG_PANIC_HANG 1
|
||||||
|
|
||||||
|
#define ADSP_BF531 0x31
|
||||||
|
#define ADSP_BF532 0x32
|
||||||
|
#define ADSP_BF533 0x33
|
||||||
|
#define BFIN_CPU ADSP_BF533
|
||||||
|
|
||||||
|
/* This sets the default state of the cache on U-Boot's boot */
|
||||||
|
#define CONFIG_ICACHE_ON
|
||||||
|
#define CONFIG_DCACHE_ON
|
||||||
|
|
||||||
|
/* Define where the uboot will be loaded by on-chip boot rom */
|
||||||
|
#define APP_ENTRY 0x00001000
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Stringize definitions - needed for environmental settings
|
||||||
|
*/
|
||||||
|
#define STRINGIZE2(x) #x
|
||||||
|
#define STRINGIZE(x) STRINGIZE2(x)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Board settings
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define CONFIG_DRIVER_SMC91111 1
|
||||||
|
#define CONFIG_SMC91111_BASE 0x20300300
|
||||||
|
|
||||||
|
/* FLASH/ETHERNET uses the same address range */
|
||||||
|
#define SHARED_RESOURCES 1
|
||||||
|
|
||||||
|
/* Is I2C bit-banged? */
|
||||||
|
#define CONFIG_SOFT_I2C 1
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Software (bit-bang) I2C driver configuration
|
||||||
|
*/
|
||||||
|
#define PF_SCL PF3
|
||||||
|
#define PF_SDA PF2
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Video splash screen support
|
||||||
|
*/
|
||||||
|
#define CONFIG_VIDEO 0
|
||||||
|
|
||||||
|
#define CONFIG_VDSP 1
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Clock settings
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* CONFIG_CLKIN_HZ is any value in Hz */
|
||||||
|
#define CONFIG_CLKIN_HZ 11059200
|
||||||
|
/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
|
||||||
|
/* 1=CLKIN/2 */
|
||||||
|
#define CONFIG_CLKIN_HALF 0
|
||||||
|
/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
|
||||||
|
/* 1=bypass PLL */
|
||||||
|
#define CONFIG_PLL_BYPASS 0
|
||||||
|
/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */
|
||||||
|
/* Values can range from 1-64 */
|
||||||
|
#define CONFIG_VCO_MULT 36
|
||||||
|
/* CONFIG_CCLK_DIV controls what the core clock divider is */
|
||||||
|
/* Values can be 1, 2, 4, or 8 ONLY */
|
||||||
|
#define CONFIG_CCLK_DIV 1
|
||||||
|
/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
|
||||||
|
/* Values can range from 1-15 */
|
||||||
|
#define CONFIG_SCLK_DIV 5
|
||||||
|
/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
|
||||||
|
/* Values can range from 2-65535 */
|
||||||
|
/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
|
||||||
|
#define CONFIG_SPI_BAUD 2
|
||||||
|
|
||||||
|
#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
|
||||||
|
#define CONFIG_SPI_BAUD_INITBLOCK 4
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Network settings
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if (CONFIG_DRIVER_SMC91111)
|
||||||
|
#if 0
|
||||||
|
#define CONFIG_MII
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* network support */
|
||||||
|
#define CONFIG_IPADDR 192.168.0.15
|
||||||
|
#define CONFIG_NETMASK 255.255.255.0
|
||||||
|
#define CONFIG_GATEWAYIP 192.168.0.1
|
||||||
|
#define CONFIG_SERVERIP 192.168.0.2
|
||||||
|
#define CONFIG_HOSTNAME STAMP
|
||||||
|
#define CONFIG_ROOTPATH /checkout/uClinux-dist/romfs
|
||||||
|
|
||||||
|
/* To remove hardcoding and enable MAC storage in EEPROM */
|
||||||
|
/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */
|
||||||
|
#endif /* CONFIG_DRIVER_SMC91111 */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Flash settings
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define CFG_FLASH_CFI /* The flash is CFI compatible */
|
||||||
|
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
|
||||||
|
#define CFG_FLASH_CFI_AMD_RESET
|
||||||
|
|
||||||
|
#define CFG_FLASH_BASE 0x20000000
|
||||||
|
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||||
|
#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
|
||||||
|
|
||||||
|
#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
|
||||||
|
#define CFG_ENV_IS_IN_FLASH 1
|
||||||
|
#define CFG_ENV_ADDR 0x20004000
|
||||||
|
#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
|
||||||
|
#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
|
||||||
|
#define CFG_ENV_IS_IN_EEPROM 1
|
||||||
|
#define CFG_ENV_OFFSET 0x4000
|
||||||
|
#define CFG_ENV_HEADER (CFG_ENV_OFFSET + 0x12A) /* 0x12A is the length of LDR file header */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define CFG_ENV_SIZE 0x2000
|
||||||
|
#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */
|
||||||
|
#define ENV_IS_EMBEDDED
|
||||||
|
|
||||||
|
#define CFG_FLASH_ERASE_TOUT 30000 /* Timeout for Chip Erase (in ms) */
|
||||||
|
#define CFG_FLASH_ERASEBLOCK_TOUT 5000 /* Timeout for Block Erase (in ms) */
|
||||||
|
#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
|
||||||
|
|
||||||
|
/* JFFS Partition offset set */
|
||||||
|
#define CFG_JFFS2_FIRST_BANK 0
|
||||||
|
#define CFG_JFFS2_NUM_BANKS 1
|
||||||
|
/* 512k reserved for u-boot */
|
||||||
|
#define CFG_JFFS2_FIRST_SECTOR 11
|
||||||
|
|
||||||
|
/*
|
||||||
|
* following timeouts shall be used once the
|
||||||
|
* Flash real protection is enabled
|
||||||
|
*/
|
||||||
|
#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
|
||||||
|
#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SDRAM settings & memory map
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define CONFIG_MEM_SIZE 128 /* 128, 64, 32, 16 */
|
||||||
|
#define CONFIG_MEM_ADD_WDTH 11 /* 8, 9, 10, 11 */
|
||||||
|
#define CONFIG_MEM_MT48LC64M4A2FB_7E 1
|
||||||
|
|
||||||
|
#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
|
||||||
|
#define CFG_MEMTEST_START 0x00000000 /* memtest works on */
|
||||||
|
#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
|
||||||
|
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define CFG_SDRAM_BASE 0x00000000
|
||||||
|
|
||||||
|
#define CFG_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 *1024)
|
||||||
|
#define CFG_MEMTEST_END (CFG_MAX_RAM_SIZE - 0x80000 - 1)
|
||||||
|
#define CONFIG_LOADADDR 0x01000000
|
||||||
|
|
||||||
|
#define CFG_LOAD_ADDR CONFIG_LOADADDR
|
||||||
|
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
||||||
|
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
||||||
|
#define CFG_GBL_DATA_SIZE 0x4000 /* Reserve 16k for Global Data */
|
||||||
|
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
|
||||||
|
|
||||||
|
#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - 0x40000)
|
||||||
|
#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
|
||||||
|
#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
|
||||||
|
#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4)
|
||||||
|
|
||||||
|
/* Check to make sure everything fits in SDRAM */
|
||||||
|
#if ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) > CFG_MAX_RAM_SIZE)
|
||||||
|
#error Memory Map does not fit into configuration
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if ( CONFIG_CLKIN_HALF == 0 )
|
||||||
|
#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
|
||||||
|
#else
|
||||||
|
#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CONFIG_PLL_BYPASS == 0)
|
||||||
|
#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
|
||||||
|
#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
|
||||||
|
#else
|
||||||
|
#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
|
||||||
|
#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
|
||||||
|
#if (CONFIG_SCLK_HZ / (2*CONFIG_SPI_BAUD) > 20000000)
|
||||||
|
#define CONFIG_SPI_FLASH_FAST_READ 1 /* Needed if SPI_CLK > 20 MHz */
|
||||||
|
#else
|
||||||
|
#undef CONFIG_SPI_FLASH_FAST_READ
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
/*
|
||||||
|
* Command settings
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define CFG_LONGHELP 1
|
||||||
|
#define CONFIG_CMDLINE_EDITING 1
|
||||||
|
|
||||||
|
#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
|
||||||
|
#define CFG_AUTOLOAD "no" /*rarpb, bootp or dhcp commands will perform only a */
|
||||||
|
#endif
|
||||||
|
/* configuration lookup from the BOOTP/DHCP server, */
|
||||||
|
/* but not try to load any image using TFTP */
|
||||||
|
|
||||||
|
#define CONFIG_BOOTDELAY 5
|
||||||
|
#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
|
||||||
|
#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
|
||||||
|
#define CONFIG_BOOTCOMMAND "run ramboot"
|
||||||
|
#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
|
||||||
|
#define CONFIG_BOOTCOMMAND "eeprom read 0x1000000 0x100000 0x180000;icache on;dcache on;bootm 0x1000000"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600"
|
||||||
|
|
||||||
|
#if (CONFIG_DRIVER_SMC91111)
|
||||||
|
#define CONFIG_COMMANDS1 (CONFIG_CMD_DFL | \
|
||||||
|
CFG_CMD_PING | \
|
||||||
|
CFG_CMD_ELF | \
|
||||||
|
CFG_CMD_CACHE | \
|
||||||
|
CFG_CMD_JFFS2 | \
|
||||||
|
CFG_CMD_EEPROM | \
|
||||||
|
CFG_CMD_DATE)
|
||||||
|
|
||||||
|
#else
|
||||||
|
#define CONFIG_COMMANDS1 (CONFIG_CMD_DFL | \
|
||||||
|
CFG_CMD_ELF | \
|
||||||
|
CFG_CMD_CACHE | \
|
||||||
|
CFG_CMD_JFFS2 | \
|
||||||
|
CFG_CMD_EEPROM | \
|
||||||
|
CFG_CMD_DATE)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
|
||||||
|
#if (CONFIG_DRIVER_SMC91111)
|
||||||
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||||
|
"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
|
||||||
|
"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
|
||||||
|
"$(rootpath) console=ttyBF0,57600\0" \
|
||||||
|
"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
|
||||||
|
"$(gatewayip):$(netmask):$(hostname):eth0:off\0" \
|
||||||
|
"ramboot=tftpboot $(loadaddr) linux; " \
|
||||||
|
"run ramargs;run addip;bootelf\0" \
|
||||||
|
"nfsboot=tftpboot $(loadaddr) linux; " \
|
||||||
|
"run nfsargs;run addip;bootelf\0" \
|
||||||
|
"flashboot=bootm 0x20100000\0" \
|
||||||
|
"update=tftpboot $(loadaddr) u-boot.bin; " \
|
||||||
|
"protect off 0x20000000 0x2003FFFF; erase 0x20000000 0x2003FFFF;" \
|
||||||
|
"cp.b $(loadaddr) 0x20000000 $(filesize)\0" \
|
||||||
|
""
|
||||||
|
#else
|
||||||
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||||
|
"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
|
||||||
|
"flashboot=bootm 0x20100000\0" \
|
||||||
|
""
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
|
||||||
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||||
|
"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
|
||||||
|
"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
|
||||||
|
"$(rootpath) console=ttyBF0,57600\0" \
|
||||||
|
"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
|
||||||
|
"$(gatewayip):$(netmask):$(hostname):eth0:off\0" \
|
||||||
|
"ramboot=tftpboot $(loadaddr) linux; " \
|
||||||
|
"run ramargs;run addip;bootelf\0" \
|
||||||
|
"nfsboot=tftpboot $(loadaddr) linux; " \
|
||||||
|
"run nfsargs;run addip;bootelf\0" \
|
||||||
|
"flashboot=bootm 0x20100000\0" \
|
||||||
|
"update=tftpboot $(loadaddr) u-boot.ldr;" \
|
||||||
|
"eeprom write $(loadaddr) 0x0 $(filesize);\0"\
|
||||||
|
""
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_SOFT_I2C
|
||||||
|
#if (!CONFIG_SOFT_I2C)
|
||||||
|
#undef CONFIG_SOFT_I2C
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CONFIG_SOFT_I2C)
|
||||||
|
#define CONFIG_COMMANDS2 CFG_CMD_I2C
|
||||||
|
#else
|
||||||
|
#define CONFIG_COMMANDS2 0
|
||||||
|
#endif /* CONFIG_SOFT_I2C */
|
||||||
|
|
||||||
|
#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
|
||||||
|
#define CONFIG_COMMANDS ( CONFIG_COMMANDS1 | CONFIG_COMMANDS2 | CFG_CMD_DHCP)
|
||||||
|
#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
|
||||||
|
#define CONFIG_COMMANDS ( CONFIG_COMMANDS1 | CONFIG_COMMANDS2)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||||
|
#include <cmd_confdefs.h>
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Console settings
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define CONFIG_BAUDRATE 57600
|
||||||
|
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||||
|
|
||||||
|
#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
|
||||||
|
#if (BFIN_CPU == ADSP_BF531)
|
||||||
|
#define CFG_PROMPT "serial_bf531> " /* Monitor Command Prompt */
|
||||||
|
#elif (BFIN_CPU == ADSP_BF532)
|
||||||
|
#define CFG_PROMPT "serial_bf532> " /* Monitor Command Prompt */
|
||||||
|
#else
|
||||||
|
#define CFG_PROMPT "serial_bf533> " /* Monitor Command Prompt */
|
||||||
|
#endif
|
||||||
|
#else
|
||||||
|
#if (BFIN_CPU == ADSP_BF531)
|
||||||
|
#define CFG_PROMPT "bf531> " /* Monitor Command Prompt */
|
||||||
|
#elif (BFIN_CPU == ADSP_BF532)
|
||||||
|
#define CFG_PROMPT "bf532> " /* Monitor Command Prompt */
|
||||||
|
#else
|
||||||
|
#define CFG_PROMPT "bf533> " /* Monitor Command Prompt */
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||||
|
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||||
|
#else
|
||||||
|
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||||
|
#endif
|
||||||
|
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||||
|
#define CFG_MAXARGS 16 /* max number of command args */
|
||||||
|
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||||
|
|
||||||
|
#define CONFIG_LOADS_ECHO 1
|
||||||
|
|
||||||
|
/*
|
||||||
|
* I2C settings
|
||||||
|
* By default PF2 is used as SDA and PF3 as SCL on the Stamp board
|
||||||
|
*/
|
||||||
|
#if (CONFIG_SOFT_I2C)
|
||||||
|
|
||||||
|
#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;")
|
||||||
|
#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
|
||||||
|
#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
|
||||||
|
#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
|
||||||
|
#define I2C_SDA(bit) if(bit) { \
|
||||||
|
*pFIO_FLAG_S = PF_SDA; \
|
||||||
|
asm("ssync;"); \
|
||||||
|
} \
|
||||||
|
else { \
|
||||||
|
*pFIO_FLAG_C = PF_SDA; \
|
||||||
|
asm("ssync;"); \
|
||||||
|
}
|
||||||
|
#define I2C_SCL(bit) if(bit) { \
|
||||||
|
*pFIO_FLAG_S = PF_SCL; \
|
||||||
|
asm("ssync;"); \
|
||||||
|
} \
|
||||||
|
else { \
|
||||||
|
*pFIO_FLAG_C = PF_SCL; \
|
||||||
|
asm("ssync;"); \
|
||||||
|
}
|
||||||
|
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
|
||||||
|
|
||||||
|
#define CFG_I2C_SPEED 50000
|
||||||
|
#define CFG_I2C_SLAVE 0xFE
|
||||||
|
#endif /* CONFIG_SOFT_I2C */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Compact Flash settings
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Enabled below option for CF support */
|
||||||
|
/* #define CONFIG_STAMP_CF 1 */
|
||||||
|
|
||||||
|
#if defined(CONFIG_STAMP_CF) && (CONFIG_COMMANDS & CFG_CMD_IDE)
|
||||||
|
|
||||||
|
#define CONFIG_MISC_INIT_R 1
|
||||||
|
#define CONFIG_DOS_PARTITION 1
|
||||||
|
/*
|
||||||
|
* IDE/ATA stuff
|
||||||
|
*/
|
||||||
|
#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
|
||||||
|
#undef CONFIG_IDE_LED /* no led for ide supported */
|
||||||
|
#undef CONFIG_IDE_RESET /* no reset for ide supported */
|
||||||
|
|
||||||
|
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
|
||||||
|
#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
|
||||||
|
|
||||||
|
#define CFG_ATA_BASE_ADDR 0x20200000
|
||||||
|
#define CFG_ATA_IDE0_OFFSET 0x0000
|
||||||
|
|
||||||
|
#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
|
||||||
|
#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
|
||||||
|
#define CFG_ATA_ALT_OFFSET 0x0007 /* Offset for alternate registers */
|
||||||
|
|
||||||
|
#define CFG_ATA_STRIDE 2
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Miscellaneous configurable options
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define CFG_HZ 1000 /* 1ms time tick */
|
||||||
|
|
||||||
|
#define CFG_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */
|
||||||
|
|
||||||
|
#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
|
||||||
|
|
||||||
|
#define CONFIG_SPI
|
||||||
|
|
||||||
|
#ifdef CONFIG_VIDEO
|
||||||
|
#if (CONFIG_VIDEO)
|
||||||
|
#define CONFIG_SPLASH_SCREEN 1
|
||||||
|
#define CONFIG_SILENT_CONSOLE 1
|
||||||
|
#else
|
||||||
|
#undef CONFIG_VIDEO
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* FLASH organization and environment definitions
|
||||||
|
*/
|
||||||
|
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||||
|
|
||||||
|
/* 0xFF, 0xBBC3BBc3, 0x99B39983 */
|
||||||
|
/*#define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
|
||||||
|
#define AMBCTL0VAL (B1WAT_11 | B1RAT_11 | B1HT_3 | B1ST_4 | B1TT_4 | B1RDYPOL | \
|
||||||
|
B1RDYEN | B0WAT_11 | B0RAT_11 | B0HT_3 | B0ST_4 | B0TT_4 | B0RDYPOL | B0RDYEN)
|
||||||
|
#define AMBCTL1VAL (B3WAT_9 | B3RAT_9 | B3HT_2 | B3ST_3 | B3TT_4 | B3RDYPOL | \
|
||||||
|
B3RDYEN | B2WAT_9 | B2RAT_9 | B2HT_2 | B2ST_4 | B2TT_4 | B2RDYPOL | B2RDYEN)
|
||||||
|
*/
|
||||||
|
#define AMGCTLVAL 0xFF
|
||||||
|
#define AMBCTL0VAL 0xBBC3BBC3
|
||||||
|
#define AMBCTL1VAL 0x99B39983
|
||||||
|
#define CF_AMBCTL1VAL 0x99B3ffc2
|
||||||
|
|
||||||
|
#ifdef CONFIG_VDSP
|
||||||
|
#define ET_EXEC_VDSP 0x8
|
||||||
|
#define SHT_STRTAB_VDSP 0x1
|
||||||
|
#define ELFSHDRSIZE_VDSP 0x2C
|
||||||
|
#define VDSP_ENTRY_ADDR 0xFFA00000
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#endif
|
|
@ -1,188 +0,0 @@
|
||||||
#ifndef __CONFIG_EZKIT533_H__
|
|
||||||
#define __CONFIG_EZKIT533_H__
|
|
||||||
|
|
||||||
#define CFG_LONGHELP 1
|
|
||||||
#define CONFIG_BAUDRATE 57600
|
|
||||||
#define CONFIG_STAMP 1
|
|
||||||
#define CONFIG_BOOTDELAY 5
|
|
||||||
|
|
||||||
#define CONFIG_DRIVER_SMC91111 1
|
|
||||||
#define CONFIG_SMC91111_BASE 0x20310300
|
|
||||||
#if 0
|
|
||||||
#define CONFIG_MII
|
|
||||||
#define CFG_DISCOVER_PHY
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define CONFIG_RTC_BF533 1
|
|
||||||
#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
|
|
||||||
|
|
||||||
/* CONFIG_CLKIN_HZ is any value in Hz */
|
|
||||||
#define CONFIG_CLKIN_HZ 27000000
|
|
||||||
/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
|
|
||||||
/* 1=CLKIN/2 */
|
|
||||||
#define CONFIG_CLKIN_HALF 0
|
|
||||||
/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
|
|
||||||
/* 1=bypass PLL */
|
|
||||||
#define CONFIG_PLL_BYPASS 0
|
|
||||||
/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */
|
|
||||||
/* Values can range from 1-64 */
|
|
||||||
#define CONFIG_VCO_MULT 22
|
|
||||||
/* CONFIG_CCLK_DIV controls what the core clock divider is */
|
|
||||||
/* Values can be 1, 2, 4, or 8 ONLY */
|
|
||||||
#define CONFIG_CCLK_DIV 1
|
|
||||||
/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
|
|
||||||
/* Values can range from 1-15 */
|
|
||||||
#define CONFIG_SCLK_DIV 5
|
|
||||||
|
|
||||||
#if ( CONFIG_CLKIN_HALF == 0 )
|
|
||||||
#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
|
|
||||||
#else
|
|
||||||
#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if (CONFIG_PLL_BYPASS == 0)
|
|
||||||
#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
|
|
||||||
#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
|
|
||||||
#else
|
|
||||||
#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
|
|
||||||
#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define CONFIG_MEM_SIZE 32 /* 128, 64, 32, 16 */
|
|
||||||
#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */
|
|
||||||
#define CONFIG_MEM_MT48LC16M16A2TG_75 1
|
|
||||||
|
|
||||||
#define CONFIG_LOADS_ECHO 1
|
|
||||||
|
|
||||||
|
|
||||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
|
|
||||||
CFG_CMD_PING | \
|
|
||||||
CFG_CMD_ELF | \
|
|
||||||
CFG_CMD_I2C | \
|
|
||||||
CFG_CMD_JFFS2 | \
|
|
||||||
CFG_CMD_DATE)
|
|
||||||
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 ip=192.168.0.15:192.168.0.2:192.168.0.1:255.255.255.0:ezkit:eth0:off"
|
|
||||||
|
|
||||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
|
||||||
#include <cmd_confdefs.h>
|
|
||||||
|
|
||||||
#define CFG_PROMPT "ezkit> " /* Monitor Command Prompt */
|
|
||||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
|
||||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
|
||||||
#else
|
|
||||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
|
||||||
#endif
|
|
||||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
|
||||||
#define CFG_MAXARGS 16 /* max number of command args */
|
|
||||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
|
||||||
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
|
|
||||||
#define CFG_MEMTEST_END 0x01F00000 /* 1 ... 31 MB in DRAM */
|
|
||||||
#define CFG_LOAD_ADDR 0x01000000 /* default load address */
|
|
||||||
#define CFG_HZ 1000 /* decrementer freq: 10 ms ticks */
|
|
||||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
|
||||||
#define CFG_SDRAM_BASE 0x00000000
|
|
||||||
#define CFG_MAX_RAM_SIZE 0x02000000
|
|
||||||
#define CFG_FLASH_BASE 0x20000000
|
|
||||||
|
|
||||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
|
||||||
#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
|
|
||||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
|
||||||
#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
|
|
||||||
#define CFG_GBL_DATA_SIZE 0x4000
|
|
||||||
#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
|
|
||||||
#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4)
|
|
||||||
|
|
||||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
|
||||||
#define CFG_FLASH0_BASE 0x20000000
|
|
||||||
#define CFG_FLASH1_BASE 0x20200000
|
|
||||||
#define CFG_FLASH2_BASE 0x20280000
|
|
||||||
#define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */
|
|
||||||
#define CFG_MAX_FLASH_SECT 40 /* max number of sectors on one chip */
|
|
||||||
|
|
||||||
#define CFG_ENV_IS_IN_FLASH 1
|
|
||||||
#define CFG_ENV_ADDR 0x20020000
|
|
||||||
#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */
|
|
||||||
|
|
||||||
/* JFFS Partition offset set */
|
|
||||||
#define CFG_JFFS2_FIRST_BANK 0
|
|
||||||
#define CFG_JFFS2_NUM_BANKS 1
|
|
||||||
/* 512k reserved for u-boot */
|
|
||||||
#define CFG_JFFS2_FIRST_SECTOR 11
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Stack sizes
|
|
||||||
*/
|
|
||||||
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
|
|
||||||
|
|
||||||
#define POLL_MODE 1
|
|
||||||
#define FLASH_TOT_SECT 40
|
|
||||||
#define FLASH_SIZE 0x220000
|
|
||||||
#define CFG_FLASH_SIZE 0x220000
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Initialize PSD4256 registers for using I2C
|
|
||||||
*/
|
|
||||||
#define CONFIG_MISC_INIT_R
|
|
||||||
|
|
||||||
/*
|
|
||||||
* I2C settings
|
|
||||||
* By default PF1 is used as SDA and PF0 as SCL on the Stamp board
|
|
||||||
*/
|
|
||||||
#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
|
|
||||||
/*
|
|
||||||
* Software (bit-bang) I2C driver configuration
|
|
||||||
*/
|
|
||||||
#define PF_SCL PF0
|
|
||||||
#define PF_SDA PF1
|
|
||||||
|
|
||||||
#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;")
|
|
||||||
#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
|
|
||||||
#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
|
|
||||||
#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
|
|
||||||
#define I2C_SDA(bit) if(bit) { \
|
|
||||||
*pFIO_FLAG_S = PF_SDA; \
|
|
||||||
asm("ssync;"); \
|
|
||||||
} \
|
|
||||||
else { \
|
|
||||||
*pFIO_FLAG_C = PF_SDA; \
|
|
||||||
asm("ssync;"); \
|
|
||||||
}
|
|
||||||
#define I2C_SCL(bit) if(bit) { \
|
|
||||||
*pFIO_FLAG_S = PF_SCL; \
|
|
||||||
asm("ssync;"); \
|
|
||||||
} \
|
|
||||||
else { \
|
|
||||||
*pFIO_FLAG_C = PF_SCL; \
|
|
||||||
asm("ssync;"); \
|
|
||||||
}
|
|
||||||
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
|
|
||||||
|
|
||||||
#define CFG_I2C_SPEED 50000
|
|
||||||
#define CFG_I2C_SLAVE 0xFE
|
|
||||||
|
|
||||||
|
|
||||||
#define __ADSPLPBLACKFIN__ 1
|
|
||||||
#define __ADSPBF533__ 1
|
|
||||||
|
|
||||||
/* 0xFF, 0x7BB07BB0, 0x22547BB0 */
|
|
||||||
/* #define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
|
|
||||||
#define AMBCTL0VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \
|
|
||||||
~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN)
|
|
||||||
#define AMBCTL1VAL (B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \
|
|
||||||
B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN)
|
|
||||||
*/
|
|
||||||
#define AMGCTLVAL 0xFF
|
|
||||||
#define AMBCTL0VAL 0x7BB07BB0
|
|
||||||
#define AMBCTL1VAL 0xFFC27BB0
|
|
||||||
|
|
||||||
#define CONFIG_VDSP 1
|
|
||||||
|
|
||||||
#ifdef CONFIG_VDSP
|
|
||||||
#define ET_EXEC_VDSP 0x8
|
|
||||||
#define SHT_STRTAB_VDSP 0x1
|
|
||||||
#define ELFSHDRSIZE_VDSP 0x2C
|
|
||||||
#define VDSP_ENTRY_ADDR 0xFFA00000
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
|
|
@ -1,333 +0,0 @@
|
||||||
/*
|
|
||||||
* U-boot - stamp.h Configuration file for STAMP board
|
|
||||||
* having BF533 processor
|
|
||||||
*
|
|
||||||
* Copyright (c) 2005 blackfin.uclinux.org
|
|
||||||
*
|
|
||||||
* (C) Copyright 2000-2004
|
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
*
|
|
||||||
* See file CREDITS for list of people who contributed to this
|
|
||||||
* project.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or
|
|
||||||
* modify it under the terms of the GNU General Public License as
|
|
||||||
* published by the Free Software Foundation; either version 2 of
|
|
||||||
* the License, or (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License
|
|
||||||
* along with this program; if not, write to the Free Software
|
|
||||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
||||||
* MA 02111-1307 USA
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __CONFIG_STAMP_H__
|
|
||||||
#define __CONFIG_STAMP_H__
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Board settings
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define __ADSPLPBLACKFIN__ 1
|
|
||||||
#define __ADSPBF533__ 1
|
|
||||||
#define CONFIG_STAMP 1
|
|
||||||
#define CONFIG_RTC_BF533 1
|
|
||||||
|
|
||||||
/* FLASH/ETHERNET uses the same address range */
|
|
||||||
#define SHARED_RESOURCES 1
|
|
||||||
|
|
||||||
#define CONFIG_VDSP 1
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Clock settings
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* CONFIG_CLKIN_HZ is any value in Hz */
|
|
||||||
#define CONFIG_CLKIN_HZ 11059200
|
|
||||||
/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
|
|
||||||
/* 1=CLKIN/2 */
|
|
||||||
#define CONFIG_CLKIN_HALF 0
|
|
||||||
/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
|
|
||||||
/* 1=bypass PLL */
|
|
||||||
#define CONFIG_PLL_BYPASS 0
|
|
||||||
/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */
|
|
||||||
/* Values can range from 1-64 */
|
|
||||||
#define CONFIG_VCO_MULT 45
|
|
||||||
/* CONFIG_CCLK_DIV controls what the core clock divider is */
|
|
||||||
/* Values can be 1, 2, 4, or 8 ONLY */
|
|
||||||
#define CONFIG_CCLK_DIV 1
|
|
||||||
/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
|
|
||||||
/* Values can range from 1-15 */
|
|
||||||
#define CONFIG_SCLK_DIV 6
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Network Settings
|
|
||||||
*/
|
|
||||||
/* network support */
|
|
||||||
#define CONFIG_IPADDR 192.168.0.15
|
|
||||||
#define CONFIG_NETMASK 255.255.255.0
|
|
||||||
#define CONFIG_GATEWAYIP 192.168.0.1
|
|
||||||
#define CONFIG_SERVERIP 192.168.0.2
|
|
||||||
#define CONFIG_HOSTNAME STAMP
|
|
||||||
#define CONFIG_ROOTPATH /checkout/uClinux-dist/romfs
|
|
||||||
|
|
||||||
/* To remove hardcoding and enable MAC storage in EEPROM */
|
|
||||||
/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Command settings
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define CFG_LONGHELP 1
|
|
||||||
|
|
||||||
#define CONFIG_BOOTDELAY 5
|
|
||||||
#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
|
|
||||||
#define CONFIG_BOOTCOMMAND "run ramboot"
|
|
||||||
#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
|
|
||||||
|
|
||||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
|
|
||||||
CFG_CMD_PING | \
|
|
||||||
CFG_CMD_ELF | \
|
|
||||||
CFG_CMD_I2C | \
|
|
||||||
CFG_CMD_CACHE | \
|
|
||||||
CFG_CMD_JFFS2 | \
|
|
||||||
CFG_CMD_DATE)
|
|
||||||
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw"
|
|
||||||
|
|
||||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
||||||
"ramargs=setenv bootargs root=/dev/mtdblock0 rw\0" \
|
|
||||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
|
||||||
"nfsroot=$(serverip):$(rootpath)\0" \
|
|
||||||
"addip=setenv bootargs $(bootargs) " \
|
|
||||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
|
|
||||||
":$(hostname):eth0:off\0" \
|
|
||||||
"ramboot=tftpboot 0x1000000 linux;" \
|
|
||||||
"run ramargs;run addip;bootelf\0" \
|
|
||||||
"nfsboot=tftpboot 0x1000000 linux;" \
|
|
||||||
"run nfsargs;run addip;bootelf\0" \
|
|
||||||
"flashboot=bootm 0x20100000\0" \
|
|
||||||
""
|
|
||||||
|
|
||||||
/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
|
||||||
#include <cmd_confdefs.h>
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Console settings
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define CONFIG_BAUDRATE 57600
|
|
||||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
|
||||||
|
|
||||||
#define CFG_PROMPT "stamp>" /* Monitor Command Prompt */
|
|
||||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
|
||||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
|
||||||
#else
|
|
||||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
|
||||||
#endif
|
|
||||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
|
||||||
#define CFG_MAXARGS 16 /* max number of command args */
|
|
||||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
|
||||||
|
|
||||||
#define CONFIG_LOADS_ECHO 1
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Network settings
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define CONFIG_DRIVER_SMC91111 1
|
|
||||||
#define CONFIG_SMC91111_BASE 0x20300300
|
|
||||||
/* To remove hardcoding and enable MAC storage in EEPROM */
|
|
||||||
/* #define HARDCODE_MAC 1 */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Flash settings
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define CFG_FLASH_CFI /* The flash is CFI compatible */
|
|
||||||
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
|
|
||||||
#define CFG_FLASH_CFI_AMD_RESET
|
|
||||||
|
|
||||||
#define CFG_ENV_IS_IN_FLASH 1
|
|
||||||
|
|
||||||
#define CFG_FLASH_BASE 0x20000000
|
|
||||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
|
||||||
#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
|
|
||||||
|
|
||||||
#define CFG_ENV_ADDR 0x20020000
|
|
||||||
#define CFG_ENV_SIZE 0x10000
|
|
||||||
#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */
|
|
||||||
|
|
||||||
#define CFG_FLASH_ERASE_TOUT 30000 /* Timeout for Chip Erase (in ms) */
|
|
||||||
#define CFG_FLASH_ERASEBLOCK_TOUT 5000 /* Timeout for Block Erase (in ms) */
|
|
||||||
#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
|
|
||||||
|
|
||||||
/* JFFS Partition offset set */
|
|
||||||
#define CFG_JFFS2_FIRST_BANK 0
|
|
||||||
#define CFG_JFFS2_NUM_BANKS 1
|
|
||||||
/* 512k reserved for u-boot */
|
|
||||||
#define CFG_JFFS2_FIRST_SECTOR 11
|
|
||||||
|
|
||||||
/*
|
|
||||||
* following timeouts shall be used once the
|
|
||||||
* Flash real protection is enabled
|
|
||||||
*/
|
|
||||||
#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
|
|
||||||
#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* I2C settings
|
|
||||||
* By default PF2 is used as SDA and PF3 as SCL on the Stamp board
|
|
||||||
*/
|
|
||||||
#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
|
|
||||||
/*
|
|
||||||
* Software (bit-bang) I2C driver configuration
|
|
||||||
*/
|
|
||||||
#define PF_SCL PF3
|
|
||||||
#define PF_SDA PF2
|
|
||||||
|
|
||||||
#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;")
|
|
||||||
#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
|
|
||||||
#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
|
|
||||||
#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
|
|
||||||
#define I2C_SDA(bit) if(bit) { \
|
|
||||||
*pFIO_FLAG_S = PF_SDA; \
|
|
||||||
asm("ssync;"); \
|
|
||||||
} \
|
|
||||||
else { \
|
|
||||||
*pFIO_FLAG_C = PF_SDA; \
|
|
||||||
asm("ssync;"); \
|
|
||||||
}
|
|
||||||
#define I2C_SCL(bit) if(bit) { \
|
|
||||||
*pFIO_FLAG_S = PF_SCL; \
|
|
||||||
asm("ssync;"); \
|
|
||||||
} \
|
|
||||||
else { \
|
|
||||||
*pFIO_FLAG_C = PF_SCL; \
|
|
||||||
asm("ssync;"); \
|
|
||||||
}
|
|
||||||
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
|
|
||||||
|
|
||||||
#define CFG_I2C_SPEED 50000
|
|
||||||
#define CFG_I2C_SLAVE 0xFE
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Compact Flash settings
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Enabled below option for CF support */
|
|
||||||
/* #define CONFIG_STAMP_CF 1 */
|
|
||||||
|
|
||||||
#if defined(CONFIG_STAMP_CF) && (CONFIG_COMMANDS & CFG_CMD_IDE)
|
|
||||||
|
|
||||||
#define CONFIG_MISC_INIT_R 1
|
|
||||||
#define CONFIG_DOS_PARTITION 1
|
|
||||||
|
|
||||||
/*
|
|
||||||
* IDE/ATA stuff
|
|
||||||
*/
|
|
||||||
#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
|
|
||||||
#undef CONFIG_IDE_LED /* no led for ide supported */
|
|
||||||
#undef CONFIG_IDE_RESET /* no reset for ide supported */
|
|
||||||
|
|
||||||
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
|
|
||||||
#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
|
|
||||||
|
|
||||||
#define CFG_ATA_BASE_ADDR 0x20200000
|
|
||||||
#define CFG_ATA_IDE0_OFFSET 0x0000
|
|
||||||
|
|
||||||
#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
|
|
||||||
#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
|
|
||||||
#define CFG_ATA_ALT_OFFSET 0x0007 /* Offset for alternate registers */
|
|
||||||
|
|
||||||
#define CFG_ATA_STRIDE 2
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*
|
|
||||||
* SDRAM settings
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define CONFIG_MEM_SIZE 128 /* 128, 64, 32, 16 */
|
|
||||||
#define CONFIG_MEM_ADD_WDTH 11 /* 8, 9, 10, 11 */
|
|
||||||
#define CONFIG_MEM_MT48LC64M4A2FB_7E 1
|
|
||||||
|
|
||||||
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
|
|
||||||
#define CFG_MEMTEST_END 0x07EFFFFF /* 1 ... 127 MB in DRAM */
|
|
||||||
#define CFG_LOAD_ADDR 0x01000000 /* default load address */
|
|
||||||
|
|
||||||
#define CFG_SDRAM_BASE 0x00000000
|
|
||||||
#define CFG_MAX_RAM_SIZE 0x08000000
|
|
||||||
|
|
||||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
|
||||||
#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
|
|
||||||
|
|
||||||
#if ( CONFIG_CLKIN_HALF == 0 )
|
|
||||||
#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
|
|
||||||
#else
|
|
||||||
#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if (CONFIG_PLL_BYPASS == 0)
|
|
||||||
#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
|
|
||||||
#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
|
|
||||||
#else
|
|
||||||
#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
|
|
||||||
#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Miscellaneous configurable options
|
|
||||||
*/
|
|
||||||
#define CFG_HZ 1000 /* 1ms time tick */
|
|
||||||
|
|
||||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
|
||||||
#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
|
|
||||||
#define CFG_GBL_DATA_SIZE 0x4000
|
|
||||||
#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
|
|
||||||
#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4)
|
|
||||||
|
|
||||||
#define CFG_LARGE_IMAGE_LEN 0x4000000 /* Large Image Length, set to 64 Meg */
|
|
||||||
|
|
||||||
#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Stack sizes
|
|
||||||
*/
|
|
||||||
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* FLASH organization and environment definitions
|
|
||||||
*/
|
|
||||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
|
||||||
|
|
||||||
/* 0xFF, 0xBBC3BBc3, 0x99B39983 */
|
|
||||||
/*#define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
|
|
||||||
#define AMBCTL0VAL (B1WAT_11 | B1RAT_11 | B1HT_3 | B1ST_4 | B1TT_4 | B1RDYPOL | \
|
|
||||||
B1RDYEN | B0WAT_11 | B0RAT_11 | B0HT_3 | B0ST_4 | B0TT_4 | B0RDYPOL | B0RDYEN)
|
|
||||||
#define AMBCTL1VAL (B3WAT_9 | B3RAT_9 | B3HT_2 | B3ST_3 | B3TT_4 | B3RDYPOL | \
|
|
||||||
B3RDYEN | B2WAT_9 | B2RAT_9 | B2HT_2 | B2ST_4 | B2TT_4 | B2RDYPOL | B2RDYEN)
|
|
||||||
*/
|
|
||||||
#define AMGCTLVAL 0xFF
|
|
||||||
#define AMBCTL0VAL 0xBBC3BBC3
|
|
||||||
#define AMBCTL1VAL 0x99B39983
|
|
||||||
#define CF_AMBCTL1VAL 0x99B3ffc2
|
|
||||||
|
|
||||||
#ifdef CONFIG_VDSP
|
|
||||||
#define ET_EXEC_VDSP 0x8
|
|
||||||
#define SHT_STRTAB_VDSP 0x1
|
|
||||||
#define ELFSHDRSIZE_VDSP 0x2C
|
|
||||||
#define VDSP_ENTRY_ADDR 0xFFA00000
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif
|
|
|
@ -3,7 +3,7 @@
|
||||||
#
|
#
|
||||||
# Copyright (c) 2005 blackfin.uclinux.org
|
# Copyright (c) 2005 blackfin.uclinux.org
|
||||||
#
|
#
|
||||||
# (C) Copyright 2000-2006
|
# (C) Copyright 2000-2004
|
||||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
#
|
#
|
||||||
# See file CREDITS for list of people who contributed to this
|
# See file CREDITS for list of people who contributed to this
|
||||||
|
@ -27,23 +27,21 @@
|
||||||
|
|
||||||
include $(TOPDIR)/config.mk
|
include $(TOPDIR)/config.mk
|
||||||
|
|
||||||
LIB = $(obj)lib$(ARCH).a
|
LIB = lib$(ARCH).a
|
||||||
|
|
||||||
SOBJS =
|
AOBJS = memcpy.o memcmp.o memset.o memmove.o
|
||||||
|
|
||||||
COBJS = board.o bf533_linux.o bf533_string.o cache.o muldi3.o
|
COBJS = post.o tests.o board.o bf533_linux.o bf533_string.o cache.o muldi3.o
|
||||||
|
OBJS = $(AOBJS) $(COBJS)
|
||||||
|
|
||||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
$(LIB): .depend $(OBJS)
|
||||||
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
|
$(AR) cr $@ $(OBJS)
|
||||||
|
|
||||||
$(LIB): $(obj).depend $(OBJS)
|
|
||||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
|
||||||
|
|
||||||
#########################################################################
|
#########################################################################
|
||||||
|
|
||||||
# defines $(obj).depend target
|
.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c)
|
||||||
include $(SRCTREE)/rules.mk
|
$(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@
|
||||||
|
|
||||||
sinclude $(obj).depend
|
sinclude .depend
|
||||||
|
|
||||||
#########################################################################
|
#########################################################################
|
||||||
|
|
|
@ -49,10 +49,11 @@
|
||||||
extern void swap_to(int device_id);
|
extern void swap_to(int device_id);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
extern image_header_t header;
|
||||||
|
extern void flush_instruction_cache(void);
|
||||||
|
extern void flush_data_cache(void);
|
||||||
static char *make_command_line(void);
|
static char *make_command_line(void);
|
||||||
|
|
||||||
extern image_header_t header;
|
|
||||||
extern int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]);
|
|
||||||
void do_bootm_linux(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[],
|
void do_bootm_linux(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[],
|
||||||
ulong addr, ulong * len_ptr, int verify)
|
ulong addr, ulong * len_ptr, int verify)
|
||||||
{
|
{
|
||||||
|
|
|
@ -28,7 +28,12 @@
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <asm/setup.h>
|
#include <asm/setup.h>
|
||||||
#include <asm/page.h>
|
#include <asm/page.h>
|
||||||
#include <asm/cpu/defBF533.h>
|
#include <config.h>
|
||||||
|
#include <asm/blackfin.h>
|
||||||
|
|
||||||
|
extern void blackfin_icache_flush_range(const void *, const void *);
|
||||||
|
extern void blackfin_dcache_flush_range(const void *, const void *);
|
||||||
|
extern void *memcpy_ASM(void *dest, const void *src, size_t count);
|
||||||
|
|
||||||
void *dma_memcpy(void *, const void *, size_t);
|
void *dma_memcpy(void *, const void *, size_t);
|
||||||
|
|
||||||
|
@ -74,8 +79,7 @@ int strcmp(const char *cs, const char *ct)
|
||||||
{
|
{
|
||||||
char __res1, __res2;
|
char __res1, __res2;
|
||||||
|
|
||||||
__asm__
|
__asm__("1:\t%2 = B[%0++] (Z);\n\t" /* get *cs */
|
||||||
("1:\t%2 = B[%0++] (Z);\n\t" /* get *cs */
|
|
||||||
"%3 = B[%1++] (Z);\n\t" /* get *ct */
|
"%3 = B[%1++] (Z);\n\t" /* get *ct */
|
||||||
"CC = %2 == %3;\n\t" /* compare a byte */
|
"CC = %2 == %3;\n\t" /* compare a byte */
|
||||||
"if ! cc jump 2f;\n\t" /* not equal, break out */
|
"if ! cc jump 2f;\n\t" /* not equal, break out */
|
||||||
|
@ -83,8 +87,7 @@ int strcmp(const char *cs, const char *ct)
|
||||||
"if cc jump 1b (bp);\n\t" /* no, keep going */
|
"if cc jump 1b (bp);\n\t" /* no, keep going */
|
||||||
"jump.s 3f;\n" /* strings are equal */
|
"jump.s 3f;\n" /* strings are equal */
|
||||||
"2:\t%2 = %2 - %3;\n" /* *cs - *ct */
|
"2:\t%2 = %2 - %3;\n" /* *cs - *ct */
|
||||||
"3:\n": "=a"(cs), "=a"(ct), "=d"(__res1),
|
"3:\n": "=a"(cs), "=a"(ct), "=d"(__res1), "=d"(__res2)
|
||||||
"=d"(__res2)
|
|
||||||
: "0"(cs), "1"(ct));
|
: "0"(cs), "1"(ct));
|
||||||
|
|
||||||
return __res1;
|
return __res1;
|
||||||
|
@ -97,8 +100,7 @@ int strncmp(const char *cs, const char *ct, size_t count)
|
||||||
if (!count)
|
if (!count)
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
__asm__
|
__asm__("1:\t%3 = B[%0++] (Z);\n\t" /* get *cs */
|
||||||
("1:\t%3 = B[%0++] (Z);\n\t" /* get *cs */
|
|
||||||
"%4 = B[%1++] (Z);\n\t" /* get *ct */
|
"%4 = B[%1++] (Z);\n\t" /* get *ct */
|
||||||
"CC = %3 == %4;\n\t" /* compare a byte */
|
"CC = %3 == %4;\n\t" /* compare a byte */
|
||||||
"if ! cc jump 3f;\n\t" /* not equal, break out */
|
"if ! cc jump 3f;\n\t" /* not equal, break out */
|
||||||
|
@ -128,29 +130,32 @@ void * memcpy(void * dest,const void *src,size_t count)
|
||||||
{
|
{
|
||||||
char *tmp = (char *)dest, *s = (char *)src;
|
char *tmp = (char *)dest, *s = (char *)src;
|
||||||
|
|
||||||
/* Turn off the cache, if destination in the L1 memory */
|
/* L1_ISRAM can only be accessed via dma */
|
||||||
if ( (tmp >= (char *)L1_ISRAM) && (tmp < (char *)L1_ISRAM_END)
|
if ((tmp >= (char *)L1_ISRAM) && (tmp < (char *)L1_ISRAM_END)) {
|
||||||
|| (tmp >= (char *)DATA_BANKA_SRAM) && (tmp < DATA_BANKA_SRAM_END)
|
/* L1 is the destination */
|
||||||
|| (tmp >= (char *)DATA_BANKB_SRAM) && (tmp < DATA_BANKB_SRAM_END) ){
|
dma_memcpy(dest, src, count);
|
||||||
|
|
||||||
if (icache_status()) {
|
if (icache_status()) {
|
||||||
blackfin_icache_flush_range(src, src + count);
|
blackfin_icache_flush_range(src, src + count);
|
||||||
icache_disable();
|
}
|
||||||
|
} else if ((s >= (char *)L1_ISRAM) && (s < (char *)L1_ISRAM_END)) {
|
||||||
|
/* L1 is the source */
|
||||||
|
dma_memcpy(dest, src, count);
|
||||||
|
|
||||||
|
if (icache_status()) {
|
||||||
|
blackfin_icache_flush_range(dest, dest + count);
|
||||||
}
|
}
|
||||||
if (dcache_status()) {
|
if (dcache_status()) {
|
||||||
blackfin_dcache_flush_range(src, src+count);
|
blackfin_dcache_flush_range(dest, dest + count);
|
||||||
dcache_disable();
|
|
||||||
}
|
}
|
||||||
dma_memcpy(dest,src,count);
|
|
||||||
} else {
|
} else {
|
||||||
while(count--)
|
memcpy_ASM(dest, src, count);
|
||||||
*tmp++ = *s++;
|
|
||||||
}
|
}
|
||||||
return dest;
|
return dest;
|
||||||
}
|
}
|
||||||
|
|
||||||
void *dma_memcpy(void *dest, const void *src, size_t count)
|
void *dma_memcpy(void *dest, const void *src, size_t count)
|
||||||
{
|
{
|
||||||
|
|
||||||
*pMDMA_D0_IRQ_STATUS = DMA_DONE | DMA_ERR;
|
*pMDMA_D0_IRQ_STATUS = DMA_DONE | DMA_ERR;
|
||||||
|
|
||||||
/* Copy sram functions from sdram to sram */
|
/* Copy sram functions from sdram to sram */
|
||||||
|
@ -170,7 +175,7 @@ void *dma_memcpy(void * dest,const void *src,size_t count)
|
||||||
|
|
||||||
/* Enable source DMA */
|
/* Enable source DMA */
|
||||||
*pMDMA_S0_CONFIG = (DMAEN);
|
*pMDMA_S0_CONFIG = (DMAEN);
|
||||||
asm("ssync;");
|
__builtin_bfin_ssync();
|
||||||
|
|
||||||
*pMDMA_D0_CONFIG = (WNR | DMAEN);
|
*pMDMA_D0_CONFIG = (WNR | DMAEN);
|
||||||
|
|
||||||
|
|
|
@ -28,6 +28,8 @@
|
||||||
#ifndef __BLACKFIN_BOARD_H__
|
#ifndef __BLACKFIN_BOARD_H__
|
||||||
#define __BLACKFIN_BOARD_H__
|
#define __BLACKFIN_BOARD_H__
|
||||||
|
|
||||||
|
#include <version.h>
|
||||||
|
|
||||||
extern void timer_init(void);
|
extern void timer_init(void);
|
||||||
extern void init_IRQ(void);
|
extern void init_IRQ(void);
|
||||||
extern void rtc_init(void);
|
extern void rtc_init(void);
|
||||||
|
|
|
@ -32,21 +32,79 @@
|
||||||
#include <version.h>
|
#include <version.h>
|
||||||
#include <net.h>
|
#include <net.h>
|
||||||
#include <environment.h>
|
#include <environment.h>
|
||||||
|
#include <i2c.h>
|
||||||
#include "blackfin_board.h"
|
#include "blackfin_board.h"
|
||||||
|
#include <asm/cplb.h>
|
||||||
#include "../drivers/smc91111.h"
|
#include "../drivers/smc91111.h"
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
#if defined(CONFIG_BF537)&&defined(CONFIG_POST)
|
||||||
|
#include <post.h>
|
||||||
|
int post_flag;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef DEBUG
|
||||||
|
#define pr_debug(fmt,arg...) printf(fmt,##arg)
|
||||||
|
#else
|
||||||
|
static inline int
|
||||||
|
__attribute__ ((format(printf, 1, 2))) pr_debug(const char *fmt, ...)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef CFG_NO_FLASH
|
||||||
extern flash_info_t flash_info[];
|
extern flash_info_t flash_info[];
|
||||||
|
#endif
|
||||||
|
|
||||||
|
static inline u_long get_vco(void)
|
||||||
|
{
|
||||||
|
u_long msel;
|
||||||
|
u_long vco;
|
||||||
|
|
||||||
|
msel = (*pPLL_CTL >> 9) & 0x3F;
|
||||||
|
if (0 == msel)
|
||||||
|
msel = 64;
|
||||||
|
|
||||||
|
vco = CONFIG_CLKIN_HZ;
|
||||||
|
vco >>= (1 & *pPLL_CTL); /* DF bit */
|
||||||
|
vco = msel * vco;
|
||||||
|
return vco;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*Get the Core clock*/
|
||||||
|
u_long get_cclk(void)
|
||||||
|
{
|
||||||
|
u_long csel, ssel;
|
||||||
|
if (*pPLL_STAT & 0x1)
|
||||||
|
return CONFIG_CLKIN_HZ;
|
||||||
|
|
||||||
|
ssel = *pPLL_DIV;
|
||||||
|
csel = ((ssel >> 4) & 0x03);
|
||||||
|
ssel &= 0xf;
|
||||||
|
if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */
|
||||||
|
return get_vco() / ssel;
|
||||||
|
return get_vco() >> csel;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Get the System clock */
|
||||||
|
u_long get_sclk(void)
|
||||||
|
{
|
||||||
|
u_long ssel;
|
||||||
|
|
||||||
|
if (*pPLL_STAT & 0x1)
|
||||||
|
return CONFIG_CLKIN_HZ;
|
||||||
|
|
||||||
|
ssel = (*pPLL_DIV & 0xf);
|
||||||
|
|
||||||
|
return get_vco() / ssel;
|
||||||
|
}
|
||||||
|
|
||||||
static void mem_malloc_init(void)
|
static void mem_malloc_init(void)
|
||||||
{
|
{
|
||||||
mem_malloc_start = CFG_MALLOC_BASE;
|
mem_malloc_start = CFG_MALLOC_BASE;
|
||||||
mem_malloc_end = (CFG_MALLOC_BASE + CFG_MALLOC_LEN);
|
mem_malloc_end = (CFG_MALLOC_BASE + CFG_MALLOC_LEN);
|
||||||
mem_malloc_brk = mem_malloc_start;
|
mem_malloc_brk = mem_malloc_start;
|
||||||
memset((void *) mem_malloc_start, 0,
|
memset((void *)mem_malloc_start, 0, mem_malloc_end - mem_malloc_start);
|
||||||
mem_malloc_end - mem_malloc_start);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void *sbrk(ptrdiff_t increment)
|
void *sbrk(ptrdiff_t increment)
|
||||||
|
@ -78,7 +136,9 @@ static void display_flash_config(ulong size)
|
||||||
|
|
||||||
static int init_baudrate(void)
|
static int init_baudrate(void)
|
||||||
{
|
{
|
||||||
uchar tmp[64];
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
|
char tmp[64];
|
||||||
int i = getenv_r("baudrate", tmp, sizeof(tmp));
|
int i = getenv_r("baudrate", tmp, sizeof(tmp));
|
||||||
gd->bd->bi_baudrate = gd->baudrate = (i > 0)
|
gd->bd->bi_baudrate = gd->baudrate = (i > 0)
|
||||||
? (int)simple_strtoul(tmp, NULL, 10)
|
? (int)simple_strtoul(tmp, NULL, 10)
|
||||||
|
@ -89,6 +149,7 @@ static int init_baudrate(void)
|
||||||
#ifdef DEBUG
|
#ifdef DEBUG
|
||||||
static void display_global_data(void)
|
static void display_global_data(void)
|
||||||
{
|
{
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
bd_t *bd;
|
bd_t *bd;
|
||||||
bd = gd->bd;
|
bd = gd->bd;
|
||||||
printf("--flags:%x\n", gd->flags);
|
printf("--flags:%x\n", gd->flags);
|
||||||
|
@ -106,9 +167,7 @@ static void display_global_data(void)
|
||||||
bd->bi_enetaddr[0],
|
bd->bi_enetaddr[0],
|
||||||
bd->bi_enetaddr[1],
|
bd->bi_enetaddr[1],
|
||||||
bd->bi_enetaddr[2],
|
bd->bi_enetaddr[2],
|
||||||
bd->bi_enetaddr[3],
|
bd->bi_enetaddr[3], bd->bi_enetaddr[4], bd->bi_enetaddr[5]);
|
||||||
bd->bi_enetaddr[4],
|
|
||||||
bd->bi_enetaddr[5]);
|
|
||||||
printf("---bi_arch_number:%x\n", bd->bi_arch_number);
|
printf("---bi_arch_number:%x\n", bd->bi_arch_number);
|
||||||
printf("---bi_boot_params:%x\n", bd->bi_boot_params);
|
printf("---bi_boot_params:%x\n", bd->bi_boot_params);
|
||||||
printf("---bi_memstart:%x\n", bd->bi_memstart);
|
printf("---bi_memstart:%x\n", bd->bi_memstart);
|
||||||
|
@ -120,6 +179,71 @@ static void display_global_data(void)
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
/* we cover everything with 4 meg pages, and need an extra for L1 */
|
||||||
|
unsigned int icplb_table[page_descriptor_table_size][2];
|
||||||
|
unsigned int dcplb_table[page_descriptor_table_size][2];
|
||||||
|
|
||||||
|
void init_cplbtables(void)
|
||||||
|
{
|
||||||
|
int i, j;
|
||||||
|
|
||||||
|
j = 0;
|
||||||
|
icplb_table[j][0] = 0xFFA00000;
|
||||||
|
icplb_table[j][1] = L1_IMEMORY;
|
||||||
|
j++;
|
||||||
|
|
||||||
|
for (i = 0; i <= CONFIG_MEM_SIZE / 4; i++) {
|
||||||
|
icplb_table[j][0] = (i * 4 * 1024 * 1024);
|
||||||
|
if (i * 4 * 1024 * 1024 <= CFG_MONITOR_BASE
|
||||||
|
&& (i + 1) * 4 * 1024 * 1024 >= CFG_MONITOR_BASE) {
|
||||||
|
icplb_table[j][1] = SDRAM_IKERNEL;
|
||||||
|
} else {
|
||||||
|
icplb_table[j][1] = SDRAM_IGENERIC;
|
||||||
|
}
|
||||||
|
j++;
|
||||||
|
}
|
||||||
|
#if defined(CONFIG_BF561)
|
||||||
|
/* Async Memory space */
|
||||||
|
for (i = 0; i < 3; i++) {
|
||||||
|
icplb_table[j++][0] = 0x20000000 + i * 4 * 1024 * 1024;
|
||||||
|
icplb_table[j++][1] = SDRAM_IGENERIC;
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
icplb_table[j][0] = 0x20000000;
|
||||||
|
icplb_table[j][1] = SDRAM_IGENERIC;
|
||||||
|
#endif
|
||||||
|
j = 0;
|
||||||
|
dcplb_table[j][0] = 0xFF800000;
|
||||||
|
dcplb_table[j][1] = L1_DMEMORY;
|
||||||
|
j++;
|
||||||
|
|
||||||
|
for (i = 0; i < CONFIG_MEM_SIZE / 4; i++) {
|
||||||
|
dcplb_table[j][0] = (i * 4 * 1024 * 1024);
|
||||||
|
if (i * 4 * 1024 * 1024 <= CFG_MONITOR_BASE
|
||||||
|
&& (i + 1) * 4 * 1024 * 1024 >= CFG_MONITOR_BASE) {
|
||||||
|
dcplb_table[j][1] = SDRAM_DKERNEL;
|
||||||
|
} else {
|
||||||
|
dcplb_table[j][1] = SDRAM_DGENERIC;
|
||||||
|
}
|
||||||
|
j++;
|
||||||
|
}
|
||||||
|
|
||||||
|
#if defined(CONFIG_BF561)
|
||||||
|
/* MAC space */
|
||||||
|
dcplb_table[j++][0] = CONFIG_ASYNC_EBIU_BASE;
|
||||||
|
dcplb_table[j++][1] = SDRAM_EBIU;
|
||||||
|
|
||||||
|
/* Flash space */
|
||||||
|
for (i = 0; i < 2; i++) {
|
||||||
|
dcplb_table[j++][0] = 0x20000000 + i * 4 * 1024 * 1024;
|
||||||
|
dcplb_table[j++][1] = SDRAM_EBIU;
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
dcplb_table[j][0] = 0x20000000;
|
||||||
|
dcplb_table[j][1] = SDRAM_EBIU;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* All attempts to come up with a "common" initialization sequence
|
* All attempts to come up with a "common" initialization sequence
|
||||||
* that works for all boards and architectures failed: some of the
|
* that works for all boards and architectures failed: some of the
|
||||||
|
@ -135,8 +259,12 @@ static void display_global_data(void)
|
||||||
|
|
||||||
void board_init_f(ulong bootflag)
|
void board_init_f(ulong bootflag)
|
||||||
{
|
{
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
ulong addr;
|
ulong addr;
|
||||||
bd_t *bd;
|
bd_t *bd;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
init_cplbtables();
|
||||||
|
|
||||||
gd = (gd_t *) (CFG_GBL_DATA_ADDR);
|
gd = (gd_t *) (CFG_GBL_DATA_ADDR);
|
||||||
memset((void *)gd, 0, sizeof(gd_t));
|
memset((void *)gd, 0, sizeof(gd_t));
|
||||||
|
@ -156,21 +284,51 @@ void board_init_f(ulong bootflag)
|
||||||
init_baudrate(); /* initialze baudrate settings */
|
init_baudrate(); /* initialze baudrate settings */
|
||||||
serial_init(); /* serial communications setup */
|
serial_init(); /* serial communications setup */
|
||||||
console_init_f();
|
console_init_f();
|
||||||
|
#ifdef CONFIG_ICACHE_ON
|
||||||
|
icache_enable();
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_DCACHE_ON
|
||||||
|
dcache_enable();
|
||||||
|
#endif
|
||||||
display_banner(); /* say that we are here */
|
display_banner(); /* say that we are here */
|
||||||
|
|
||||||
|
for (i = 0; i < page_descriptor_table_size; i++) {
|
||||||
|
pr_debug
|
||||||
|
("data (%02i)= 0x%08x : 0x%08x intr = 0x%08x : 0x%08x\n",
|
||||||
|
i, dcplb_table[i][0], dcplb_table[i][1], icplb_table[i][0],
|
||||||
|
icplb_table[i][1]);
|
||||||
|
}
|
||||||
|
|
||||||
checkboard();
|
checkboard();
|
||||||
#if defined(CONFIG_RTC_BF533) && (CONFIG_COMMANDS & CFG_CMD_DATE)
|
#if defined(CONFIG_RTC_BF533) && (CONFIG_COMMANDS & CFG_CMD_DATE)
|
||||||
rtc_init();
|
rtc_init();
|
||||||
#endif
|
#endif
|
||||||
timer_init();
|
timer_init();
|
||||||
printf("Clock: VCO: %lu MHz, Core: %lu MHz, System: %lu MHz\n", \
|
printf("Clock: VCO: %lu MHz, Core: %lu MHz, System: %lu MHz\n",
|
||||||
CONFIG_VCO_HZ/1000000, CONFIG_CCLK_HZ/1000000, CONFIG_SCLK_HZ/1000000);
|
get_vco() / 1000000, get_cclk() / 1000000, get_sclk() / 1000000);
|
||||||
printf("SDRAM: ");
|
printf("SDRAM: ");
|
||||||
print_size(initdram(0), "\n");
|
print_size(initdram(0), "\n");
|
||||||
|
#if defined(CONFIG_BF537)&&defined(CONFIG_POST)
|
||||||
|
post_init_f();
|
||||||
|
post_bootmode_init();
|
||||||
|
post_run(NULL, POST_ROM | post_bootmode_get(0));
|
||||||
|
#endif
|
||||||
board_init_r((gd_t *) gd, 0x20000010);
|
board_init_r((gd_t *) gd, 0x20000010);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#if defined(CONFIG_SOFT_I2C) || defined(CONFIG_HARD_I2C)
|
||||||
|
static int init_func_i2c(void)
|
||||||
|
{
|
||||||
|
puts("I2C: ");
|
||||||
|
i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
|
||||||
|
puts("ready\n");
|
||||||
|
return (0);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
void board_init_r(gd_t * id, ulong dest_addr)
|
void board_init_r(gd_t * id, ulong dest_addr)
|
||||||
{
|
{
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
ulong size;
|
ulong size;
|
||||||
extern void malloc_bin_reloc(void);
|
extern void malloc_bin_reloc(void);
|
||||||
char *s, *e;
|
char *s, *e;
|
||||||
|
@ -180,12 +338,18 @@ void board_init_r(gd_t * id, ulong dest_addr)
|
||||||
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
|
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
|
||||||
bd = gd->bd;
|
bd = gd->bd;
|
||||||
|
|
||||||
#if CONFIG_STAMP
|
#if defined(CONFIG_BF537) && defined(CONFIG_POST)
|
||||||
|
post_output_backlog();
|
||||||
|
post_reloc();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CONFIG_STAMP || CONFIG_BF537 || CONFIG_EZKIT561) && !defined(CFG_NO_FLASH)
|
||||||
/* There are some other pointer constants we must deal with */
|
/* There are some other pointer constants we must deal with */
|
||||||
/* configure available FLASH banks */
|
/* configure available FLASH banks */
|
||||||
size = flash_init();
|
size = flash_init();
|
||||||
display_flash_config(size);
|
display_flash_config(size);
|
||||||
flash_protect(FLAG_PROTECT_SET, CFG_FLASH_BASE, CFG_FLASH_BASE + 0x1ffff, &flash_info[0]);
|
flash_protect(FLAG_PROTECT_SET, CFG_FLASH_BASE,
|
||||||
|
CFG_FLASH_BASE + 0x1ffff, &flash_info[0]);
|
||||||
bd->bi_flashstart = CFG_FLASH_BASE;
|
bd->bi_flashstart = CFG_FLASH_BASE;
|
||||||
bd->bi_flashsize = size;
|
bd->bi_flashsize = size;
|
||||||
bd->bi_flashoffset = 0;
|
bd->bi_flashoffset = 0;
|
||||||
|
@ -198,6 +362,13 @@ void board_init_r(gd_t * id, ulong dest_addr)
|
||||||
mem_malloc_init();
|
mem_malloc_init();
|
||||||
malloc_bin_reloc();
|
malloc_bin_reloc();
|
||||||
|
|
||||||
|
#ifdef CONFIG_SPI
|
||||||
|
# if ! defined(CFG_ENV_IS_IN_EEPROM)
|
||||||
|
spi_init_f();
|
||||||
|
# endif
|
||||||
|
spi_init_r();
|
||||||
|
#endif
|
||||||
|
|
||||||
/* relocate environment function pointers etc. */
|
/* relocate environment function pointers etc. */
|
||||||
env_relocate();
|
env_relocate();
|
||||||
|
|
||||||
|
@ -228,18 +399,30 @@ void board_init_r(gd_t * id, ulong dest_addr)
|
||||||
copy_filename(BootFile, s, sizeof(BootFile));
|
copy_filename(BootFile, s, sizeof(BootFile));
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
|
||||||
|
puts("NAND: ");
|
||||||
|
nand_init(); /* go init the NAND */
|
||||||
|
#endif
|
||||||
|
|
||||||
#if defined(CONFIG_MISC_INIT_R)
|
#if defined(CONFIG_MISC_INIT_R)
|
||||||
/* miscellaneous platform dependent initialisations */
|
/* miscellaneous platform dependent initialisations */
|
||||||
misc_init_r();
|
misc_init_r();
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if ((BFIN_CPU == ADSP_BF537) || (BFIN_CPU == ADSP_BF536))
|
||||||
|
printf("Net: ");
|
||||||
|
eth_initialize(bd);
|
||||||
|
#endif
|
||||||
|
|
||||||
#ifdef CONFIG_DRIVER_SMC91111
|
#ifdef CONFIG_DRIVER_SMC91111
|
||||||
#ifdef SHARED_RESOURCES
|
#ifdef SHARED_RESOURCES
|
||||||
/* Switch to Ethernet */
|
/* Switch to Ethernet */
|
||||||
swap_to(ETHERNET);
|
swap_to(ETHERNET);
|
||||||
#endif
|
#endif
|
||||||
if ((SMC_inw(BANK_SELECT) & UPPER_BYTE_MASK) != SMC_IDENT) {
|
if ((SMC_inw(BANK_SELECT) & UPPER_BYTE_MASK) != SMC_IDENT) {
|
||||||
printf("ERROR: Can't find SMC91111 at address %x\n", SMC_BASE_ADDRESS);
|
printf("ERROR: Can't find SMC91111 at address %x\n",
|
||||||
|
SMC_BASE_ADDRESS);
|
||||||
} else {
|
} else {
|
||||||
printf("Net: SMC91111 at 0x%08X\n", SMC_BASE_ADDRESS);
|
printf("Net: SMC91111 at 0x%08X\n", SMC_BASE_ADDRESS);
|
||||||
}
|
}
|
||||||
|
@ -248,12 +431,17 @@ void board_init_r(gd_t * id, ulong dest_addr)
|
||||||
swap_to(FLASH);
|
swap_to(FLASH);
|
||||||
#endif
|
#endif
|
||||||
#endif
|
#endif
|
||||||
#ifdef CONFIG_SOFT_I2C
|
#if defined(CONFIG_SOFT_I2C) || defined(CONFIG_HARD_I2C)
|
||||||
init_func_i2c();
|
init_func_i2c();
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef DEBUG
|
#ifdef DEBUG
|
||||||
display_global_data(void);
|
display_global_data();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_BF537) && defined(CONFIG_POST)
|
||||||
|
if (post_flag)
|
||||||
|
post_run(NULL, POST_RAM | post_bootmode_get(0));
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* main_loop() can return to retry autoboot, if so just run it again. */
|
/* main_loop() can return to retry autoboot, if so just run it again. */
|
||||||
|
@ -262,16 +450,6 @@ void board_init_r(gd_t * id, ulong dest_addr)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
#ifdef CONFIG_SOFT_I2C
|
|
||||||
static int init_func_i2c (void)
|
|
||||||
{
|
|
||||||
puts ("I2C: ");
|
|
||||||
i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
|
|
||||||
puts ("ready\n");
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void hang(void)
|
void hang(void)
|
||||||
{
|
{
|
||||||
puts("### ERROR ### Please RESET the board ###\n");
|
puts("### ERROR ### Please RESET the board ###\n");
|
||||||
|
|
|
@ -26,15 +26,26 @@
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* for now: just dummy functions to satisfy the linker */
|
/* for now: just dummy functions to satisfy the linker */
|
||||||
extern void blackfin_icache_range (unsigned long *, unsigned long *);
|
#include <config.h>
|
||||||
extern void blackfin_dcache_range (unsigned long *, unsigned long *);
|
#include <common.h>
|
||||||
|
#include <asm/blackfin.h>
|
||||||
|
|
||||||
|
extern void blackfin_icache_flush_range(unsigned long, unsigned long);
|
||||||
|
extern void blackfin_dcache_flush_range(unsigned long, unsigned long);
|
||||||
|
|
||||||
void flush_cache(unsigned long dummy1, unsigned long dummy2)
|
void flush_cache(unsigned long dummy1, unsigned long dummy2)
|
||||||
{
|
{
|
||||||
if (icache_status ()) {
|
if ((dummy1 >= L1_ISRAM) && (dummy1 < L1_ISRAM_END))
|
||||||
|
return;
|
||||||
|
if ((dummy1 >= DATA_BANKA_SRAM) && (dummy1 < DATA_BANKA_SRAM_END))
|
||||||
|
return;
|
||||||
|
if ((dummy1 >= DATA_BANKB_SRAM) && (dummy1 < DATA_BANKB_SRAM_END))
|
||||||
|
return;
|
||||||
|
|
||||||
|
if (icache_status())
|
||||||
blackfin_icache_flush_range(dummy1, dummy1 + dummy2);
|
blackfin_icache_flush_range(dummy1, dummy1 + dummy2);
|
||||||
}
|
if (dcache_status())
|
||||||
if (dcache_status ()) {
|
|
||||||
blackfin_dcache_flush_range(dummy1, dummy1 + dummy2);
|
blackfin_dcache_flush_range(dummy1, dummy1 + dummy2);
|
||||||
}
|
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
|
@ -0,0 +1,109 @@
|
||||||
|
/*
|
||||||
|
* File: arch/blackfin/lib/memcmp.S
|
||||||
|
* Based on:
|
||||||
|
* Author:
|
||||||
|
*
|
||||||
|
* Created:
|
||||||
|
* Description:
|
||||||
|
*
|
||||||
|
* Rev: $Id: memcmp.S 2386 2006-11-01 04:57:26Z magicyang $
|
||||||
|
*
|
||||||
|
* Modified:
|
||||||
|
* Copyright 2004-2006 Analog Devices Inc.
|
||||||
|
*
|
||||||
|
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, see the file COPYING, or write
|
||||||
|
* to the Free Software Foundation, Inc.,
|
||||||
|
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
.align 2
|
||||||
|
|
||||||
|
/*
|
||||||
|
* C Library function MEMCMP
|
||||||
|
* R0 = First Address
|
||||||
|
* R1 = Second Address
|
||||||
|
* R2 = count
|
||||||
|
* Favours word aligned data.
|
||||||
|
*/
|
||||||
|
|
||||||
|
.globl _memcmp;
|
||||||
|
_memcmp:
|
||||||
|
I1 = P3;
|
||||||
|
P0 = R0; /* P0 = s1 address */
|
||||||
|
P3 = R1; /* P3 = s2 Address */
|
||||||
|
P2 = R2 ; /* P2 = count */
|
||||||
|
CC = R2 <= 7(IU);
|
||||||
|
IF CC JUMP .Ltoo_small;
|
||||||
|
I0 = R1; /* s2 */
|
||||||
|
R1 = R1 | R0; /* OR addresses together */
|
||||||
|
R1 <<= 30; /* check bottom two bits */
|
||||||
|
CC = AZ; /* AZ set if zero. */
|
||||||
|
IF !CC JUMP .Lbytes ; /* Jump if addrs not aligned. */
|
||||||
|
|
||||||
|
P1 = P2 >> 2; /* count = n/4 */
|
||||||
|
R3 = 3;
|
||||||
|
R2 = R2 & R3; /* remainder */
|
||||||
|
P2 = R2; /* set remainder */
|
||||||
|
|
||||||
|
LSETUP (.Lquad_loop_s , .Lquad_loop_e) LC0=P1;
|
||||||
|
.Lquad_loop_s:
|
||||||
|
NOP;
|
||||||
|
R0 = [P0++];
|
||||||
|
R1 = [I0++];
|
||||||
|
CC = R0 == R1;
|
||||||
|
IF !CC JUMP .Lquad_different;
|
||||||
|
.Lquad_loop_e:
|
||||||
|
NOP;
|
||||||
|
|
||||||
|
P3 = I0; /* s2 */
|
||||||
|
.Ltoo_small:
|
||||||
|
CC = P2 == 0; /* Check zero count*/
|
||||||
|
IF CC JUMP .Lfinished; /* very unlikely*/
|
||||||
|
|
||||||
|
.Lbytes:
|
||||||
|
LSETUP (.Lbyte_loop_s , .Lbyte_loop_e) LC0=P2;
|
||||||
|
.Lbyte_loop_s:
|
||||||
|
R1 = B[P3++](Z); /* *s2 */
|
||||||
|
R0 = B[P0++](Z); /* *s1 */
|
||||||
|
CC = R0 == R1;
|
||||||
|
IF !CC JUMP .Ldifferent;
|
||||||
|
.Lbyte_loop_e:
|
||||||
|
NOP;
|
||||||
|
|
||||||
|
.Ldifferent:
|
||||||
|
R0 = R0 - R1;
|
||||||
|
P3 = I1;
|
||||||
|
RTS;
|
||||||
|
|
||||||
|
.Lquad_different:
|
||||||
|
/* We've read two quads which don't match.
|
||||||
|
* Can't just compare them, because we're
|
||||||
|
* a little-endian machine, so the MSBs of
|
||||||
|
* the regs occur at later addresses in the
|
||||||
|
* string.
|
||||||
|
* Arrange to re-read those two quads again,
|
||||||
|
* byte-by-byte.
|
||||||
|
*/
|
||||||
|
P0 += -4; /* back up to the start of the */
|
||||||
|
P3 = I0; /* quads, and increase the*/
|
||||||
|
P2 += 4; /* remainder count*/
|
||||||
|
P3 += -4;
|
||||||
|
JUMP .Lbytes;
|
||||||
|
|
||||||
|
.Lfinished:
|
||||||
|
R0 = 0;
|
||||||
|
P3 = I1;
|
||||||
|
RTS;
|
|
@ -0,0 +1,130 @@
|
||||||
|
/*
|
||||||
|
* File: arch/blackfin/lib/memcpy.S
|
||||||
|
* Based on:
|
||||||
|
* Author:
|
||||||
|
*
|
||||||
|
* Created:
|
||||||
|
* Description: internal version of memcpy(), issued by the compiler
|
||||||
|
* to copy blocks of data around.
|
||||||
|
* This is really memmove() - it has to be able to deal with
|
||||||
|
* possible overlaps, because that ambiguity is when the compiler
|
||||||
|
* gives up and calls a function. We have our own, internal version
|
||||||
|
* so that we get something we trust, even if the user has redefined
|
||||||
|
* the normal symbol.
|
||||||
|
* Rev: $Id: memcpy.S 2775 2007-02-21 13:58:44Z hennerich $
|
||||||
|
*
|
||||||
|
* Modified:
|
||||||
|
* Copyright 2004-2006 Analog Devices Inc.
|
||||||
|
*
|
||||||
|
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, see the file COPYING, or write
|
||||||
|
* to the Free Software Foundation, Inc.,
|
||||||
|
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
.align 2
|
||||||
|
|
||||||
|
.globl _memcpy_ASM;
|
||||||
|
_memcpy_ASM:
|
||||||
|
CC = R2 <= 0; /* length not positive?*/
|
||||||
|
IF CC JUMP .L_P1L2147483647; /* Nothing to do */
|
||||||
|
|
||||||
|
P0 = R0 ; /* dst*/
|
||||||
|
P1 = R1 ; /* src*/
|
||||||
|
P2 = R2 ; /* length */
|
||||||
|
|
||||||
|
/* check for overlapping data */
|
||||||
|
CC = R1 < R0; /* src < dst */
|
||||||
|
IF !CC JUMP .Lno_overlap;
|
||||||
|
R3 = R1 + R2;
|
||||||
|
CC = R0 < R3; /* and dst < src+len */
|
||||||
|
IF CC JUMP .Lhas_overlap;
|
||||||
|
|
||||||
|
.Lno_overlap:
|
||||||
|
/* Check for aligned data.*/
|
||||||
|
|
||||||
|
R3 = R1 | R0;
|
||||||
|
R0 = 0x3;
|
||||||
|
R3 = R3 & R0;
|
||||||
|
CC = R3; /* low bits set on either address? */
|
||||||
|
IF CC JUMP .Lnot_aligned;
|
||||||
|
|
||||||
|
/* Both addresses are word-aligned, so we can copy
|
||||||
|
at least part of the data using word copies.*/
|
||||||
|
P2 = P2 >> 2;
|
||||||
|
CC = P2 <= 2;
|
||||||
|
IF !CC JUMP .Lmore_than_seven;
|
||||||
|
/* less than eight bytes... */
|
||||||
|
P2 = R2;
|
||||||
|
LSETUP(.Lthree_start, .Lthree_end) LC0=P2;
|
||||||
|
R0 = R1; /* setup src address for return */
|
||||||
|
.Lthree_start:
|
||||||
|
R3 = B[P1++] (X);
|
||||||
|
.Lthree_end:
|
||||||
|
B[P0++] = R3;
|
||||||
|
|
||||||
|
RTS;
|
||||||
|
|
||||||
|
.Lmore_than_seven:
|
||||||
|
/* There's at least eight bytes to copy. */
|
||||||
|
P2 += -1; /* because we unroll one iteration */
|
||||||
|
LSETUP(.Lword_loop, .Lword_loop) LC0=P2;
|
||||||
|
R0 = R1;
|
||||||
|
I1 = P1;
|
||||||
|
R3 = [I1++];
|
||||||
|
.Lword_loop:
|
||||||
|
MNOP || [P0++] = R3 || R3 = [I1++];
|
||||||
|
|
||||||
|
[P0++] = R3;
|
||||||
|
/* Any remaining bytes to copy? */
|
||||||
|
R3 = 0x3;
|
||||||
|
R3 = R2 & R3;
|
||||||
|
CC = R3 == 0;
|
||||||
|
P1 = I1; /* in case there's something left, */
|
||||||
|
IF !CC JUMP .Lbytes_left;
|
||||||
|
RTS;
|
||||||
|
.Lbytes_left: P2 = R3;
|
||||||
|
.Lnot_aligned:
|
||||||
|
/* From here, we're copying byte-by-byte. */
|
||||||
|
LSETUP (.Lbyte_start , .Lbyte_end) LC0=P2;
|
||||||
|
R0 = R1; /* Save src address for return */
|
||||||
|
.Lbyte_start:
|
||||||
|
R1 = B[P1++] (X);
|
||||||
|
.Lbyte_end:
|
||||||
|
B[P0++] = R1;
|
||||||
|
|
||||||
|
.L_P1L2147483647:
|
||||||
|
RTS;
|
||||||
|
|
||||||
|
.Lhas_overlap:
|
||||||
|
/* Need to reverse the copying, because the
|
||||||
|
* dst would clobber the src.
|
||||||
|
* Don't bother to work out alignment for
|
||||||
|
* the reverse case.
|
||||||
|
*/
|
||||||
|
R0 = R1; /* save src for later. */
|
||||||
|
P0 = P0 + P2;
|
||||||
|
P0 += -1;
|
||||||
|
P1 = P1 + P2;
|
||||||
|
P1 += -1;
|
||||||
|
LSETUP(.Lover_start, .Lover_end) LC0=P2;
|
||||||
|
.Lover_start:
|
||||||
|
R1 = B[P1--] (X);
|
||||||
|
.Lover_end:
|
||||||
|
B[P0--] = R1;
|
||||||
|
|
||||||
|
RTS;
|
|
@ -0,0 +1,102 @@
|
||||||
|
/*
|
||||||
|
* File: arch/blackfin/lib/memmove.S
|
||||||
|
* Based on:
|
||||||
|
* Author:
|
||||||
|
*
|
||||||
|
* Created:
|
||||||
|
* Description:
|
||||||
|
*
|
||||||
|
* Rev: $Id: memmove.S 2205 2006-09-23 07:53:49Z vapier $
|
||||||
|
*
|
||||||
|
* Modified:
|
||||||
|
* Copyright 2004-2006 Analog Devices Inc.
|
||||||
|
*
|
||||||
|
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, see the file COPYING, or write
|
||||||
|
* to the Free Software Foundation, Inc.,
|
||||||
|
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
.align 2
|
||||||
|
|
||||||
|
/*
|
||||||
|
* C Library function MEMMOVE
|
||||||
|
* R0 = To Address (leave unchanged to form result)
|
||||||
|
* R1 = From Address
|
||||||
|
* R2 = count
|
||||||
|
* Data may overlap
|
||||||
|
*/
|
||||||
|
|
||||||
|
.globl _memmove;
|
||||||
|
_memmove:
|
||||||
|
I1 = P3;
|
||||||
|
P0 = R0; /* P0 = To address */
|
||||||
|
P3 = R1; /* P3 = From Address */
|
||||||
|
P2 = R2 ; /* P2 = count */
|
||||||
|
CC = P2 == 0; /* Check zero count*/
|
||||||
|
IF CC JUMP .Lfinished; /* very unlikely */
|
||||||
|
|
||||||
|
CC = R1 < R0 (IU); /* From < To */
|
||||||
|
IF !CC JUMP .Lno_overlap;
|
||||||
|
R3 = R1 + R2;
|
||||||
|
CC = R0 <= R3 (IU); /* (From+len) >= To */
|
||||||
|
IF CC JUMP .Loverlap;
|
||||||
|
.Lno_overlap:
|
||||||
|
R3 = 11;
|
||||||
|
CC = R2 <= R3;
|
||||||
|
IF CC JUMP .Lbytes;
|
||||||
|
R3 = R1 | R0; /* OR addresses together */
|
||||||
|
R3 <<= 30; /* check bottom two bits */
|
||||||
|
CC = AZ; /* AZ set if zero.*/
|
||||||
|
IF !CC JUMP .Lbytes ; /* Jump if addrs not aligned.*/
|
||||||
|
|
||||||
|
I0 = P3;
|
||||||
|
P1 = P2 >> 2; /* count = n/4 */
|
||||||
|
P1 += -1;
|
||||||
|
R3 = 3;
|
||||||
|
R2 = R2 & R3; /* remainder */
|
||||||
|
P2 = R2; /* set remainder */
|
||||||
|
R1 = [I0++];
|
||||||
|
|
||||||
|
LSETUP (.Lquad_loop , .Lquad_loop) LC0=P1;
|
||||||
|
.Lquad_loop: MNOP || [P0++] = R1 || R1 = [I0++];
|
||||||
|
[P0++] = R1;
|
||||||
|
|
||||||
|
CC = P2 == 0; /* any remaining bytes? */
|
||||||
|
P3 = I0; /* Ammend P3 to updated ptr. */
|
||||||
|
IF !CC JUMP .Lbytes;
|
||||||
|
P3 = I1;
|
||||||
|
RTS;
|
||||||
|
|
||||||
|
.Lbytes: LSETUP (.Lbyte2_s , .Lbyte2_e) LC0=P2;
|
||||||
|
.Lbyte2_s: R1 = B[P3++](Z);
|
||||||
|
.Lbyte2_e: B[P0++] = R1;
|
||||||
|
|
||||||
|
.Lfinished: P3 = I1;
|
||||||
|
RTS;
|
||||||
|
|
||||||
|
.Loverlap:
|
||||||
|
P2 += -1;
|
||||||
|
P0 = P0 + P2;
|
||||||
|
P3 = P3 + P2;
|
||||||
|
R1 = B[P3--] (Z);
|
||||||
|
CC = P2 == 0;
|
||||||
|
IF CC JUMP .Lno_loop;
|
||||||
|
LSETUP (.Lol_s, .Lol_e) LC0 = P2;
|
||||||
|
.Lol_s: B[P0--] = R1;
|
||||||
|
.Lol_e: R1 = B[P3--] (Z);
|
||||||
|
.Lno_loop: B[P0] = R1;
|
||||||
|
P3 = I1;
|
||||||
|
RTS;
|
|
@ -0,0 +1,103 @@
|
||||||
|
/*
|
||||||
|
* File: arch/blackfin/lib/memset.S
|
||||||
|
* Based on:
|
||||||
|
* Author:
|
||||||
|
*
|
||||||
|
* Created:
|
||||||
|
* Description:
|
||||||
|
*
|
||||||
|
* Rev: $Id: memset.S 2769 2007-02-19 16:45:53Z hennerich $
|
||||||
|
*
|
||||||
|
* Modified:
|
||||||
|
* Copyright 2004-2006 Analog Devices Inc.
|
||||||
|
*
|
||||||
|
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, see the file COPYING, or write
|
||||||
|
* to the Free Software Foundation, Inc.,
|
||||||
|
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
.align 2
|
||||||
|
|
||||||
|
/*
|
||||||
|
* C Library function MEMSET
|
||||||
|
* R0 = address (leave unchanged to form result)
|
||||||
|
* R1 = filler byte
|
||||||
|
* R2 = count
|
||||||
|
* Favours word aligned data.
|
||||||
|
*/
|
||||||
|
|
||||||
|
.globl _memset;
|
||||||
|
_memset:
|
||||||
|
P0 = R0 ; /* P0 = address */
|
||||||
|
P2 = R2 ; /* P2 = count */
|
||||||
|
R3 = R0 + R2; /* end */
|
||||||
|
CC = R2 <= 7(IU);
|
||||||
|
IF CC JUMP .Ltoo_small;
|
||||||
|
R1 = R1.B (Z); /* R1 = fill char */
|
||||||
|
R2 = 3;
|
||||||
|
R2 = R0 & R2; /* addr bottom two bits */
|
||||||
|
CC = R2 == 0; /* AZ set if zero. */
|
||||||
|
IF !CC JUMP .Lforce_align ; /* Jump if addr not aligned. */
|
||||||
|
|
||||||
|
.Laligned:
|
||||||
|
P1 = P2 >> 2; /* count = n/4 */
|
||||||
|
R2 = R1 << 8; /* create quad filler */
|
||||||
|
R2.L = R2.L + R1.L(NS);
|
||||||
|
R2.H = R2.L + R1.H(NS);
|
||||||
|
P2 = R3;
|
||||||
|
|
||||||
|
LSETUP (.Lquad_loop , .Lquad_loop) LC0=P1;
|
||||||
|
.Lquad_loop:
|
||||||
|
[P0++] = R2;
|
||||||
|
|
||||||
|
CC = P0 == P2;
|
||||||
|
IF !CC JUMP .Lbytes_left;
|
||||||
|
RTS;
|
||||||
|
|
||||||
|
.Lbytes_left:
|
||||||
|
R2 = R3; /* end point */
|
||||||
|
R3 = P0; /* current position */
|
||||||
|
R2 = R2 - R3; /* bytes left */
|
||||||
|
P2 = R2;
|
||||||
|
|
||||||
|
.Ltoo_small:
|
||||||
|
CC = P2 == 0; /* Check zero count */
|
||||||
|
IF CC JUMP .Lfinished; /* Unusual */
|
||||||
|
|
||||||
|
.Lbytes:
|
||||||
|
LSETUP (.Lbyte_loop , .Lbyte_loop) LC0=P2;
|
||||||
|
.Lbyte_loop:
|
||||||
|
B[P0++] = R1;
|
||||||
|
|
||||||
|
.Lfinished:
|
||||||
|
RTS;
|
||||||
|
|
||||||
|
.Lforce_align:
|
||||||
|
CC = BITTST (R0, 0); /* odd byte */
|
||||||
|
R0 = 4;
|
||||||
|
R0 = R0 - R2;
|
||||||
|
P1 = R0;
|
||||||
|
R0 = P0; /* Recover return address */
|
||||||
|
IF !CC JUMP .Lskip1;
|
||||||
|
B[P0++] = R1;
|
||||||
|
.Lskip1:
|
||||||
|
CC = R2 <= 2; /* 2 bytes */
|
||||||
|
P2 -= P1; /* reduce count */
|
||||||
|
IF !CC JUMP .Laligned;
|
||||||
|
B[P0++] = R1;
|
||||||
|
B[P0++] = R1;
|
||||||
|
JUMP .Laligned;
|
|
@ -69,9 +69,10 @@ typedef int SItype __attribute__ ((mode (SI)));
|
||||||
typedef int DItype __attribute__ ((mode(DI)));
|
typedef int DItype __attribute__ ((mode(DI)));
|
||||||
typedef int word_type __attribute__ ((mode(__word__)));
|
typedef int word_type __attribute__ ((mode(__word__)));
|
||||||
|
|
||||||
struct DIstruct {SItype low, high;};
|
struct DIstruct {
|
||||||
typedef union
|
SItype low, high;
|
||||||
{
|
};
|
||||||
|
typedef union {
|
||||||
struct DIstruct s;
|
struct DIstruct s;
|
||||||
DItype ll;
|
DItype ll;
|
||||||
} DIunion;
|
} DIunion;
|
||||||
|
@ -81,8 +82,7 @@ DItype __muldi3 (DItype u, DItype v)
|
||||||
DIunion w;
|
DIunion w;
|
||||||
DIunion uu, vv;
|
DIunion uu, vv;
|
||||||
|
|
||||||
uu.ll = u,
|
uu.ll = u, vv.ll = v;
|
||||||
vv.ll = v;
|
|
||||||
/* panic("kernel panic for __muldi3"); */
|
/* panic("kernel panic for __muldi3"); */
|
||||||
w.ll = __umulsidi3(uu.s.low, vv.s.low);
|
w.ll = __umulsidi3(uu.s.low, vv.s.low);
|
||||||
w.s.high += ((USItype) uu.s.low * (USItype) vv.s.high
|
w.s.high += ((USItype) uu.s.low * (USItype) vv.s.high
|
||||||
|
|
|
@ -0,0 +1,435 @@
|
||||||
|
/*
|
||||||
|
* (C) Copyright 2002
|
||||||
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
#include <console.h>
|
||||||
|
#include <watchdog.h>
|
||||||
|
#include <post.h>
|
||||||
|
|
||||||
|
#ifdef CONFIG_LOGBUFFER
|
||||||
|
#include <logbuff.h>
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_POST
|
||||||
|
|
||||||
|
#define POST_MAX_NUMBER 32
|
||||||
|
|
||||||
|
#define BOOTMODE_MAGIC 0xDEAD0000
|
||||||
|
|
||||||
|
int post_init_f(void)
|
||||||
|
{
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
|
int res = 0;
|
||||||
|
unsigned int i;
|
||||||
|
|
||||||
|
for (i = 0; i < post_list_size; i++) {
|
||||||
|
struct post_test *test = post_list + i;
|
||||||
|
|
||||||
|
if (test->init_f && test->init_f()) {
|
||||||
|
res = -1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
gd->post_init_f_time = post_time_ms(0);
|
||||||
|
if (!gd->post_init_f_time) {
|
||||||
|
printf
|
||||||
|
("post/post.c: post_time_ms seems not to be implemented\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
void post_bootmode_init(void)
|
||||||
|
{
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
int bootmode = post_bootmode_get(0);
|
||||||
|
int newword;
|
||||||
|
|
||||||
|
if (post_hotkeys_pressed() && !(bootmode & POST_POWERTEST)) {
|
||||||
|
newword = BOOTMODE_MAGIC | POST_SLOWTEST;
|
||||||
|
} else if (bootmode == 0) {
|
||||||
|
newword = BOOTMODE_MAGIC | POST_POWERON;
|
||||||
|
} else if (bootmode == POST_POWERON || bootmode == POST_SLOWTEST) {
|
||||||
|
newword = BOOTMODE_MAGIC | POST_NORMAL;
|
||||||
|
} else {
|
||||||
|
/* Use old value */
|
||||||
|
newword = post_word_load() & ~POST_COLDBOOT;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (bootmode == 0) {
|
||||||
|
/* We are booting after power-on */
|
||||||
|
newword |= POST_COLDBOOT;
|
||||||
|
}
|
||||||
|
|
||||||
|
post_word_store(newword);
|
||||||
|
|
||||||
|
/* Reset activity record */
|
||||||
|
gd->post_log_word = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int post_bootmode_get(unsigned int *last_test)
|
||||||
|
{
|
||||||
|
unsigned long word = post_word_load();
|
||||||
|
int bootmode;
|
||||||
|
|
||||||
|
if ((word & 0xFFFF0000) != BOOTMODE_MAGIC) {
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
bootmode = word & 0x7F;
|
||||||
|
|
||||||
|
if (last_test && (bootmode & POST_POWERTEST)) {
|
||||||
|
*last_test = (word >> 8) & 0xFF;
|
||||||
|
}
|
||||||
|
|
||||||
|
return bootmode;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* POST tests run before relocation only mark status bits .... */
|
||||||
|
static void post_log_mark_start(unsigned long testid)
|
||||||
|
{
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
gd->post_log_word |= (testid) << 16;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void post_log_mark_succ(unsigned long testid)
|
||||||
|
{
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
gd->post_log_word |= testid;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* ... and the messages are output once we are relocated */
|
||||||
|
void post_output_backlog(void)
|
||||||
|
{
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
int j;
|
||||||
|
|
||||||
|
for (j = 0; j < post_list_size; j++) {
|
||||||
|
if (gd->post_log_word & (post_list[j].testid << 16)) {
|
||||||
|
post_log("POST %s ", post_list[j].cmd);
|
||||||
|
if (gd->post_log_word & post_list[j].testid)
|
||||||
|
post_log("PASSED\n");
|
||||||
|
else {
|
||||||
|
post_log("FAILED\n");
|
||||||
|
#ifdef CONFIG_SHOW_BOOT_PROGRESS
|
||||||
|
show_boot_progress(-31);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void post_bootmode_test_on(unsigned int last_test)
|
||||||
|
{
|
||||||
|
unsigned long word = post_word_load();
|
||||||
|
|
||||||
|
word |= POST_POWERTEST;
|
||||||
|
|
||||||
|
word |= (last_test & 0xFF) << 8;
|
||||||
|
|
||||||
|
post_word_store(word);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void post_bootmode_test_off(void)
|
||||||
|
{
|
||||||
|
unsigned long word = post_word_load();
|
||||||
|
|
||||||
|
word &= ~POST_POWERTEST;
|
||||||
|
|
||||||
|
post_word_store(word);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void post_get_flags(int *test_flags)
|
||||||
|
{
|
||||||
|
int flag[] = { POST_POWERON, POST_NORMAL, POST_SLOWTEST };
|
||||||
|
char *var[] = { "post_poweron", "post_normal", "post_slowtest" };
|
||||||
|
int varnum = sizeof(var) / sizeof(var[0]);
|
||||||
|
char list[128]; /* long enough for POST list */
|
||||||
|
char *name;
|
||||||
|
char *s;
|
||||||
|
int last;
|
||||||
|
int i, j;
|
||||||
|
|
||||||
|
for (j = 0; j < post_list_size; j++) {
|
||||||
|
test_flags[j] = post_list[j].flags;
|
||||||
|
}
|
||||||
|
|
||||||
|
for (i = 0; i < varnum; i++) {
|
||||||
|
if (getenv_r(var[i], list, sizeof(list)) <= 0)
|
||||||
|
continue;
|
||||||
|
|
||||||
|
for (j = 0; j < post_list_size; j++) {
|
||||||
|
test_flags[j] &= ~flag[i];
|
||||||
|
}
|
||||||
|
|
||||||
|
last = 0;
|
||||||
|
name = list;
|
||||||
|
while (!last) {
|
||||||
|
while (*name && *name == ' ')
|
||||||
|
name++;
|
||||||
|
if (*name == 0)
|
||||||
|
break;
|
||||||
|
s = name + 1;
|
||||||
|
while (*s && *s != ' ')
|
||||||
|
s++;
|
||||||
|
if (*s == 0)
|
||||||
|
last = 1;
|
||||||
|
else
|
||||||
|
*s = 0;
|
||||||
|
|
||||||
|
for (j = 0; j < post_list_size; j++) {
|
||||||
|
if (strcmp(post_list[j].cmd, name) == 0) {
|
||||||
|
test_flags[j] |= flag[i];
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (j == post_list_size) {
|
||||||
|
printf("No such test: %s\n", name);
|
||||||
|
}
|
||||||
|
|
||||||
|
name = s + 1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
for (j = 0; j < post_list_size; j++) {
|
||||||
|
if (test_flags[j] & POST_POWERON) {
|
||||||
|
test_flags[j] |= POST_SLOWTEST;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static int post_run_single(struct post_test *test,
|
||||||
|
int test_flags, int flags, unsigned int i)
|
||||||
|
{
|
||||||
|
if ((flags & test_flags & POST_ALWAYS) &&
|
||||||
|
(flags & test_flags & POST_MEM)) {
|
||||||
|
WATCHDOG_RESET();
|
||||||
|
|
||||||
|
if (!(flags & POST_REBOOT)) {
|
||||||
|
if ((test_flags & POST_REBOOT)
|
||||||
|
&& !(flags & POST_MANUAL)) {
|
||||||
|
post_bootmode_test_on(i);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (test_flags & POST_PREREL)
|
||||||
|
post_log_mark_start(test->testid);
|
||||||
|
else
|
||||||
|
post_log("POST %s ", test->cmd);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (test_flags & POST_PREREL) {
|
||||||
|
if ((*test->test) (flags) == 0)
|
||||||
|
post_log_mark_succ(test->testid);
|
||||||
|
} else {
|
||||||
|
if ((*test->test) (flags) != 0) {
|
||||||
|
post_log("FAILED\n");
|
||||||
|
#ifdef CONFIG_SHOW_BOOT_PROGRESS
|
||||||
|
show_boot_progress(-32);
|
||||||
|
#endif
|
||||||
|
} else
|
||||||
|
post_log("PASSED\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
if ((test_flags & POST_REBOOT) && !(flags & POST_MANUAL)) {
|
||||||
|
post_bootmode_test_off();
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
} else {
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
int post_run(char *name, int flags)
|
||||||
|
{
|
||||||
|
unsigned int i;
|
||||||
|
int test_flags[POST_MAX_NUMBER];
|
||||||
|
|
||||||
|
post_get_flags(test_flags);
|
||||||
|
|
||||||
|
if (name == NULL) {
|
||||||
|
unsigned int last;
|
||||||
|
|
||||||
|
if (post_bootmode_get(&last) & POST_POWERTEST) {
|
||||||
|
if (last < post_list_size &&
|
||||||
|
(flags & test_flags[last] & POST_ALWAYS) &&
|
||||||
|
(flags & test_flags[last] & POST_MEM)) {
|
||||||
|
|
||||||
|
post_run_single(post_list + last,
|
||||||
|
test_flags[last],
|
||||||
|
flags | POST_REBOOT, last);
|
||||||
|
|
||||||
|
for (i = last + 1; i < post_list_size; i++) {
|
||||||
|
post_run_single(post_list + i,
|
||||||
|
test_flags[i],
|
||||||
|
flags, i);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
for (i = 0; i < post_list_size; i++) {
|
||||||
|
post_run_single(post_list + i,
|
||||||
|
test_flags[i], flags, i);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
} else {
|
||||||
|
for (i = 0; i < post_list_size; i++) {
|
||||||
|
if (strcmp(post_list[i].cmd, name) == 0)
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (i < post_list_size) {
|
||||||
|
return post_run_single(post_list + i,
|
||||||
|
test_flags[i], flags, i);
|
||||||
|
} else {
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static int post_info_single(struct post_test *test, int full)
|
||||||
|
{
|
||||||
|
if (test->flags & POST_MANUAL) {
|
||||||
|
if (full)
|
||||||
|
printf("%s - %s\n"
|
||||||
|
" %s\n", test->cmd, test->name, test->desc);
|
||||||
|
else
|
||||||
|
printf(" %-15s - %s\n", test->cmd, test->name);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
} else {
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
int post_info(char *name)
|
||||||
|
{
|
||||||
|
unsigned int i;
|
||||||
|
|
||||||
|
if (name == NULL) {
|
||||||
|
for (i = 0; i < post_list_size; i++) {
|
||||||
|
post_info_single(post_list + i, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
} else {
|
||||||
|
for (i = 0; i < post_list_size; i++) {
|
||||||
|
if (strcmp(post_list[i].cmd, name) == 0)
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (i < post_list_size) {
|
||||||
|
return post_info_single(post_list + i, 1);
|
||||||
|
} else {
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
int post_log(char *format, ...)
|
||||||
|
{
|
||||||
|
va_list args;
|
||||||
|
uint i;
|
||||||
|
char printbuffer[CFG_PBSIZE];
|
||||||
|
|
||||||
|
va_start(args, format);
|
||||||
|
|
||||||
|
/* For this to work, printbuffer must be larger than
|
||||||
|
* anything we ever want to print.
|
||||||
|
*/
|
||||||
|
i = vsprintf(printbuffer, format, args);
|
||||||
|
va_end(args);
|
||||||
|
|
||||||
|
#ifdef CONFIG_LOGBUFFER
|
||||||
|
/* Send to the logbuffer */
|
||||||
|
logbuff_log(printbuffer);
|
||||||
|
#else
|
||||||
|
/* Send to the stdout file */
|
||||||
|
puts(printbuffer);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
void post_reloc(void)
|
||||||
|
{
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
|
unsigned int i;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* We have to relocate the test table manually
|
||||||
|
*/
|
||||||
|
for (i = 0; i < post_list_size; i++) {
|
||||||
|
ulong addr;
|
||||||
|
struct post_test *test = post_list + i;
|
||||||
|
|
||||||
|
if (test->name) {
|
||||||
|
addr = (ulong) (test->name) + gd->reloc_off;
|
||||||
|
test->name = (char *)addr;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (test->cmd) {
|
||||||
|
addr = (ulong) (test->cmd) + gd->reloc_off;
|
||||||
|
test->cmd = (char *)addr;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (test->desc) {
|
||||||
|
addr = (ulong) (test->desc) + gd->reloc_off;
|
||||||
|
test->desc = (char *)addr;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (test->test) {
|
||||||
|
addr = (ulong) (test->test) + gd->reloc_off;
|
||||||
|
test->test = (int (*)(int flags))addr;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (test->init_f) {
|
||||||
|
addr = (ulong) (test->init_f) + gd->reloc_off;
|
||||||
|
test->init_f = (int (*)(void))addr;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (test->reloc) {
|
||||||
|
addr = (ulong) (test->reloc) + gd->reloc_off;
|
||||||
|
test->reloc = (void (*)(void))addr;
|
||||||
|
|
||||||
|
test->reloc();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Some tests (e.g. SYSMON) need the time when post_init_f started,
|
||||||
|
* but we cannot use get_timer() at this point.
|
||||||
|
*
|
||||||
|
* On PowerPC we implement it using the timebase register.
|
||||||
|
*/
|
||||||
|
unsigned long post_time_ms(unsigned long base)
|
||||||
|
{
|
||||||
|
return (unsigned long)get_ticks() / (get_tbclk() / CFG_HZ) - base;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* CONFIG_POST */
|
|
@ -0,0 +1,253 @@
|
||||||
|
/*
|
||||||
|
* (C) Copyright 2002
|
||||||
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*
|
||||||
|
* Be sure to mark tests to be run before relocation as such with the
|
||||||
|
* CFG_POST_PREREL flag so that logging is done correctly if the
|
||||||
|
* logbuffer support is enabled.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
#include <config.h>
|
||||||
|
#ifdef CONFIG_POST
|
||||||
|
|
||||||
|
#include <post.h>
|
||||||
|
#define CFG_POST_FLASH 0x00004000
|
||||||
|
#define CFG_POST_LED 0x00008000
|
||||||
|
#define CFG_POST_BUTTON 0x00010000
|
||||||
|
|
||||||
|
extern int cache_post_test(int flags);
|
||||||
|
extern int watchdog_post_test(int flags);
|
||||||
|
extern int i2c_post_test(int flags);
|
||||||
|
extern int rtc_post_test(int flags);
|
||||||
|
extern int memory_post_test(int flags);
|
||||||
|
extern int cpu_post_test(int flags);
|
||||||
|
extern int uart_post_test(int flags);
|
||||||
|
extern int ether_post_test(int flags);
|
||||||
|
extern int spi_post_test(int flags);
|
||||||
|
extern int usb_post_test(int flags);
|
||||||
|
extern int spr_post_test(int flags);
|
||||||
|
extern int sysmon_post_test(int flags);
|
||||||
|
extern int dsp_post_test(int flags);
|
||||||
|
extern int codec_post_test(int flags);
|
||||||
|
|
||||||
|
extern int sysmon_init_f(void);
|
||||||
|
|
||||||
|
extern void sysmon_reloc(void);
|
||||||
|
|
||||||
|
extern int flash_post_test(int flags);
|
||||||
|
extern int led_post_test(int flags);
|
||||||
|
extern int button_post_test(int flags);
|
||||||
|
|
||||||
|
struct post_test post_list[] = {
|
||||||
|
#if CONFIG_POST & CFG_POST_CACHE
|
||||||
|
{
|
||||||
|
"Cache test",
|
||||||
|
"cache",
|
||||||
|
"This test verifies the CPU cache operation.",
|
||||||
|
POST_RAM | POST_ALWAYS,
|
||||||
|
&cache_post_test,
|
||||||
|
NULL,
|
||||||
|
NULL,
|
||||||
|
CFG_POST_CACHE},
|
||||||
|
#endif
|
||||||
|
#if CONFIG_POST & CFG_POST_WATCHDOG
|
||||||
|
{
|
||||||
|
"Watchdog timer test",
|
||||||
|
"watchdog",
|
||||||
|
"This test checks the watchdog timer.",
|
||||||
|
POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT,
|
||||||
|
&watchdog_post_test,
|
||||||
|
NULL,
|
||||||
|
NULL,
|
||||||
|
CFG_POST_WATCHDOG},
|
||||||
|
#endif
|
||||||
|
#if CONFIG_POST & CFG_POST_I2C
|
||||||
|
{
|
||||||
|
"I2C test",
|
||||||
|
"i2c",
|
||||||
|
"This test verifies the I2C operation.",
|
||||||
|
POST_RAM | POST_ALWAYS,
|
||||||
|
&i2c_post_test,
|
||||||
|
NULL,
|
||||||
|
NULL,
|
||||||
|
CFG_POST_I2C},
|
||||||
|
#endif
|
||||||
|
#if CONFIG_POST & CFG_POST_RTC
|
||||||
|
{
|
||||||
|
"RTC test",
|
||||||
|
"rtc",
|
||||||
|
"This test verifies the RTC operation.",
|
||||||
|
POST_RAM | POST_SLOWTEST | POST_MANUAL,
|
||||||
|
&rtc_post_test,
|
||||||
|
NULL,
|
||||||
|
NULL,
|
||||||
|
CFG_POST_RTC},
|
||||||
|
#endif
|
||||||
|
#if CONFIG_POST & CFG_POST_MEMORY
|
||||||
|
{
|
||||||
|
"Memory test",
|
||||||
|
"memory",
|
||||||
|
"This test checks RAM.",
|
||||||
|
POST_ROM | POST_POWERON | POST_SLOWTEST | POST_PREREL,
|
||||||
|
&memory_post_test,
|
||||||
|
NULL,
|
||||||
|
NULL,
|
||||||
|
CFG_POST_MEMORY},
|
||||||
|
#endif
|
||||||
|
#if CONFIG_POST & CFG_POST_CPU
|
||||||
|
{
|
||||||
|
"CPU test",
|
||||||
|
"cpu",
|
||||||
|
"This test verifies the arithmetic logic unit of" " CPU.",
|
||||||
|
POST_RAM | POST_ALWAYS,
|
||||||
|
&cpu_post_test,
|
||||||
|
NULL,
|
||||||
|
NULL,
|
||||||
|
CFG_POST_CPU},
|
||||||
|
#endif
|
||||||
|
#if CONFIG_POST & CFG_POST_UART
|
||||||
|
{
|
||||||
|
"UART test",
|
||||||
|
"uart",
|
||||||
|
"This test verifies the UART operation.",
|
||||||
|
POST_RAM | POST_SLOWTEST | POST_MANUAL,
|
||||||
|
&uart_post_test,
|
||||||
|
NULL,
|
||||||
|
NULL,
|
||||||
|
CFG_POST_UART},
|
||||||
|
#endif
|
||||||
|
#if CONFIG_POST & CFG_POST_ETHER
|
||||||
|
{
|
||||||
|
"ETHERNET test",
|
||||||
|
"ethernet",
|
||||||
|
"This test verifies the ETHERNET operation.",
|
||||||
|
POST_RAM | POST_ALWAYS | POST_MANUAL,
|
||||||
|
ðer_post_test,
|
||||||
|
NULL,
|
||||||
|
NULL,
|
||||||
|
CFG_POST_ETHER},
|
||||||
|
#endif
|
||||||
|
#if CONFIG_POST & CFG_POST_SPI
|
||||||
|
{
|
||||||
|
"SPI test",
|
||||||
|
"spi",
|
||||||
|
"This test verifies the SPI operation.",
|
||||||
|
POST_RAM | POST_ALWAYS | POST_MANUAL,
|
||||||
|
&spi_post_test,
|
||||||
|
NULL,
|
||||||
|
NULL,
|
||||||
|
CFG_POST_SPI},
|
||||||
|
#endif
|
||||||
|
#if CONFIG_POST & CFG_POST_USB
|
||||||
|
{
|
||||||
|
"USB test",
|
||||||
|
"usb",
|
||||||
|
"This test verifies the USB operation.",
|
||||||
|
POST_RAM | POST_ALWAYS | POST_MANUAL,
|
||||||
|
&usb_post_test,
|
||||||
|
NULL,
|
||||||
|
NULL,
|
||||||
|
CFG_POST_USB},
|
||||||
|
#endif
|
||||||
|
#if CONFIG_POST & CFG_POST_SPR
|
||||||
|
{
|
||||||
|
"SPR test",
|
||||||
|
"spr",
|
||||||
|
"This test checks SPR contents.",
|
||||||
|
POST_ROM | POST_ALWAYS | POST_PREREL,
|
||||||
|
&spr_post_test,
|
||||||
|
NULL,
|
||||||
|
NULL,
|
||||||
|
CFG_POST_SPR},
|
||||||
|
#endif
|
||||||
|
#if CONFIG_POST & CFG_POST_SYSMON
|
||||||
|
{
|
||||||
|
"SYSMON test",
|
||||||
|
"sysmon",
|
||||||
|
"This test monitors system hardware.",
|
||||||
|
POST_RAM | POST_ALWAYS,
|
||||||
|
&sysmon_post_test,
|
||||||
|
&sysmon_init_f,
|
||||||
|
&sysmon_reloc,
|
||||||
|
CFG_POST_SYSMON},
|
||||||
|
#endif
|
||||||
|
#if CONFIG_POST & CFG_POST_DSP
|
||||||
|
{
|
||||||
|
"DSP test",
|
||||||
|
"dsp",
|
||||||
|
"This test checks any connected DSP(s).",
|
||||||
|
POST_RAM | POST_MANUAL,
|
||||||
|
&dsp_post_test,
|
||||||
|
NULL,
|
||||||
|
NULL,
|
||||||
|
CFG_POST_DSP},
|
||||||
|
#endif
|
||||||
|
#if CONFIG_POST & CFG_POST_CODEC
|
||||||
|
{
|
||||||
|
"CODEC test",
|
||||||
|
"codec",
|
||||||
|
"This test checks any connected codec(s).",
|
||||||
|
POST_RAM | POST_MANUAL,
|
||||||
|
&codec_post_test,
|
||||||
|
NULL,
|
||||||
|
NULL,
|
||||||
|
CFG_POST_CODEC},
|
||||||
|
#endif
|
||||||
|
#if CONFIG_POST & CFG_POST_FLASH
|
||||||
|
{
|
||||||
|
"FLASH test",
|
||||||
|
"flash",
|
||||||
|
"This test checks flash.",
|
||||||
|
POST_RAM | POST_ALWAYS | POST_MANUAL,
|
||||||
|
&flash_post_test,
|
||||||
|
NULL,
|
||||||
|
NULL,
|
||||||
|
CFG_POST_FLASH},
|
||||||
|
#endif
|
||||||
|
#if CONFIG_POST & CFG_POST_LED
|
||||||
|
{
|
||||||
|
"LED test",
|
||||||
|
"LED",
|
||||||
|
"This test checks LED ",
|
||||||
|
POST_RAM | POST_ALWAYS | POST_MANUAL,
|
||||||
|
&led_post_test,
|
||||||
|
NULL,
|
||||||
|
NULL,
|
||||||
|
CFG_POST_LED},
|
||||||
|
#endif
|
||||||
|
#if CONFIG_POST & CFG_POST_BUTTON
|
||||||
|
{
|
||||||
|
"Button test",
|
||||||
|
"button",
|
||||||
|
"This test checks Button ",
|
||||||
|
POST_RAM | POST_ALWAYS | POST_MANUAL,
|
||||||
|
&button_post_test,
|
||||||
|
NULL,
|
||||||
|
NULL,
|
||||||
|
CFG_POST_BUTTON},
|
||||||
|
#endif
|
||||||
|
|
||||||
|
};
|
||||||
|
|
||||||
|
unsigned int post_list_size = sizeof(post_list) / sizeof(struct post_test);
|
||||||
|
|
||||||
|
#endif /* CONFIG_POST */
|
|
@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
|
||||||
LIB = $(obj)librtc.a
|
LIB = $(obj)librtc.a
|
||||||
|
|
||||||
COBJS = date.o \
|
COBJS = date.o \
|
||||||
bf533_rtc.o ds12887.o ds1302.o ds1306.o ds1307.o \
|
bf5xx_rtc.o ds12887.o ds1302.o ds1306.o ds1307.o \
|
||||||
ds1337.o ds1374.o ds1556.o ds164x.o ds174x.o ds3231.o \
|
ds1337.o ds1374.o ds1556.o ds164x.o ds174x.o ds3231.o \
|
||||||
m41t11.o max6900.o m48t35ax.o mc146818.o mk48t59.o \
|
m41t11.o max6900.o m48t35ax.o mc146818.o mk48t59.o \
|
||||||
mpc5xxx.o mpc8xx.o pcf8563.o s3c24x0_rtc.o rs5c372.o
|
mpc5xxx.o mpc8xx.o pcf8563.o s3c24x0_rtc.o rs5c372.o
|
||||||
|
|
|
@ -49,10 +49,10 @@
|
||||||
#include <command.h>
|
#include <command.h>
|
||||||
#include <rtc.h>
|
#include <rtc.h>
|
||||||
|
|
||||||
#if defined(CONFIG_RTC_BF533) && (CONFIG_COMMANDS & CFG_CMD_DATE)
|
#if defined(CONFIG_RTC_BFIN) && (CONFIG_COMMANDS & CFG_CMD_DATE)
|
||||||
|
|
||||||
#include <asm/blackfin.h>
|
#include <asm/blackfin.h>
|
||||||
#include <asm/cpu/bf533_rtc.h>
|
#include <asm/arch/bf5xx_rtc.h>
|
||||||
|
|
||||||
void rtc_reset(void)
|
void rtc_reset(void)
|
||||||
{
|
{
|
||||||
|
@ -137,9 +137,7 @@ void rtc_get (struct rtc_time *tmp)
|
||||||
|
|
||||||
/* Calculate the total number of seconds since Jan 1970 */
|
/* Calculate the total number of seconds since Jan 1970 */
|
||||||
time_in_sec = (tm_sec) +
|
time_in_sec = (tm_sec) +
|
||||||
MIN_TO_SECS (tm_min) +
|
MIN_TO_SECS(tm_min) + HRS_TO_SECS(tm_hour) + DAYS_TO_SECS(tm_day);
|
||||||
HRS_TO_SECS (tm_hour) +
|
|
||||||
DAYS_TO_SECS (tm_day);
|
|
||||||
to_tm(time_in_sec, tmp);
|
to_tm(time_in_sec, tmp);
|
||||||
}
|
}
|
||||||
#endif /* CONFIG_RTC_BF533 && CFG_CMD_DATE */
|
#endif /* CONFIG_RTC_BFIN && CFG_CMD_DATE */
|
Loading…
Reference in New Issue