173 lines
8.9 KiB
C
173 lines
8.9 KiB
C
/*
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* File: include/asm-blackfin/arch-bf533/anomaly.h
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* Based on:
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* Author:
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*
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* Created:
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* Description:
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*
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* Rev:
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*
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* Modified:
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*
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING.
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* If not, write to the Free Software Foundation,
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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/* This file shoule be up to date with:
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* - Revision U, May 17, 2006; ADSP-BF533 Blackfin Processor Anomaly List
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* - Revision Y, May 17, 2006; ADSP-BF532 Blackfin Processor Anomaly List
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* - Revision T, May 17, 2006; ADSP-BF531 Blackfin Processor Anomaly List
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*/
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#ifndef _MACH_ANOMALY_H_
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#define _MACH_ANOMALY_H_
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/* We do not support 0.1 or 0.2 silicon - sorry */
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#if (defined(CONFIG_BF_REV_0_1) || defined(CONFIG_BF_REV_0_2))
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#error Kernel will not work on BF533 Version 0.1 or 0.2
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#endif
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/* Issues that are common to 0.5, 0.4, and 0.3 silicon */
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#if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3))
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#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
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slot1 and store of a P register in slot 2 is not
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supported */
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#define ANOMALY_05000105 /* Watchpoint Status Register (WPSTAT) bits are set on
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every corresponding match */
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#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
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Channel DMA stops */
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#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
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registers. */
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#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out
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upper bits*/
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#define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */
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#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
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syncs */
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#define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not
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functional */
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#define ANOMALY_05000219 /* NMI event at boot time results in unpredictable
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state */
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#define ANOMALY_05000229 /* SPI Slave Boot Mode modifies registers */
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#define ANOMALY_05000272 /* Certain data cache write through modes fail for
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VDDint <=0.9V */
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#define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */
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#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
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an edge is detected may clear interrupt */
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#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
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DMA system instability */
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#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
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not restored */
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#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
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control */
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#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
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killed in a particular stage*/
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#endif
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/* These issues only occur on 0.3 or 0.4 BF533 */
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#if (defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3))
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#define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not
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updated at the same time. */
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#define ANOMALY_05000158 /* Boot fails when data cache enabled: Data from a Data
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Cache Fill can be corrupted after or during
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Instruction DMA if certain core stalls exist */
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#define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General
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Purpose TX or RX modes */
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#define ANOMALY_05000198 /* Failing SYSTEM MMR accesses when stalled by
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preceding memory read */
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#define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during
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inactive channels in certain conditions */
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#define ANOMALY_05000202 /* Possible infinite stall with specific dual dag
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situation */
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#define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */
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#define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */
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#define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect
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data*/
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#define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate
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Differences in certain Conditions */
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#define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */
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#define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to
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hardware reset */
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#define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or
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IDLE around a Change of Control causes
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unpredictable results */
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#define ANOMALY_05000245 /* Spurious Hardware Error from an access in the
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shadow of a conditional branch */
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#define ANOMALY_05000246 /* Data CPLB's should prevent spurious hardware
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errors */
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#define ANOMALY_05000253 /* Maximum external clock speed for Timers */
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#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event
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interrupt not functional */
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#define ANOMALY_05000257 /* An interrupt or exception during short Hardware
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loops may cause the instruction fetch unit to
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malfunction */
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#define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of
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the ICPLB Data registers differ */
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#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
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#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
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#define ANOMALY_05000262 /* Stores to data cache may be lost */
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#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */
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#define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE
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instruction will cause an infinite stall in the
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second to last instruction in a hardware loop */
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#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
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SPORT external receive and transmit clocks. */
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#define ANOMALY_05000269 /* High I/O activity causes the output voltage of the
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internal voltage regulator (VDDint) to increase. */
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#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the
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internal voltage regulator (VDDint) to decrease */
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#endif
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/* These issues are only on 0.4 silicon */
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#if (defined(CONFIG_BF_REV_0_4))
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#define ANOMALY_05000234 /* Incorrect Revision Number in DSPID Register */
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#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
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(TDM) */
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#endif
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/* These issues are only on 0.3 silicon */
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#if defined(CONFIG_BF_REV_0_3)
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#define ANOMALY_05000183 /* Timer Pin limitations for PPI TX Modes with
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External Frame Syncs */
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#define ANOMALY_05000189 /* False Protection Exceptions caused by Speculative
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Instruction or Data Fetches, or by Fetches at the
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boundary of reserved memory space */
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#define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs
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when polarity setting is changed */
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#define ANOMALY_05000194 /* Sport Restarting in specific modes may cause data
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corruption */
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#define ANOMALY_05000199 /* DMA current address shows wrong value during carry
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fix */
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#define ANOMALY_05000201 /* Receive frame sync not ignored during active
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frames in sport MCM */
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#define ANOMALY_05000203 /* Specific sequence that can cause DMA error or DMA
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stopping */
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#if defined(CONFIG_BF533)
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#define ANOMALY_05000204 /* Incorrect data read with write-through cache and
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allocate cache lines on reads only mode */
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#endif /* CONFIG_BF533 */
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#define ANOMALY_05000207 /* Recovery from "brown-out" condition */
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#define ANOMALY_05000209 /* Speed-Path in computational unit affects certain
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instructions */
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#define ANOMALY_05000233 /* PPI_FS3 is not driven in 2 or 3 internal Frame
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Sync Transmit Mode */
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#define ANOMALY_05000271 /* Spontaneous reset of Internal Voltage Regulator */
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#endif
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#endif /* _MACH_ANOMALY_H_ */
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