Coding style cleanup
Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese
parent
157cda4d0c
commit
35d22f957a
2
MAKEALL
2
MAKEALL
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@ -91,7 +91,7 @@ LIST_4xx=" \
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PPChameleonEVB sbc405 sc3 sequoia \
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sequoia_nand taishan VOH405 VOM405 \
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W7OLMC W7OLMG walnut WUH405 \
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XPEDITE1K yellowstone yosemite yucca \
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XPEDITE1K yellowstone yosemite yucca \
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"
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#########################################################################
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8
Makefile
8
Makefile
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@ -1040,7 +1040,7 @@ ADCIOP_config: unconfig
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@$(MKCONFIG) $(@:_config=) ppc ppc4xx adciop esd
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alpr_config: unconfig
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@./mkconfig $(@:_config=) ppc ppc4xx alpr prodrive
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@$(MKCONFIG) $(@:_config=) ppc ppc4xx alpr prodrive
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AP1000_config:unconfig
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@$(MKCONFIG) $(@:_config=) ppc ppc4xx ap1000 amirix
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@ -1135,10 +1135,10 @@ G2000_config: unconfig
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@$(MKCONFIG) $(@:_config=) ppc ppc4xx g2000
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hcu4_config: unconfig
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@./mkconfig $(@:_config=) ppc ppc4xx hcu4 netstal
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@$(MKCONFIG) $(@:_config=) ppc ppc4xx hcu4 netstal
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hcu5_config: unconfig
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@./mkconfig $(@:_config=) ppc ppc4xx hcu5 netstal
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@$(MKCONFIG) $(@:_config=) ppc ppc4xx hcu5 netstal
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HH405_config: unconfig
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@$(MKCONFIG) $(@:_config=) ppc ppc4xx hh405 esd
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@ -1258,7 +1258,7 @@ rainier_nand_config: unconfig
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@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
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sc3_config:unconfig
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@./mkconfig $(@:_config=) ppc ppc4xx sc3
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@$(MKCONFIG) $(@:_config=) ppc ppc4xx sc3
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taishan_config: unconfig
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@$(MKCONFIG) $(@:_config=) ppc ppc4xx taishan amcc
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@ -39,4 +39,3 @@ U_BOOT_CMD(
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"Help for Netstal Maschinen BSP specific command.\n"
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);
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#endif
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@ -26,4 +26,3 @@ TEXT_BASE = 0xFFFa0000
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ifeq ($(debug),1)
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PLATFORM_CPPFLAGS += -DDEBUG -g
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endif
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@ -27,10 +27,30 @@
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DECLARE_GLOBAL_DATA_PTR;
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#define HCU_MACH_VERSIONS_REGISTER (0x7C000000 + 0xF00000)
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#define mtsdram(reg, data) { mtdcr(memcfga,reg);mtdcr(memcfgd,data); }
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#define mfsdram(value, reg) { mtdcr(memcfga,reg); value = mfdcr(memcfgd); }
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#define SDRAM_LEN 32*1024*1024 /* 32 MB -RAM */
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#define DO_UGLY_SDRAM_WORKAROUND
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enum {
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/* HW_GENERATION_HCU wird nicht mehr unterstuetzt */
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HW_GENERATION_HCU2 = 0x10,
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HW_GENERATION_HCU3 = 0x10,
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HW_GENERATION_HCU4 = 0x20,
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HW_GENERATION_MCU = 0x08,
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HW_GENERATION_MCU20 = 0x0a,
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HW_GENERATION_MCU25 = 0x09,
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};
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void sysLedSet(u32 value);
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long int spd_sdram(int(read_spd)(uint addr))
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long int spd_sdram(int(read_spd)(uint addr));
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#ifdef CONFIG_SPD_EEPROM
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#define DEBUG
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#define DEBUG
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#endif
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#if defined(DEBUG)
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@ -86,26 +106,15 @@ int board_pre_init (void)
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{
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return board_early_init_f ();
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}
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#endif
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enum {
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/* HW_GENERATION_HCU wird nicht mehr unterstuetzt */
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HW_GENERATION_HCU2 = 0x10,
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HW_GENERATION_HCU3 = 0x10,
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HW_GENERATION_HCU4 = 0x20,
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HW_GENERATION_MCU = 0x08,
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HW_GENERATION_MCU20 = 0x0a,
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HW_GENERATION_MCU25 = 0x09,
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};
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int checkboard (void)
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{
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#define HCU_MACH_VERSIONS_REGISTER ( 0x7C000000 + 0xF00000 )
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unsigned j;
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uint16_t *boardVersReg = (uint16_t *) HCU_MACH_VERSIONS_REGISTER;
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uint16_t generation = *boardVersReg & 0xf0;
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uint16_t index = *boardVersReg & 0x0f;
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unsigned int j;
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u16 *boardVersReg = (u16 *) HCU_MACH_VERSIONS_REGISTER;
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u16 generation = *boardVersReg & 0xf0;
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u16 index = *boardVersReg & 0x0f;
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/* Force /RTS to active. The board it not wired quite
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correctly to use cts/rtc flow control, so just force the
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/RST active and forget about it. */
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@ -117,24 +126,26 @@ int checkboard (void)
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printf ("HCU4: index %d\n\n", index);
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/* GPIO here noch nicht richtig initialisert !!! */
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sysLedSet(0);
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for (j=0; j < 7;j++) {
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for (j = 0; j < 7; j++) {
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sysLedSet(1 << j);
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udelay(50*1000);
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udelay(50 * 1000);
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}
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return 0;
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}
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u32 sysLedGet(void)
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{
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return( ~( (*(u32 *)GPIO0_OR)) >> 23) & 0xff;
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return (~((*(u32 *)GPIO0_OR)) >> 23) & 0xff;
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}
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void sysLedSet(u32 value /* value to place in LEDs */)
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{
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u32 tmp = ~value;
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u32 *ledReg;
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tmp = (tmp << 23) | 0x7FFFFF;
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ledReg = (u32 *)GPIO0_OR;
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tmp = (tmp << 23) | 0x7FFFFF;
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ledReg = (u32 *)GPIO0_OR;
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*ledReg = tmp;
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}
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@ -147,13 +158,11 @@ void sdram_init(void)
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return;
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}
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#define mtsdram(reg, data) { mtdcr(memcfga,reg);mtdcr(memcfgd,data); }
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#define mfsdram(value, reg) { mtdcr(memcfga,reg); value = mfdcr(memcfgd); }
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#if defined(DEBUG)
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void show_sdram_registers(void)
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{
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u32 value;
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printf ("SDRAM Controller Registers --\n");
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mfsdram(value, mem_mcopt1);
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printf (" SDRAM0_CFG : 0x%08x\n", value);
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@ -170,8 +179,6 @@ void show_sdram_registers(void)
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}
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#endif
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#define SDRAM_LEN 32*1024*1024 /* 32 MB -RAM */
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/*
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* this is even after checkboard. It returns the size of the SDRAM
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* that we have installed. This function is called by board_init_f
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@ -244,9 +251,10 @@ long int fixed_hcu4_sdram (int board_type)
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static u32 getSerialNr(void)
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{
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u32 *serial = (u32 *)CFG_FLASH_BASE;
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if (*serial == 0xffffffff) {
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if (*serial == 0xffffffff)
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return get_ticks();
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}
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return *serial;
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}
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@ -260,12 +268,14 @@ int misc_init_r(void)
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char *s = getenv("ethaddr");
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char *e;
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int i;
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u32 serial = getSerialNr();
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u32 serial = getSerialNr();
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for (i = 0; i < 6; ++i) {
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gd->bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0;
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if (s)
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s = (*e) ? e + 1 : e;
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}
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if (gd->bd->bi_enetaddr[3] == 0 &&
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gd->bd->bi_enetaddr[4] == 0 &&
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gd->bd->bi_enetaddr[5] == 0) {
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@ -288,13 +298,14 @@ int misc_init_r(void)
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return 0;
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}
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#define DO_UGLY_SDRAM_WORKAROUND
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#ifdef DO_UGLY_SDRAM_WORKAROUND
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#include "i2c.h"
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#include "i2c.h"
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void set_spd_default_value(unsigned int spd_addr,uchar def_val)
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{
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uchar value;
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int res = i2c_read(SPD_EEPROM_ADDRESS, spd_addr, 1, &value, 1) ;
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if (res == 0 && value == 0xff) {
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res = i2c_write(SPD_EEPROM_ADDRESS,
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spd_addr, 1, &def_val, 1) ;
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@ -387,7 +398,6 @@ long int initdram(int board_type)
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bcu4_testdram(dram_size);
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printf("%s %d MB of SDRAM\n", __FUNCTION__, dram_size/(1024*1024));
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#endif
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return dram_size;
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}
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@ -28,4 +28,3 @@ PLATFORM_CPPFLAGS += -DCONFIG_440=1
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ifeq ($(debug),1)
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PLATFORM_CPPFLAGS += -DDEBUG -g
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endif
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@ -29,12 +29,34 @@ void sysLedSet(u32 value);
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extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
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#define mtcpr0(reg, data) do { mtdcr(CPR0_CFGADDR,reg); \
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mtdcr(CPR0_CFGDATA,data); } while (0)
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#define mfcpr0(reg, data) do { mtdcr(CPR0_CFGADDR,reg); \
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data = mfdcr(CPR0_CFGDATA); } while (0)
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#undef BOOTSTRAP_OPTION_A_ACTIVE
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#define SDR0_CP440 0x0180
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#define SYSTEM_RESET 0x30000000
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#define CHIP_RESET 0x20000000
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#define SDR0_ECID0 0x0080
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#define SDR0_ECID1 0x0081
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#define SDR0_ECID2 0x0082
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#define SDR0_ECID3 0x0083
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#define SYS_IO_ADDRESS 0xcce00000
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#define DEFAULT_ETH_ADDR "ethaddr"
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/* ethaddr for first or etha1ddr for second ethernet */
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enum {
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/* HW_GENERATION_HCU1 is no longer supported */
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HW_GENERATION_HCU2 = 0x10,
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HW_GENERATION_HCU3 = 0x10,
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HW_GENERATION_HCU4 = 0x20,
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HW_GENERATION_HCU5 = 0x30,
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HW_GENERATION_MCU = 0x08,
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HW_GENERATION_MCU20 = 0x0a,
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HW_GENERATION_MCU25 = 0x09,
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};
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#define SDR0_CP440 0x0180
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/*
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* This function is run very early, out of flash, and before devices are
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@ -50,7 +72,6 @@ int board_early_init_f(void)
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{
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u32 reg;
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#undef BOOTSTRAP_OPTION_A_ACTIVE
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#ifdef BOOTSTRAP_OPTION_A_ACTIVE
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/* Booting with Bootstrap Option A
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* First boot, with CPR0_ICFG_RLI_MASK == 0
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@ -64,27 +85,26 @@ int board_early_init_f(void)
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u32 cpr0icfg;
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u32 dbcr;
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mfcpr0(CPR0_ICFG, cpr0icfg);
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if ( ! (cpr0icfg & CPR0_ICFG_RLI_MASK ) ) {
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mtcpr0(CPR0_MALD, 0x02000000);
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mtcpr0(CPR0_OPBD, 0x02000000);
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mtcpr0(CPR0_PERD, 0x05000000); /* 1:5 */
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mtcpr0(CPR0_PLLC, 0x40000238);
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mtcpr0(CPR0_PLLD, 0x01010414);
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mtcpr0(CPR0_PRIMAD, 0x01000000);
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mtcpr0(CPR0_PRIMBD, 0x01000000);
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mtcpr0(CPR0_SPCID, 0x03000000);
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mtsdr(SDR0_PFC0, 0x00003E00); /* [CTE] = 0 */
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mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/
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mtcpr0(CPR0_ICFG, cpr0icfg | CPR0_ICFG_RLI_MASK);
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mfcpr(CPR0_ICFG, cpr0icfg);
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if (!(cpr0icfg & CPR0_ICFG_RLI_MASK)) {
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mtcpr(CPR0_MALD, 0x02000000);
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mtcpr(CPR0_OPBD, 0x02000000);
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mtcpr(CPR0_PERD, 0x05000000); /* 1:5 */
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mtcpr(CPR0_PLLC, 0x40000238);
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mtcpr(CPR0_PLLD, 0x01010414);
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mtcpr(CPR0_PRIMAD, 0x01000000);
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mtcpr(CPR0_PRIMBD, 0x01000000);
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mtcpr(CPR0_SPCID, 0x03000000);
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mtsdr(SDR0_PFC0, 0x00003E00); /* [CTE] = 0 */
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mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/
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mtcpr(CPR0_ICFG, cpr0icfg | CPR0_ICFG_RLI_MASK);
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/*
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* Initiate system reset in debug control register DBCR
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*/
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dbcr = mfspr(dbcr0);
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#define SYSTEM_RESET 0x30000000
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#define CHIP_RESET 0x20000000
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mtspr(dbcr0, dbcr | CHIP_RESET );
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mtspr(dbcr0, dbcr | CHIP_RESET);
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}
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mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/
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#endif
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@ -162,60 +182,42 @@ int board_early_init_f(void)
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return 0;
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}
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#ifdef CONFIG_BOARD_PRE_INIT
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int board_pre_init (void)
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int board_pre_init(void)
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{
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return board_early_init_f ();
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return board_early_init_f();
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}
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#endif
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enum {
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/* HW_GENERATION_HCU1 is no longer supported */
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HW_GENERATION_HCU2 = 0x10,
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HW_GENERATION_HCU3 = 0x10,
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HW_GENERATION_HCU4 = 0x20,
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HW_GENERATION_HCU5 = 0x30,
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HW_GENERATION_MCU = 0x08,
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HW_GENERATION_MCU20 = 0x0a,
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HW_GENERATION_MCU25 = 0x09,
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};
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int checkboard (void)
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int checkboard(void)
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{
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#define SDR0_ECID0 0x0080
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#define SDR0_ECID1 0x0081
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#define SDR0_ECID2 0x0082
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#define SDR0_ECID3 0x0083
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unsigned j;
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uint16_t *hwVersReg = (uint16_t *) HCU_HW_VERSION_REGISTER;
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uint16_t *boardVersReg = (uint16_t *) HCU_CPLD_VERSION_REGISTER;
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uint16_t generation = *boardVersReg & 0xf0;
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uint16_t index = *boardVersReg & 0x0f;
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ulong ecid0, ecid1, ecid2, ecid3;
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printf ("Netstal Maschinen AG: ");
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unsigned int j;
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u16 *hwVersReg = (u16 *) HCU_HW_VERSION_REGISTER;
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u16 *boardVersReg = (u16 *) HCU_CPLD_VERSION_REGISTER;
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u16 generation = *boardVersReg & 0xf0;
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u16 index = *boardVersReg & 0x0f;
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u32 ecid0, ecid1, ecid2, ecid3;
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printf("Netstal Maschinen AG: ");
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if (generation == HW_GENERATION_HCU3)
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printf ("HCU3: index %d", index);
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printf("HCU3: index %d", index);
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else if (generation == HW_GENERATION_HCU4)
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printf ("HCU4: index %d", index);
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printf("HCU4: index %d", index);
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else if (generation == HW_GENERATION_HCU5)
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printf ("HCU5: index %d", index);
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printf (" HW 0x%02x\n", *hwVersReg & 0xff);
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printf("HCU5: index %d", index);
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printf(" HW 0x%02x\n", *hwVersReg & 0xff);
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mfsdr(SDR0_ECID0, ecid0);
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mfsdr(SDR0_ECID1, ecid1);
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mfsdr(SDR0_ECID2, ecid2);
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mfsdr(SDR0_ECID3, ecid3);
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printf("Chip ID 0x%x 0x%x 0x%x 0x%x\n", ecid0, ecid1, ecid2, ecid3);
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for (j=0; j < 6;j++) {
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printf("Chip ID 0x%x 0x%x 0x%x 0x%x\n", ecid0, ecid1, ecid2, ecid3);
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for (j = 0;j < 6; j++) {
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sysLedSet(1 << j);
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udelay(200*1000);
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udelay(200 * 1000);
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}
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return 0;
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}
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#define SYS_IO_ADDRESS 0xcce00000
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u32 sysLedGet(void)
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{
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return in16(SYS_IO_ADDRESS) & 0x3f;
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@ -232,9 +234,10 @@ void sysLedSet(u32 value /* value to place in LEDs */)
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static u32 getSerialNr(void)
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{
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u32 *serial = (u32 *)CFG_FLASH_BASE;
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if (*serial == 0xffffffff) {
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if (*serial == 0xffffffff)
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return get_ticks();
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}
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return *serial;
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}
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|
|
@ -242,45 +245,44 @@ static u32 getSerialNr(void)
|
|||
/*---------------------------------------------------------------------------+
|
||||
* misc_init_r.
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
#define DEFAULT_ETH_ADDR "ethaddr"
|
||||
/* ethaddr for first or etha1ddr for second ethernet */
|
||||
|
||||
int misc_init_r(void)
|
||||
{
|
||||
char *s = getenv(DEFAULT_ETH_ADDR);
|
||||
char *e;
|
||||
int i;
|
||||
u32 serial = getSerialNr();
|
||||
u32 serial = getSerialNr();
|
||||
unsigned long usb2d0cr = 0;
|
||||
unsigned long usb2phy0cr, usb2h0cr = 0;
|
||||
unsigned long sdr0_pfc1;
|
||||
|
||||
for (i = 0; i < 6; ++i) {
|
||||
gd->bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0;
|
||||
gd->bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0;
|
||||
if (s)
|
||||
s = (*e) ? e + 1 : e;
|
||||
}
|
||||
|
||||
if (gd->bd->bi_enetaddr[3] == 0 &&
|
||||
gd->bd->bi_enetaddr[4] == 0 &&
|
||||
gd->bd->bi_enetaddr[5] == 0) {
|
||||
char ethaddr[22];
|
||||
|
||||
/* Must be in sync with CONFIG_ETHADDR */
|
||||
gd->bd->bi_enetaddr[0] = 0x00;
|
||||
gd->bd->bi_enetaddr[1] = 0x60;
|
||||
gd->bd->bi_enetaddr[2] = 0x13;
|
||||
gd->bd->bi_enetaddr[3] = (serial >> 16) & 0xff;
|
||||
gd->bd->bi_enetaddr[4] = (serial >> 8) & 0xff;
|
||||
gd->bd->bi_enetaddr[3] = (serial >> 16) & 0xff;
|
||||
gd->bd->bi_enetaddr[4] = (serial >> 8) & 0xff;
|
||||
/* byte[5].bit 0 must be zero */
|
||||
gd->bd->bi_enetaddr[5] = (serial >> 0) & 0xfe;
|
||||
sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X\0",
|
||||
gd->bd->bi_enetaddr[0], gd->bd->bi_enetaddr[1],
|
||||
gd->bd->bi_enetaddr[2], gd->bd->bi_enetaddr[3],
|
||||
gd->bd->bi_enetaddr[4], gd->bd->bi_enetaddr[5]) ;
|
||||
gd->bd->bi_enetaddr[5] = (serial >> 0) & 0xfe;
|
||||
sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X\0",
|
||||
gd->bd->bi_enetaddr[0], gd->bd->bi_enetaddr[1],
|
||||
gd->bd->bi_enetaddr[2], gd->bd->bi_enetaddr[3],
|
||||
gd->bd->bi_enetaddr[4], gd->bd->bi_enetaddr[5]) ;
|
||||
printf("%s: Setting eth %s serial 0x%x\n", __FUNCTION__,
|
||||
ethaddr, serial);
|
||||
setenv (DEFAULT_ETH_ADDR, ethaddr);
|
||||
setenv(DEFAULT_ETH_ADDR, ethaddr);
|
||||
}
|
||||
|
||||
#ifdef CFG_ENV_IS_IN_FLASH
|
||||
/* Monitor protection ON by default */
|
||||
(void)flash_protect(FLAG_PROTECT_SET,
|
||||
|
|
@ -334,9 +336,9 @@ int misc_init_r(void)
|
|||
mtsdr(SDR0_USB2H0CR, usb2h0cr);
|
||||
|
||||
/*clear resets*/
|
||||
udelay (1000);
|
||||
udelay(1000);
|
||||
mtsdr(SDR0_SRST1, 0x00000000);
|
||||
udelay (1000);
|
||||
udelay(1000);
|
||||
mtsdr(SDR0_SRST0, 0x00000000);
|
||||
|
||||
printf("USB: Host(int phy) Device(ext phy)\n");
|
||||
|
|
@ -356,7 +358,7 @@ int misc_init_r(void)
|
|||
* certain pre-initialization actions.
|
||||
*
|
||||
************************************************************************/
|
||||
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
|
||||
#if defined(CONFIG_PCI)
|
||||
int pci_pre_init(struct pci_controller *hose)
|
||||
{
|
||||
unsigned long addr;
|
||||
|
|
@ -374,7 +376,7 @@ int pci_pre_init(struct pci_controller *hose)
|
|||
mfsdr(sdr_amp1, addr);
|
||||
mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
|
||||
addr = mfdcr(plb3_acr);
|
||||
// mtdcr(plb3_acr, addr & ~plb1_acr_wrp_mask); /* ngngng */
|
||||
/* mtdcr(plb3_acr, addr & ~plb1_acr_wrp_mask); */ /* ngngng */
|
||||
mtdcr(plb3_acr, addr | 0x80000000); /* Sequoia */
|
||||
|
||||
/*-------------------------------------------------------------------+
|
||||
|
|
@ -383,7 +385,7 @@ int pci_pre_init(struct pci_controller *hose)
|
|||
mfsdr(sdr_amp0, addr);
|
||||
mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
|
||||
addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
|
||||
// mtdcr(plb4_acr, addr & ~plb1_acr_wrp_mask); /* ngngng */
|
||||
/* mtdcr(plb4_acr, addr & ~plb1_acr_wrp_mask); */ /* ngngng */
|
||||
mtdcr(plb4_acr, addr); /* Sequoia */
|
||||
|
||||
/*-------------------------------------------------------------------+
|
||||
|
|
@ -393,24 +395,23 @@ int pci_pre_init(struct pci_controller *hose)
|
|||
addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
|
||||
addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
|
||||
addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
|
||||
// addr = (addr & ~plb0_acr_wrp_mask) ; /* ngngng */
|
||||
/* addr = (addr & ~plb0_acr_wrp_mask); */ /* ngngng */
|
||||
addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; /* Sequoia */
|
||||
|
||||
// mtdcr(plb0_acr, addr); /* Sequoia */
|
||||
mtdcr(plb0_acr, 0); // PATCH HAB: WRITE PIPELINING OFF
|
||||
|
||||
/* mtdcr(plb0_acr, addr); */ /* Sequoia */
|
||||
mtdcr(plb0_acr, 0); /* PATCH HAB: WRITE PIPELINING OFF */
|
||||
|
||||
/* Segment1 */
|
||||
addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
|
||||
addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
|
||||
addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
|
||||
addr = (addr & ~plb1_acr_wrp_mask) ;
|
||||
// mtdcr(plb1_acr, addr); /* Sequoia */
|
||||
mtdcr(plb1_acr, 0); // PATCH HAB: WRITE PIPELINING OFF
|
||||
/* mtdcr(plb1_acr, addr); */ /* Sequoia */
|
||||
mtdcr(plb1_acr, 0); /* PATCH HAB: WRITE PIPELINING OFF */
|
||||
|
||||
return 1;
|
||||
}
|
||||
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
|
||||
#endif /* defined(CONFIG_PCI) */
|
||||
|
||||
/*************************************************************************
|
||||
* pci_target_init
|
||||
|
|
@ -476,7 +477,6 @@ void pci_target_init(struct pci_controller *hose)
|
|||
pci_write_config_word(0, PCI_ERREN, 0);
|
||||
|
||||
pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
|
||||
|
||||
}
|
||||
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
|
||||
|
||||
|
|
@ -523,4 +523,3 @@ int is_pci_host(struct pci_controller *hose)
|
|||
return 1;
|
||||
}
|
||||
#endif /* defined(CONFIG_PCI) */
|
||||
|
||||
|
|
|
|||
|
|
@ -55,7 +55,7 @@ tlbtab:
|
|||
tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
|
||||
|
||||
/* TLB-entry for EBC (CFG_CPLD) */
|
||||
// tlbentry( CFG_CPLD, SZ_1K, CFG_CPLD, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
/* tlbentry( CFG_CPLD, SZ_1K, CFG_CPLD, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) */
|
||||
/* CAN */
|
||||
tlbentry( CFG_CS_1, SZ_16M, CFG_CS_1, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
/* IMC + CPLD */
|
||||
|
|
@ -77,5 +77,3 @@ tlbtab:
|
|||
/* TLB for SDRAM will be added by initdram (sdram.c) */
|
||||
|
||||
tlbtab_end
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -216,8 +216,9 @@ long int initdram (int board_type)
|
|||
{
|
||||
#define HCU_HW_SDRAM_CONFIG_MASK 0x7
|
||||
#define INVALID_HW_CONFIG "Invalid HW-Config"
|
||||
uint16_t *hwVersReg = (uint16_t *) HCU_HW_VERSION_REGISTER;
|
||||
unsigned int dram_size=0;
|
||||
u16 *hwVersReg = (u16 *) HCU_HW_VERSION_REGISTER;
|
||||
unsigned int dram_size = 0;
|
||||
|
||||
mtsdram(DDR0_02, 0x00000000);
|
||||
|
||||
/* Values must be kept in sync with Excel-table <<A0001492.>> ! */
|
||||
|
|
@ -229,15 +230,15 @@ long int initdram (int board_type)
|
|||
switch (*hwVersReg & HCU_HW_SDRAM_CONFIG_MASK) {
|
||||
case 0:
|
||||
dram_size = 128 * 1024 * 1024 ;
|
||||
mtsdram(DDR0_06, 0x0102C80D); // 128MB RAM
|
||||
mtsdram(DDR0_11, 0x000FC800); // 128MB RAM
|
||||
mtsdram(DDR0_43, 0x030A0300); // 128MB RAM
|
||||
mtsdram(DDR0_06, 0x0102C80D); /* 128MB RAM */
|
||||
mtsdram(DDR0_11, 0x000FC800); /* 128MB RAM */
|
||||
mtsdram(DDR0_43, 0x030A0300); /* 128MB RAM */
|
||||
break;
|
||||
case 1:
|
||||
dram_size = 256 * 1024 * 1024 ;
|
||||
mtsdram(DDR0_06, 0x0102C812); // 256MB RAM
|
||||
mtsdram(DDR0_11, 0x0014C800); // 256MB RAM
|
||||
mtsdram(DDR0_43, 0x030A0200); // 256MB RAM
|
||||
mtsdram(DDR0_06, 0x0102C812); /* 256MB RAM */
|
||||
mtsdram(DDR0_11, 0x0014C800); /* 256MB RAM */
|
||||
mtsdram(DDR0_43, 0x030A0200); /* 256MB RAM */
|
||||
break;
|
||||
default:
|
||||
sdram_panic(INVALID_HW_CONFIG);
|
||||
|
|
@ -245,8 +246,10 @@ long int initdram (int board_type)
|
|||
}
|
||||
dram_size -= 16 * 1024 * 1024;
|
||||
mtsdram(DDR0_07, 0x00090100);
|
||||
// TCPD=200 cycles of clock input is required to lock the DLL.
|
||||
// CKE must be HIGH the entire time.mtsdram(DDR0_08, 0x02C80001);
|
||||
/*
|
||||
* TCPD=200 cycles of clock input is required to lock the DLL.
|
||||
* CKE must be HIGH the entire time.mtsdram(DDR0_08, 0x02C80001);
|
||||
*/
|
||||
mtsdram(DDR0_08, 0x02C80001);
|
||||
mtsdram(DDR0_09, 0x00011D5F);
|
||||
mtsdram(DDR0_10, 0x00000100);
|
||||
|
|
|
|||
|
|
@ -312,8 +312,6 @@
|
|||
#define CONFIG_PORT_ADDR 0xF0000500
|
||||
|
||||
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*----------------------------------------------------------------------*/
|
||||
|
|
@ -333,7 +331,7 @@
|
|||
|
||||
#define CFG_HUSH_PARSER /* use "hush" command parser */
|
||||
#ifdef CFG_HUSH_PARSER
|
||||
#define CFG_PROMPT_HUSH_PS2 "> "
|
||||
#define CFG_PROMPT_HUSH_PS2 "> "
|
||||
#endif
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
|
|
|
|||
|
|
@ -236,8 +236,6 @@
|
|||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_ISO_PARTITION
|
||||
|
||||
// CFG_CMD_FLASH |
|
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
|
||||
CFG_CMD_ASKENV | \
|
||||
CFG_CMD_BSP | \
|
||||
|
|
@ -301,7 +299,6 @@
|
|||
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
|
||||
|
||||
/* Board-specific PCI */
|
||||
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
|
||||
#define CFG_PCI_TARGET_INIT
|
||||
#define CFG_PCI_MASTER_INIT
|
||||
|
||||
|
|
@ -389,4 +386,3 @@
|
|||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
||||
#endif
|
||||
#endif /* __CONFIG_H */
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue