Add support for INKA4X0 board
This commit is contained in:
parent
45ea3fca4a
commit
138ff60c1e
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@ -2,6 +2,8 @@
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Changes since U-Boot 1.1.1:
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Changes since U-Boot 1.1.1:
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======================================================================
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======================================================================
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* Add support for INKA4X0 board
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* Patch by Steven Scholz, 12 Dec 2004:
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* Patch by Steven Scholz, 12 Dec 2004:
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Fix typo in AT91 memory setup.
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Fix typo in AT91 memory setup.
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3
Makefile
3
Makefile
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@ -258,6 +258,9 @@ icecube_5100_config: unconfig
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}
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}
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@./mkconfig -a IceCube ppc mpc5xxx icecube
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@./mkconfig -a IceCube ppc mpc5xxx icecube
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inka4x0_config: unconfig
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@./mkconfig inka4x0 ppc mpc5xxx inka4x0
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PM520_config \
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PM520_config \
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PM520_DDR_config \
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PM520_DDR_config \
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PM520_ROMBOOT_config \
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PM520_ROMBOOT_config \
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@ -0,0 +1,46 @@
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#
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# (C) Copyright 2003-2004
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = lib$(BOARD).a
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OBJS := $(BOARD).o flash.o
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$(LIB): $(OBJS) $(SOBJS)
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$(AR) crv $@ $(OBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
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$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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-include .depend
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#########################################################################
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@ -0,0 +1,41 @@
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#
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# (C) Copyright 2004
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# INKA 4X0 board:
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#
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# Valid values for TEXT_BASE are:
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#
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# 0xFFE00000 boot low
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#
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# 0x00100000 boot from RAM (for testing only)
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#
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ifndef TEXT_BASE
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## Standard: boot low
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TEXT_BASE = 0xFFE00000
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## For testing: boot from RAM
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#TEXT_BASE = 0x00100000
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endif
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PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
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@ -0,0 +1,432 @@
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/*
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* (C) Copyright 2003-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2004
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* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
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/*
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* CPU to flash interface is 8-bit, so make declaration accordingly
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*/
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typedef unsigned char FLASH_PORT_WIDTH;
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typedef volatile unsigned char FLASH_PORT_WIDTHV;
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#define FPW FLASH_PORT_WIDTH
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#define FPWV FLASH_PORT_WIDTHV
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#define FLASH_CYCLE1 0x0555
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#define FLASH_CYCLE2 0x02aa
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/*-----------------------------------------------------------------------
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* Functions
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*/
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static ulong flash_get_size(FPWV *addr, flash_info_t *info);
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static void flash_reset(flash_info_t *info);
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static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
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static flash_info_t *flash_get_info(ulong base);
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/*-----------------------------------------------------------------------
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* flash_init()
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*
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* sets up flash_info and returns size of FLASH (bytes)
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*/
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unsigned long flash_init (void)
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{
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unsigned long size = 0;
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extern void flash_preinit(void);
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ulong flashbase = CFG_FLASH_BASE;
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flash_preinit();
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/* Init: no FLASHes known */
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memset(&flash_info[0], 0, sizeof(flash_info_t));
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flash_info[0].size =
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flash_get_size((FPW *)flashbase, &flash_info[0]);
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size = flash_info[0].size;
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#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
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/* monitor protection ON by default */
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flash_protect(FLAG_PROTECT_SET,
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CFG_MONITOR_BASE,
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CFG_MONITOR_BASE+monitor_flash_len-1,
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flash_get_info(CFG_MONITOR_BASE));
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#endif
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#ifdef CFG_ENV_IS_IN_FLASH
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/* ENV protection ON by default */
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flash_protect(FLAG_PROTECT_SET,
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CFG_ENV_ADDR,
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CFG_ENV_ADDR+CFG_ENV_SIZE-1,
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flash_get_info(CFG_ENV_ADDR));
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#endif
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return size ? size : 1;
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}
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/*-----------------------------------------------------------------------
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*/
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static void flash_reset(flash_info_t *info)
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{
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FPWV *base = (FPWV *)(info->start[0]);
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/* Put FLASH back in read mode */
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if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
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*base = (FPW)0x00FF00FF; /* Intel Read Mode */
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else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
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*base = (FPW)0x00F000F0; /* AMD Read Mode */
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}
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/*-----------------------------------------------------------------------
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*/
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static flash_info_t *flash_get_info(ulong base)
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{
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int i;
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flash_info_t * info;
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for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
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info = & flash_info[i];
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if (info->size && info->start[0] <= base &&
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base <= info->start[0] + info->size - 1)
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break;
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}
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return i == CFG_MAX_FLASH_BANKS ? 0 : info;
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}
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/*-----------------------------------------------------------------------
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*/
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void flash_print_info (flash_info_t *info)
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{
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int i;
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if (info->flash_id == FLASH_UNKNOWN) {
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printf ("missing or unknown FLASH type\n");
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return;
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}
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switch (info->flash_id & FLASH_VENDMASK) {
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case FLASH_MAN_AMD: printf ("AMD "); break;
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case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
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case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
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case FLASH_MAN_SST: printf ("SST "); break;
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case FLASH_MAN_STM: printf ("STM "); break;
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case FLASH_MAN_INTEL: printf ("INTEL "); break;
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default: printf ("Unknown Vendor "); break;
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}
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switch (info->flash_id & FLASH_TYPEMASK) {
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case FLASH_AM116DB:
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printf ("AM29LV116DB (16Mbit, bottom boot sect)\n");
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break;
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case FLASH_AMLV128U:
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printf ("AM29LV128ML (128Mbit, uniform sector size)\n");
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break;
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case FLASH_AM160B:
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printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
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break;
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default:
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printf ("Unknown Chip Type\n");
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break;
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}
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printf (" Size: %ld MB in %d Sectors\n",
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info->size >> 20,
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info->sector_count);
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printf (" Sector Start Addresses:");
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for (i=0; i<info->sector_count; ++i) {
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if ((i % 5) == 0) {
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printf ("\n ");
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}
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printf (" %08lX%s",
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info->start[i],
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info->protect[i] ? " (RO)" : " ");
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}
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printf ("\n");
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return;
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}
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/*-----------------------------------------------------------------------
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*/
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/*
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* The following code cannot be run from FLASH!
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*/
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ulong flash_get_size (FPWV *addr, flash_info_t *info)
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{
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int i;
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ulong base = (ulong)addr;
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/* Write auto select command: read Manufacturer ID */
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/* Write auto select command sequence and test FLASH answer */
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addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */
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addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */
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addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */
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/* The manufacturer codes are only 1 byte, so just use 1 byte.
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* This works for any bus width and any FLASH device width.
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*/
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udelay(100);
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switch (addr[0] & 0xff) {
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case (uchar)AMD_MANUFACT:
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debug ("Manufacturer: AMD (Spansion)\n");
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info->flash_id = FLASH_MAN_AMD;
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break;
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case (uchar)INTEL_MANUFACT:
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debug ("Manufacturer: Intel (not supported yet)\n");
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info->flash_id = FLASH_MAN_INTEL;
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break;
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default:
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info->flash_id = FLASH_UNKNOWN;
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info->sector_count = 0;
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info->size = 0;
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break;
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}
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/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
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if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[1]) {
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case (uchar)AMD_ID_LV116DB:
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debug ("Chip: AM29LV116DB\n");
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info->flash_id += FLASH_AM116DB;
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info->sector_count = 35;
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info->size = 0x00200000;
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/*
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* The first 4 sectors are 16 kB, 8 kB, 8 kB and 32 kB, all
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* the other ones are 64 kB
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*/
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info->start[0] = base + 0x00000000;
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info->start[1] = base + 0x00004000;
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info->start[2] = base + 0x00006000;
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info->start[3] = base + 0x00008000;
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for( i = 4; i < info->sector_count; i++ )
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info->start[i] =
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base + (i * (64 << 10)) - 0x00030000;
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break; /* => 2 MB */
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case (FPW)AMD_ID_LV160B:
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debug ("Chip: AM29LV160MB\n");
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info->flash_id += FLASH_AM160B;
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info->sector_count = 35;
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info->size = 0x00400000;
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/*
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* The first 4 sectors are 16 kB, 8 kB, 8 kB and 32 kB, all
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* the other ones are 64 kB
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*/
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info->start[0] = base + 0x00000000;
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info->start[1] = base + 0x00008000;
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info->start[2] = base + 0x0000C000;
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info->start[3] = base + 0x00010000;
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for( i = 4; i < info->sector_count; i++ )
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info->start[i] =
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base + (i * 2 * (64 << 10)) - 0x00060000;
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break; /* => 4 MB */
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default:
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||||||
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info->flash_id = FLASH_UNKNOWN;
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||||||
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info->sector_count = 0;
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||||||
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info->size = 0;
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||||||
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}
|
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|
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/* Put FLASH back in read mode */
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flash_reset(info);
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return (info->size);
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||||||
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}
|
||||||
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||||||
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/*-----------------------------------------------------------------------
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||||||
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*/
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||||||
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|
||||||
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int flash_erase (flash_info_t *info, int s_first, int s_last)
|
||||||
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{
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||||||
|
FPWV *addr = (FPWV*)(info->start[0]);
|
||||||
|
int flag, prot, sect, l_sect;
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||||||
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ulong start, now, last;
|
||||||
|
|
||||||
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debug ("flash_erase: first: %d last: %d\n", s_first, s_last);
|
||||||
|
|
||||||
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if ((s_first < 0) || (s_first > s_last)) {
|
||||||
|
if (info->flash_id == FLASH_UNKNOWN) {
|
||||||
|
printf ("- missing\n");
|
||||||
|
} else {
|
||||||
|
printf ("- no sectors to erase\n");
|
||||||
|
}
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
if ((info->flash_id == FLASH_UNKNOWN) ||
|
||||||
|
(info->flash_id > FLASH_AMD_COMP)) {
|
||||||
|
printf ("Can't erase unknown flash type %08lx - aborted\n",
|
||||||
|
info->flash_id);
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
prot = 0;
|
||||||
|
for (sect=s_first; sect<=s_last; ++sect) {
|
||||||
|
if (info->protect[sect]) {
|
||||||
|
prot++;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (prot) {
|
||||||
|
printf ("- Warning: %d protected sectors will not be erased!\n",
|
||||||
|
prot);
|
||||||
|
} else {
|
||||||
|
printf ("\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
l_sect = -1;
|
||||||
|
|
||||||
|
/* Disable interrupts which might cause a timeout here */
|
||||||
|
flag = disable_interrupts();
|
||||||
|
|
||||||
|
addr[0x0555] = (FPW)0x00AA00AA;
|
||||||
|
addr[0x02AA] = (FPW)0x00550055;
|
||||||
|
addr[0x0555] = (FPW)0x00800080;
|
||||||
|
addr[0x0555] = (FPW)0x00AA00AA;
|
||||||
|
addr[0x02AA] = (FPW)0x00550055;
|
||||||
|
|
||||||
|
/* Start erase on unprotected sectors */
|
||||||
|
for (sect = s_first; sect<=s_last; sect++) {
|
||||||
|
if (info->protect[sect] == 0) { /* not protected */
|
||||||
|
addr = (FPWV*)(info->start[sect]);
|
||||||
|
addr[0] = (FPW)0x00300030;
|
||||||
|
l_sect = sect;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* re-enable interrupts if necessary */
|
||||||
|
if (flag)
|
||||||
|
enable_interrupts();
|
||||||
|
|
||||||
|
/* wait at least 80us - let's wait 1 ms */
|
||||||
|
udelay (1000);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* We wait for the last triggered sector
|
||||||
|
*/
|
||||||
|
if (l_sect < 0)
|
||||||
|
goto DONE;
|
||||||
|
|
||||||
|
start = get_timer (0);
|
||||||
|
last = start;
|
||||||
|
addr = (FPWV*)(info->start[l_sect]);
|
||||||
|
while ((addr[0] & (FPW)0x00800080) != (FPW)0x00800080) {
|
||||||
|
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
|
||||||
|
printf ("Timeout\n");
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
/* show that we're waiting */
|
||||||
|
if ((now - last) > 1000) { /* every second */
|
||||||
|
putc ('.');
|
||||||
|
last = now;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
DONE:
|
||||||
|
/* reset to read mode */
|
||||||
|
addr = (FPWV*)info->start[0];
|
||||||
|
addr[0] = (FPW)0x00F000F0; /* reset bank */
|
||||||
|
|
||||||
|
printf (" done\n");
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* Copy memory to flash, returns:
|
||||||
|
* 0 - OK
|
||||||
|
* 1 - write timeout
|
||||||
|
* 2 - Flash not erased
|
||||||
|
*/
|
||||||
|
|
||||||
|
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
|
||||||
|
{
|
||||||
|
int i, rc = 0;
|
||||||
|
|
||||||
|
for (i = 0; i < cnt; i++)
|
||||||
|
if ((rc = write_word_amd(info, (FPW *)(addr+i), src[i])) != 0) {
|
||||||
|
return (rc);
|
||||||
|
}
|
||||||
|
|
||||||
|
return rc;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* Write a word to Flash for AMD FLASH
|
||||||
|
* A word is 16 or 32 bits, whichever the bus width of the flash bank
|
||||||
|
* (not an individual chip) is.
|
||||||
|
*
|
||||||
|
* returns:
|
||||||
|
* 0 - OK
|
||||||
|
* 1 - write timeout
|
||||||
|
* 2 - Flash not erased
|
||||||
|
*/
|
||||||
|
static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
|
||||||
|
{
|
||||||
|
ulong start;
|
||||||
|
int flag;
|
||||||
|
FPWV *base; /* first address in flash bank */
|
||||||
|
|
||||||
|
/* Check if Flash is (sufficiently) erased */
|
||||||
|
if ((*dest & data) != data) {
|
||||||
|
return (2);
|
||||||
|
}
|
||||||
|
|
||||||
|
base = (FPWV *)(info->start[0]);
|
||||||
|
|
||||||
|
/* Disable interrupts which might cause a timeout here */
|
||||||
|
flag = disable_interrupts();
|
||||||
|
|
||||||
|
base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
|
||||||
|
base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
|
||||||
|
base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */
|
||||||
|
|
||||||
|
*dest = data; /* start programming the data */
|
||||||
|
|
||||||
|
/* re-enable interrupts if necessary */
|
||||||
|
if (flag)
|
||||||
|
enable_interrupts();
|
||||||
|
|
||||||
|
start = get_timer (0);
|
||||||
|
|
||||||
|
/* data polling for D7 */
|
||||||
|
while ((*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
|
||||||
|
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
|
||||||
|
*dest = (FPW)0x00F000F0; /* reset bank */
|
||||||
|
return (1);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return (0);
|
||||||
|
}
|
|
@ -0,0 +1,179 @@
|
||||||
|
/*
|
||||||
|
* (C) Copyright 2003-2004
|
||||||
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
|
*
|
||||||
|
* (C) Copyright 2004
|
||||||
|
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
|
||||||
|
*
|
||||||
|
* (C) Copyright 2004
|
||||||
|
* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
#include <mpc5xxx.h>
|
||||||
|
#include <pci.h>
|
||||||
|
|
||||||
|
#if defined(CONFIG_MPC5200_DDR)
|
||||||
|
#include "mt46v16m16-75.h"
|
||||||
|
#else
|
||||||
|
#include "mt48lc16m16a2-75.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef CFG_RAMBOOT
|
||||||
|
static void sdram_start (int hi_addr)
|
||||||
|
{
|
||||||
|
long hi_addr_bit = hi_addr ? 0x01000000 : 0;
|
||||||
|
|
||||||
|
/* unlock mode register */
|
||||||
|
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
|
||||||
|
hi_addr_bit;
|
||||||
|
__asm__ volatile ("sync");
|
||||||
|
|
||||||
|
/* precharge all banks */
|
||||||
|
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
|
||||||
|
hi_addr_bit;
|
||||||
|
__asm__ volatile ("sync");
|
||||||
|
|
||||||
|
#if SDRAM_DDR
|
||||||
|
/* set mode register: extended mode */
|
||||||
|
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
|
||||||
|
__asm__ volatile ("sync");
|
||||||
|
|
||||||
|
/* set mode register: reset DLL */
|
||||||
|
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
|
||||||
|
__asm__ volatile ("sync");
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* precharge all banks */
|
||||||
|
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
|
||||||
|
hi_addr_bit;
|
||||||
|
__asm__ volatile ("sync");
|
||||||
|
|
||||||
|
/* auto refresh */
|
||||||
|
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
|
||||||
|
hi_addr_bit;
|
||||||
|
__asm__ volatile ("sync");
|
||||||
|
|
||||||
|
/* set mode register */
|
||||||
|
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
|
||||||
|
__asm__ volatile ("sync");
|
||||||
|
|
||||||
|
/* normal operation */
|
||||||
|
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
|
||||||
|
__asm__ volatile ("sync");
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* ATTENTION: Although partially referenced initdram does NOT make real use
|
||||||
|
* use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
|
||||||
|
* is something else than 0x00000000.
|
||||||
|
*/
|
||||||
|
|
||||||
|
long int initdram (int board_type)
|
||||||
|
{
|
||||||
|
ulong dramsize = 0;
|
||||||
|
#ifndef CFG_RAMBOOT
|
||||||
|
ulong test1, test2;
|
||||||
|
|
||||||
|
/* setup SDRAM chip selects */
|
||||||
|
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
|
||||||
|
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
|
||||||
|
__asm__ volatile ("sync");
|
||||||
|
|
||||||
|
/* setup config registers */
|
||||||
|
*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
|
||||||
|
*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
|
||||||
|
__asm__ volatile ("sync");
|
||||||
|
|
||||||
|
#if SDRAM_DDR
|
||||||
|
/* set tap delay */
|
||||||
|
*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
|
||||||
|
__asm__ volatile ("sync");
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* find RAM size using SDRAM CS0 only */
|
||||||
|
sdram_start(0);
|
||||||
|
test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
|
||||||
|
sdram_start(1);
|
||||||
|
test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
|
||||||
|
if (test1 > test2) {
|
||||||
|
sdram_start(0);
|
||||||
|
dramsize = test1;
|
||||||
|
} else {
|
||||||
|
dramsize = test2;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* memory smaller than 1MB is impossible */
|
||||||
|
if (dramsize < (1 << 20)) {
|
||||||
|
dramsize = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* set SDRAM CS0 size according to the amount of RAM found */
|
||||||
|
if (dramsize > 0) {
|
||||||
|
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
|
||||||
|
__builtin_ffs(dramsize >> 20) - 1;
|
||||||
|
} else {
|
||||||
|
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
|
||||||
|
}
|
||||||
|
|
||||||
|
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
|
||||||
|
#else /* CFG_RAMBOOT */
|
||||||
|
|
||||||
|
/* retrieve size of memory connected to SDRAM CS0 */
|
||||||
|
dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
|
||||||
|
if (dramsize >= 0x13) {
|
||||||
|
dramsize = (1 << (dramsize - 0x13)) << 20;
|
||||||
|
} else {
|
||||||
|
dramsize = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* retrieve size of memory connected to SDRAM CS1 */
|
||||||
|
dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
|
||||||
|
if (dramsize2 >= 0x13) {
|
||||||
|
dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
|
||||||
|
} else {
|
||||||
|
dramsize2 = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* CFG_RAMBOOT */
|
||||||
|
|
||||||
|
/* return dramsize + dramsize2; */
|
||||||
|
return dramsize;
|
||||||
|
}
|
||||||
|
|
||||||
|
int checkboard (void)
|
||||||
|
{
|
||||||
|
puts ("Board: INKA 4X0 (Indatec GmbH & Co. KG)\n");
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
void flash_preinit(void)
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
* Now, when we are in RAM, enable flash write
|
||||||
|
* access for detection process.
|
||||||
|
* Note that CS_BOOT cannot be cleared when
|
||||||
|
* executing in flash.
|
||||||
|
*/
|
||||||
|
*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
|
||||||
|
}
|
||||||
|
|
|
@ -0,0 +1,37 @@
|
||||||
|
/*
|
||||||
|
* (C) Copyright 2004
|
||||||
|
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SDRAM_DDR 1 /* is DDR */
|
||||||
|
|
||||||
|
#if defined(CONFIG_MPC5200)
|
||||||
|
/* Settings for XLB = 132 MHz */
|
||||||
|
#define SDRAM_MODE 0x018D0000
|
||||||
|
#define SDRAM_EMODE 0x40090000
|
||||||
|
#define SDRAM_CONTROL 0x714f0f00
|
||||||
|
#define SDRAM_CONFIG1 0x73722930
|
||||||
|
#define SDRAM_CONFIG2 0x47770000
|
||||||
|
#define SDRAM_TAPDELAY 0x10000000
|
||||||
|
|
||||||
|
#else
|
||||||
|
#error CONFIG_MPC5200 not defined
|
||||||
|
#endif
|
|
@ -0,0 +1,47 @@
|
||||||
|
/*
|
||||||
|
* (C) Copyright 2004
|
||||||
|
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SDRAM_DDR 1 /* is SDR */
|
||||||
|
|
||||||
|
#if defined(CONFIG_MPC5200)
|
||||||
|
/* Settings for XLB = 132 MHz */
|
||||||
|
#define SDRAM_MODE 0x00CD0000
|
||||||
|
/* #define SDRAM_MODE 0x008D0000 */ /* CAS latency 2 */
|
||||||
|
#define SDRAM_CONTROL 0x504F0000
|
||||||
|
#define SDRAM_CONFIG1 0xD2322800
|
||||||
|
/* #define SDRAM_CONFIG1 0xD2222800 */ /* CAS latency 2 */
|
||||||
|
/*#define SDRAM_CONFIG1 0xD7322800 */ /* SDRAM controller bug workaround */
|
||||||
|
#define SDRAM_CONFIG2 0x8AD70000
|
||||||
|
/*#define SDRAM_CONFIG2 0xDDD70000 */ /* SDRAM controller bug workaround */
|
||||||
|
|
||||||
|
#elif defined(CONFIG_MGT5100)
|
||||||
|
/* Settings for XLB = 66 MHz */
|
||||||
|
#define SDRAM_MODE 0x008D0000
|
||||||
|
#define SDRAM_CONTROL 0x504F0000
|
||||||
|
#define SDRAM_CONFIG1 0xC2222600
|
||||||
|
#define SDRAM_CONFIG2 0x88B70004
|
||||||
|
#define SDRAM_ADDRSEL 0x02000000
|
||||||
|
|
||||||
|
#else
|
||||||
|
#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
|
||||||
|
#endif
|
|
@ -0,0 +1,133 @@
|
||||||
|
/*
|
||||||
|
* (C) Copyright 2003-2004
|
||||||
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
OUTPUT_ARCH(powerpc)
|
||||||
|
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||||
|
/* Do we need any of these for elf?
|
||||||
|
__DYNAMIC = 0; */
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* Read-only sections, merged into text segment: */
|
||||||
|
. = + SIZEOF_HEADERS;
|
||||||
|
.interp : { *(.interp) }
|
||||||
|
.hash : { *(.hash) }
|
||||||
|
.dynsym : { *(.dynsym) }
|
||||||
|
.dynstr : { *(.dynstr) }
|
||||||
|
.rel.text : { *(.rel.text) }
|
||||||
|
.rela.text : { *(.rela.text) }
|
||||||
|
.rel.data : { *(.rel.data) }
|
||||||
|
.rela.data : { *(.rela.data) }
|
||||||
|
.rel.rodata : { *(.rel.rodata) }
|
||||||
|
.rela.rodata : { *(.rela.rodata) }
|
||||||
|
.rel.got : { *(.rel.got) }
|
||||||
|
.rela.got : { *(.rela.got) }
|
||||||
|
.rel.ctors : { *(.rel.ctors) }
|
||||||
|
.rela.ctors : { *(.rela.ctors) }
|
||||||
|
.rel.dtors : { *(.rel.dtors) }
|
||||||
|
.rela.dtors : { *(.rela.dtors) }
|
||||||
|
.rel.bss : { *(.rel.bss) }
|
||||||
|
.rela.bss : { *(.rela.bss) }
|
||||||
|
.rel.plt : { *(.rel.plt) }
|
||||||
|
.rela.plt : { *(.rela.plt) }
|
||||||
|
.init : { *(.init) }
|
||||||
|
.plt : { *(.plt) }
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
/* WARNING - the following is hand-optimized to fit within */
|
||||||
|
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||||
|
|
||||||
|
cpu/mpc5xxx/start.o (.text)
|
||||||
|
cpu/mpc5xxx/traps.o (.text)
|
||||||
|
lib_generic/crc32.o (.text)
|
||||||
|
lib_ppc/cache.o (.text)
|
||||||
|
lib_ppc/time.o (.text)
|
||||||
|
|
||||||
|
. = DEFINED(env_offset) ? env_offset : .;
|
||||||
|
common/environment.o (.ppcenv)
|
||||||
|
|
||||||
|
*(.text)
|
||||||
|
*(.fixup)
|
||||||
|
*(.got1)
|
||||||
|
. = ALIGN(16);
|
||||||
|
*(.rodata)
|
||||||
|
*(.rodata1)
|
||||||
|
*(.rodata.str1.4)
|
||||||
|
}
|
||||||
|
.fini : { *(.fini) } =0
|
||||||
|
.ctors : { *(.ctors) }
|
||||||
|
.dtors : { *(.dtors) }
|
||||||
|
|
||||||
|
/* Read-write section, merged into data segment: */
|
||||||
|
. = (. + 0x0FFF) & 0xFFFFF000;
|
||||||
|
_erotext = .;
|
||||||
|
PROVIDE (erotext = .);
|
||||||
|
.reloc :
|
||||||
|
{
|
||||||
|
*(.got)
|
||||||
|
_GOT2_TABLE_ = .;
|
||||||
|
*(.got2)
|
||||||
|
_FIXUP_TABLE_ = .;
|
||||||
|
*(.fixup)
|
||||||
|
}
|
||||||
|
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
|
||||||
|
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
|
||||||
|
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
*(.data)
|
||||||
|
*(.data1)
|
||||||
|
*(.sdata)
|
||||||
|
*(.sdata2)
|
||||||
|
*(.dynamic)
|
||||||
|
CONSTRUCTORS
|
||||||
|
}
|
||||||
|
_edata = .;
|
||||||
|
PROVIDE (edata = .);
|
||||||
|
|
||||||
|
__u_boot_cmd_start = .;
|
||||||
|
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||||
|
__u_boot_cmd_end = .;
|
||||||
|
|
||||||
|
|
||||||
|
__start___ex_table = .;
|
||||||
|
__ex_table : { *(__ex_table) }
|
||||||
|
__stop___ex_table = .;
|
||||||
|
|
||||||
|
. = ALIGN(4096);
|
||||||
|
__init_begin = .;
|
||||||
|
.text.init : { *(.text.init) }
|
||||||
|
.data.init : { *(.data.init) }
|
||||||
|
. = ALIGN(4096);
|
||||||
|
__init_end = .;
|
||||||
|
|
||||||
|
__bss_start = .;
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
*(.sbss) *(.scommon)
|
||||||
|
*(.dynbss)
|
||||||
|
*(.bss)
|
||||||
|
*(COMMON)
|
||||||
|
}
|
||||||
|
_end = . ;
|
||||||
|
PROVIDE (end = .);
|
||||||
|
}
|
|
@ -870,7 +870,8 @@ int mpc5xxx_fec_initialize(bd_t * bis)
|
||||||
fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
|
fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
|
||||||
fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
|
fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
|
||||||
#if defined(CONFIG_ICECUBE) || defined(CONFIG_PM520) || \
|
#if defined(CONFIG_ICECUBE) || defined(CONFIG_PM520) || \
|
||||||
defined(CONFIG_TOP5200) || defined(CONFIG_TQM5200)
|
defined(CONFIG_TOP5200) || defined(CONFIG_TQM5200) || \
|
||||||
|
defined(CONFIG_INKA4X0)
|
||||||
# ifndef CONFIG_FEC_10MBIT
|
# ifndef CONFIG_FEC_10MBIT
|
||||||
fec->xcv_type = MII100;
|
fec->xcv_type = MII100;
|
||||||
# else
|
# else
|
||||||
|
|
|
@ -0,0 +1,244 @@
|
||||||
|
/*
|
||||||
|
* (C) Copyright 2003-2004
|
||||||
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CONFIG_H
|
||||||
|
#define __CONFIG_H
|
||||||
|
|
||||||
|
/*
|
||||||
|
* High Level Configuration Options
|
||||||
|
* (easy to change)
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
|
||||||
|
#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
|
||||||
|
#define CONFIG_INKA4X0 1 /* INKA4x0 board */
|
||||||
|
|
||||||
|
#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
|
||||||
|
|
||||||
|
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||||
|
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||||
|
|
||||||
|
#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
|
||||||
|
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||||
|
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Serial console configuration
|
||||||
|
*/
|
||||||
|
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
|
||||||
|
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
|
||||||
|
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Supported commands
|
||||||
|
*/
|
||||||
|
#define CONFIG_COMMANDS (CONFIG_CMD_DFL)
|
||||||
|
|
||||||
|
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||||
|
#include <cmd_confdefs.h>
|
||||||
|
|
||||||
|
#if (TEXT_BASE == 0xFFE00000) /* Boot low */
|
||||||
|
# define CFG_LOWBOOT 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Autobooting
|
||||||
|
*/
|
||||||
|
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||||
|
|
||||||
|
#define CONFIG_PREBOOT "echo;" \
|
||||||
|
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
|
||||||
|
"echo"
|
||||||
|
|
||||||
|
#undef CONFIG_BOOTARGS
|
||||||
|
|
||||||
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||||
|
"netdev=eth0\0" \
|
||||||
|
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||||
|
"nfsroot=$(serverip):$(rootpath)\0" \
|
||||||
|
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||||
|
"addip=setenv bootargs $(bootargs) " \
|
||||||
|
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
|
||||||
|
":$(hostname):$(netdev):off panic=1\0" \
|
||||||
|
"flash_nfs=run nfsargs addip;" \
|
||||||
|
"bootm $(kernel_addr)\0" \
|
||||||
|
"flash_self=run ramargs addip;" \
|
||||||
|
"bootm $(kernel_addr) $(ramdisk_addr)\0" \
|
||||||
|
"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
|
||||||
|
"rootpath=/opt/eldk3.0_ppc/ppc_82xx\0" \
|
||||||
|
"bootfile=uImage\0" \
|
||||||
|
"serverip=192.168.1.1\0" \
|
||||||
|
"ipaddr=192.168.160.2\0" \
|
||||||
|
"ethaddr=00:00:1A:1B:CE:AF\0" \
|
||||||
|
"dk=tftp 100000 inka4x0/u-boot.dk;protect off all;erase ffe00000 ffe2ffff;cp.b 100000 ffe00000 $(filesize)\0" \
|
||||||
|
""
|
||||||
|
|
||||||
|
#define CONFIG_BOOTCOMMAND "run net_nfs"
|
||||||
|
|
||||||
|
/*
|
||||||
|
* IPB Bus clocking configuration.
|
||||||
|
*/
|
||||||
|
#define CFG_IPBSPEED_133 /* define for 133MHz speed */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Flash configuration
|
||||||
|
*/
|
||||||
|
#define CFG_FLASH_BASE 0xFFE00000
|
||||||
|
|
||||||
|
#define CFG_FLASH_SIZE 0x00200000 /* 2 MByte */
|
||||||
|
#define CFG_MAX_FLASH_SECT 35 /* max num of sects on one chip */
|
||||||
|
|
||||||
|
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000) /* second sector */
|
||||||
|
#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
|
||||||
|
(= chip selects) */
|
||||||
|
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
|
||||||
|
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Environment settings
|
||||||
|
*/
|
||||||
|
#define CFG_ENV_IS_IN_FLASH 1
|
||||||
|
#define CFG_ENV_SIZE 0x2000
|
||||||
|
#define CFG_ENV_SECT_SIZE 0x2000
|
||||||
|
#define CONFIG_ENV_OVERWRITE 1
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Memory map
|
||||||
|
*/
|
||||||
|
#define CFG_MBAR 0xF0000000
|
||||||
|
#define CFG_SDRAM_BASE 0x00000000
|
||||||
|
#define CFG_DEFAULT_MBAR 0x80000000
|
||||||
|
|
||||||
|
#define CONFIG_MPC5200_DDR
|
||||||
|
|
||||||
|
/* Use ON-Chip SRAM until RAM will be available */
|
||||||
|
#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
|
||||||
|
#ifdef CONFIG_POST
|
||||||
|
/* preserve space for the post_word at end of on-chip SRAM */
|
||||||
|
#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
|
||||||
|
#else
|
||||||
|
#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
|
||||||
|
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||||
|
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||||
|
|
||||||
|
#define CFG_MONITOR_BASE TEXT_BASE
|
||||||
|
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
|
||||||
|
# define CFG_RAMBOOT 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
|
||||||
|
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
||||||
|
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Ethernet configuration
|
||||||
|
*/
|
||||||
|
#define CONFIG_MPC5xxx_FEC 1
|
||||||
|
/*
|
||||||
|
* Define CONFIG_FEC_10MBIT to force FEC at 10Mb
|
||||||
|
*/
|
||||||
|
/* #define CONFIG_FEC_10MBIT 1 */
|
||||||
|
#define CONFIG_PHY_ADDR 0x00
|
||||||
|
|
||||||
|
/*
|
||||||
|
* GPIO configuration
|
||||||
|
*
|
||||||
|
* use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
|
||||||
|
* Bit 0 (mask: 0x80000000): 1
|
||||||
|
* use ALT CAN position: Bits 2-3 (mask: 0x30000000):
|
||||||
|
* 00 -> No Alternatives, I2C1 is used for onboard EEPROM
|
||||||
|
* 01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
|
||||||
|
* EEPROM
|
||||||
|
* use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
|
||||||
|
* use PSC6_1 and PSC6_3 as GPIO: Bits 9:11 (mask: 0x07000000):
|
||||||
|
* 011 -> PSC6 could not be used as UART or CODEC. IrDA still possible.
|
||||||
|
* GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
|
||||||
|
* tests.
|
||||||
|
*/
|
||||||
|
#if defined (CONFIG_MINIFAP)
|
||||||
|
#define CFG_GPS_PORT_CONFIG 0x93000004
|
||||||
|
#else
|
||||||
|
#define CFG_GPS_PORT_CONFIG 0x83000004
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* RTC configuration
|
||||||
|
*/
|
||||||
|
#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Miscellaneous configurable options
|
||||||
|
*/
|
||||||
|
#define CFG_LONGHELP /* undef to save memory */
|
||||||
|
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||||
|
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||||
|
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||||
|
#else
|
||||||
|
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||||
|
#endif
|
||||||
|
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||||
|
#define CFG_MAXARGS 16 /* max number of command args */
|
||||||
|
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||||
|
|
||||||
|
/* Enable an alternate, more extensive memory test */
|
||||||
|
#define CFG_ALT_MEMTEST
|
||||||
|
|
||||||
|
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
|
||||||
|
#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
|
||||||
|
|
||||||
|
#define CFG_LOAD_ADDR 0x100000 /* default load address */
|
||||||
|
|
||||||
|
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
|
||||||
|
* which is normally part of the default commands (CFV_CMD_DFL)
|
||||||
|
*/
|
||||||
|
#define CONFIG_LOOPW
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Various low-level settings
|
||||||
|
*/
|
||||||
|
#if defined(CONFIG_MPC5200)
|
||||||
|
#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
|
||||||
|
#define CFG_HID0_FINAL HID0_ICE
|
||||||
|
#else
|
||||||
|
#define CFG_HID0_INIT 0
|
||||||
|
#define CFG_HID0_FINAL 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define CFG_BOOTCS_START CFG_FLASH_BASE
|
||||||
|
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
|
||||||
|
#define CFG_BOOTCS_CFG 0x00087800 /* for pci_clk = 66 MHz */
|
||||||
|
#define CFG_CS0_START CFG_FLASH_BASE
|
||||||
|
#define CFG_CS0_SIZE CFG_FLASH_SIZE
|
||||||
|
|
||||||
|
#define CFG_CS_BURST 0x00000000
|
||||||
|
#define CFG_CS_DEADCYCLE 0x33333333
|
||||||
|
|
||||||
|
#endif /* __CONFIG_H */
|
|
@ -149,6 +149,7 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
|
||||||
#define AMD_ID_F016D 0xAD /* 29F016 ID ( 2 M x 8) */
|
#define AMD_ID_F016D 0xAD /* 29F016 ID ( 2 M x 8) */
|
||||||
#define AMD_ID_F032B 0x41 /* 29F032 ID ( 4 M x 8) */
|
#define AMD_ID_F032B 0x41 /* 29F032 ID ( 4 M x 8) */
|
||||||
#define AMD_ID_LV116DT 0xC7 /* 29LV116DT ( 2 M x 8, top boot sect) */
|
#define AMD_ID_LV116DT 0xC7 /* 29LV116DT ( 2 M x 8, top boot sect) */
|
||||||
|
#define AMD_ID_LV116DB 0x4C /* 29LV116DB ( 2 M x 8, bottom boot sect) */
|
||||||
#define AMD_ID_LV016B 0xc8 /* 29LV016 ID ( 2 M x 8) */
|
#define AMD_ID_LV016B 0xc8 /* 29LV016 ID ( 2 M x 8) */
|
||||||
|
|
||||||
#define AMD_ID_PL160CB 0x22452245 /* 29PL160CB ID (16 M, bottom boot sect */
|
#define AMD_ID_PL160CB 0x22452245 /* 29PL160CB ID (16 M, bottom boot sect */
|
||||||
|
@ -284,6 +285,7 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
|
||||||
#define FLASH_AM800T 0x0004 /* AMD AM29LV800 */
|
#define FLASH_AM800T 0x0004 /* AMD AM29LV800 */
|
||||||
#define FLASH_AM800B 0x0005
|
#define FLASH_AM800B 0x0005
|
||||||
#define FLASH_AM116DT 0x0026 /* AMD AM29LV116DT (2Mx8bit) */
|
#define FLASH_AM116DT 0x0026 /* AMD AM29LV116DT (2Mx8bit) */
|
||||||
|
#define FLASH_AM116DB 0x0027 /* AMD AM29LV116DB (2Mx8bit) */
|
||||||
#define FLASH_AM160T 0x0006 /* AMD AM29LV160 */
|
#define FLASH_AM160T 0x0006 /* AMD AM29LV160 */
|
||||||
#define FLASH_AM160LV 0x0046 /* AMD29LV160DB (2M = 2Mx8bit ) */
|
#define FLASH_AM160LV 0x0046 /* AMD29LV160DB (2M = 2Mx8bit ) */
|
||||||
#define FLASH_AM160B 0x0007
|
#define FLASH_AM160B 0x0007
|
||||||
|
|
Loading…
Reference in New Issue