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Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx

This commit is contained in:
Wolfgang Denk 2008-10-21 21:19:35 +02:00
parent 055b12f2ff f4d14c5550
commit 06c2942218
23 changed files with 1369 additions and 331 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
MAINTAINERS
View File

@ -130,6 +130,10 @@ Jon Diekema <jon.diekema@smiths-aerospace.com>
sbc8260 MPC8260
Dirk Eibach <eibach@gdsys.de>
neo PPC405EP
Dave Ellis <DGE@sixnetio.com>
SXNI855T MPC8xx

2
MAKEALL
View File

@ -161,6 +161,7 @@ LIST_4xx=" \
alpr \
AP1000 \
AR405 \
arches \
ASH405 \
bamboo \
bamboo_nand \
@ -210,6 +211,7 @@ LIST_4xx=" \
ml300 \
ml507 \
ml507_flash \
neo \
ocotea \
OCRTC \
ORSG \

6
Makefile
View File

@ -1208,7 +1208,8 @@ bubinga_config: unconfig
CANBT_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx canbt esd
# Canyonlands & Glacier use different U-Boot images
# Arches, Canyonlands & Glacier use different U-Boot images
arches_config \
canyonlands_config \
glacier_config: unconfig
@mkdir -p $(obj)include
@ -1384,6 +1385,9 @@ ml507_config: unconfig
>> $(obj)board/xilinx/ml507/config.tmp
@$(MKCONFIG) ml507 ppc ppc4xx ml507 xilinx
neo_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx neo gdsys
ocotea_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx ocotea amcc

12
board/amcc/canyonlands/bootstrap.c
View File

@ -40,6 +40,8 @@
static char *config_labels[] = {
"CPU: 600 PLB: 200 OPB: 100 EBC: 100",
"CPU: 800 PLB: 200 OPB: 100 EBC: 100",
"CPU:1000 PLB: 200 OPB: 100 EBC: 100",
"CPU:1066 PLB: 266 OPB: 88 EBC: 88",
NULL
};
@ -54,6 +56,16 @@ static u8 boot_configs[][17] = {
0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0, 0x40, 0x08,
0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
(NAND_COMPATIBLE | NOR_COMPATIBLE),
0x86, 0x82, 0x96, 0x19, 0xb9, 0x80, 0x00, 0xa0, 0x40, 0x08,
0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
(NAND_COMPATIBLE | NOR_COMPATIBLE),
0x86, 0x80, 0xb3, 0x01, 0x9d, 0x80, 0x00, 0xa0, 0x40, 0x08,
0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0

140
board/amcc/canyonlands/canyonlands.c
View File

@ -38,11 +38,52 @@ DECLARE_GLOBAL_DATA_PTR;
#define BOARD_CANYONLANDS_PCIE 1
#define BOARD_CANYONLANDS_SATA 2
#define BOARD_GLACIER 3
#define BOARD_ARCHES 4
#if defined(CONFIG_ARCHES)
/*
* FPGA read/write helper macros
*/
static inline int board_fpga_read(int offset)
{
int data;
data = in_8((void *)(CONFIG_SYS_FPGA_BASE + offset));
return data;
}
static inline void board_fpga_write(int offset, int data)
{
out_8((void *)(CONFIG_SYS_FPGA_BASE + offset), data);
}
/*
* CPLD read/write helper macros
*/
static inline int board_cpld_read(int offset)
{
int data;
out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
data = in_8((void *)(CONFIG_SYS_CPLD_DATA));
return data;
}
static inline void board_cpld_write(int offset, int data)
{
out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
out_8((void *)(CONFIG_SYS_CPLD_DATA), data);
}
#endif /* defined(CONFIG_ARCHES) */
int board_early_init_f(void)
{
#if !defined(CONFIG_ARCHES)
u32 sdr0_cust0;
u32 pvr = get_pvr();
#endif
/*
* Setup the interrupt controller polarities, triggers, etc.
@ -79,6 +120,7 @@ int board_early_init_f(void)
mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic3sr, 0xffffffff); /* clear all */
#if !defined(CONFIG_ARCHES)
/* SDR Setting - enable NDFC */
mfsdr(SDR0_CUST0, sdr0_cust0);
sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
@ -88,6 +130,7 @@ int board_early_init_f(void)
SDR0_CUST0_NDFC_BAC_ENCODE(3) |
(0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
mtsdr(SDR0_CUST0, sdr0_cust0);
#endif
/*
* Configure PFC (Pin Function Control) registers
@ -98,6 +141,7 @@ int board_early_init_f(void)
/* Enable PCI host functionality in SDR0_PCI0 */
mtsdr(SDR0_PCI0, 0xe0000000);
#if !defined(CONFIG_ARCHES)
/* Enable ethernet and take out of reset */
out_8((void *)CONFIG_SYS_BCSR_BASE + 6, 0);
@ -123,10 +167,12 @@ int board_early_init_f(void)
gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
}
#endif
return 0;
}
#if !defined(CONFIG_ARCHES)
static void canyonlands_sata_init(int board_type)
{
u32 reg;
@ -147,7 +193,26 @@ static void canyonlands_sata_init(int board_type)
SDR_WRITE(SDR0_SRST1, 0x00000000);
}
}
#endif /* !defined(CONFIG_ARCHES) */
int get_cpu_num(void)
{
int cpu = NA_OR_UNKNOWN_CPU;
#if defined(CONFIG_ARCHES)
int cpu_num;
cpu_num = board_fpga_read(0x3);
/* sanity check; assume cpu numbering starts and increments from 0 */
if ((cpu_num >= 0) && (cpu_num < CONFIG_BD_NUM_CPUS))
cpu = cpu_num;
#endif
return cpu;
}
#if !defined(CONFIG_ARCHES)
int checkboard(void)
{
char *s = getenv("serial#");
@ -188,6 +253,39 @@ int checkboard(void)
return (0);
}
#else /* defined(CONFIG_ARCHES) */
int checkboard(void)
{
char *s = getenv("serial#");
printf("Board: Arches - AMCC DUAL PPC460GT Reference Design\n");
printf(" Revision %02x.%02x ",
board_fpga_read(0x0), board_fpga_read(0x1));
gd->board_type = BOARD_ARCHES;
/* Only CPU0 has access to CPLD registers */
if (get_cpu_num() == 0) {
u8 cfg_sw = board_cpld_read(0x1);
printf("(FPGA=%02x, CPLD=%02x)\n",
board_fpga_read(0x2), board_cpld_read(0x0));
printf(" Configuration Switch %d%d%d%d\n",
((cfg_sw >> 3) & 0x01),
((cfg_sw >> 2) & 0x01),
((cfg_sw >> 1) & 0x01),
((cfg_sw >> 0) & 0x01));
} else
printf("(FPGA=%02x, CPLD=xx)\n", board_fpga_read(0x2));
if (s != NULL)
printf(" Serial# %s\n", s);
return 0;
}
#endif /* !defined(CONFIG_ARCHES) */
/*
* Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
* board specific values.
@ -389,6 +487,7 @@ int board_early_init_r (void)
return 0;
}
#if !defined(CONFIG_ARCHES)
int misc_init_r(void)
{
u32 sdr0_srst1 = 0;
@ -434,6 +533,47 @@ int misc_init_r(void)
return 0;
}
#else /* defined(CONFIG_ARCHES) */
int misc_init_r(void)
{
u32 eth_cfg = 0;
u32 eth_pll;
u32 reg;
/*
* Set EMAC mode/configuration (GMII, SGMII, RGMII...).
* This is board specific, so let's do it here.
*/
/* enable SGMII mode */
eth_cfg |= (SDR0_ETH_CFG_SGMII0_ENABLE |
SDR0_ETH_CFG_SGMII1_ENABLE |
SDR0_ETH_CFG_SGMII2_ENABLE);
/* Set EMAC for MDIO */
eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0;
/* bypass the TAHOE0/TAHOE1 cores for U-Boot */
eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
mtsdr(SDR0_ETH_CFG, eth_cfg);
/* reset all SGMII interfaces */
mfsdr(SDR0_SRST1, reg);
reg |= (SDR0_SRST1_SGMII0 | SDR0_SRST1_SGMII1 | SDR0_SRST1_SGMII2);
mtsdr(SDR0_SRST1, reg);
mtsdr(SDR0_ETH_STS, 0xFFFFFFFF);
mtsdr(SDR0_SRST1, 0x00000000);
do {
mfsdr(SDR0_ETH_PLL, eth_pll);
} while (!(eth_pll & SDR0_ETH_PLL_PLLLOCK));
return 0;
}
#endif /* !defined(CONFIG_ARCHES) */
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{

17
board/amcc/canyonlands/init.S
View File

@ -77,11 +77,16 @@ tlbtab:
/* PCIe UTL register */
tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xC, AC_R|AC_W|SA_G|SA_I)
#if !defined(CONFIG_ARCHES)
/* TLB-entry for NAND */
tlbentry(CONFIG_SYS_NAND_ADDR, SZ_16M, CONFIG_SYS_NAND_ADDR, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
/* TLB-entry for CPLD */
tlbentry(CONFIG_SYS_BCSR_BASE, SZ_1K, CONFIG_SYS_BCSR_BASE, 4, AC_R|AC_W|SA_G|SA_I)
#else
/* TLB-entry for FPGA */
tlbentry(CONFIG_SYS_FPGA_BASE, SZ_16M, CONFIG_SYS_FPGA_BASE, 4, AC_R|AC_W|SA_G|SA_I)
#endif
/* TLB-entry for OCM */
tlbentry(CONFIG_SYS_OCM_BASE, SZ_16K, 0x00040000, 4, AC_R|AC_W|AC_X|SA_I)
@ -92,6 +97,18 @@ tlbtab:
/* AHB: Internal USB Peripherals (USB, SATA) */
tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
#if defined(CONFIG_RAPIDIO)
/* TLB-entries for RapidIO (SRIO) */
tlbentry(CONFIG_SYS_SRGPL0_REG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_REG_BAR,
0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_SRGPL0_CFG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_CFG_BAR,
0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_SRGPL0_MNT_BAR, SZ_16M, CONFIG_SYS_SRGPL0_MNT_BAR,
0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CONFIG_SYS_I2ODMA_BASE, SZ_1K, 0x00100000,
0x4, AC_R|AC_W|SA_G|SA_I)
#endif
tlbtab_end
#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)

51
board/gdsys/neo/Makefile Normal file
View File

@ -0,0 +1,51 @@
#
# (C) Copyright 2007
# Stefan Roese, DENX Software Engineering, sr@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o
SOBJS =
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

24
board/gdsys/neo/config.mk Normal file
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@ -0,0 +1,24 @@
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
TEXT_BASE = 0xFFFC0000

101
board/gdsys/neo/neo.c Normal file
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@ -0,0 +1,101 @@
/*
* (C) Copyright 2007-2008
* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <asm/processor.h>
#include <asm/io.h>
#define HWTYPE_CCX16 1
#define HWREV_300 3
int board_early_init_f(void)
{
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical */
mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest prio */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks
* -> ca. 15 us
*/
mtebc(epcr, 0xa8400000); /* ebc always driven */
return 0;
}
/*
* Check Board Identity:
*/
int checkboard(void)
{
char *s = getenv("serial#");
u16 val = in_le16((void *)CONFIG_FPGA_BASE + 2);
u8 unit_type;
u8 hardware_cpu_ports;
u8 hardware_con_ports;
u8 hardware_version;
printf("Board: CATCenter Neo");
if (s != NULL) {
puts(", serial# ");
puts(s);
}
puts("\n ");
unit_type = (val & 0xf000) >> 12;
hardware_cpu_ports = ((val & 0x0f00) >> 8) * 8;
hardware_con_ports = ((val & 0x00f0) >> 4) * 2;
hardware_version = val & 0x000f;
switch (unit_type) {
case HWTYPE_CCX16:
printf("CCX16-FPGA (80 UARTs)");
break;
default:
printf("UnitType %d, unsupported", unit_type);
break;
}
printf(", %d cpu ports, %d console ports,",
hardware_cpu_ports, hardware_con_ports);
switch (hardware_version) {
case HWREV_300:
printf(" HW-Ver 3.00\n");
break;
default:
printf(" HW-Ver %d, unsupported\n",
hardware_version);
break;
}
return 0;
}

132
board/gdsys/neo/u-boot.lds Normal file
View File

@ -0,0 +1,132 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
cpu/ppc4xx/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}

71
cpu/ppc4xx/44x_spd_ddr2.c
View File

@ -60,6 +60,26 @@
"SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \
} while (0)
#if defined(CONFIG_440)
/*
* This DDR2 setup code can dynamically setup the TLB entries for the DDR2
* memory region. Right now the cache should still be disabled in U-Boot
* because of the EMAC driver, that need its buffer descriptor to be located
* in non cached memory.
*
* If at some time this restriction doesn't apply anymore, just define
* CONFIG_4xx_DCACHE in the board config file and this code should setup
* everything correctly.
*/
#ifdef CONFIG_4xx_DCACHE
/* enable caching on SDRAM */
#define MY_TLB_WORD2_I_ENABLE 0
#else
/* disable caching on SDRAM */
#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE
#endif /* CONFIG_4xx_DCACHE */
#endif /* CONFIG_440 */
#if defined(CONFIG_SPD_EEPROM)
/*-----------------------------------------------------------------------------+
@ -130,22 +150,6 @@
#define NUMMEMWORDS 8
#define NUMLOOPS 64 /* memory test loops */
/*
* This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
* region. Right now the cache should still be disabled in U-Boot because of the
* EMAC driver, that need it's buffer descriptor to be located in non cached
* memory.
*
* If at some time this restriction doesn't apply anymore, just define
* CONFIG_4xx_DCACHE in the board config file and this code should setup
* everything correctly.
*/
#ifdef CONFIG_4xx_DCACHE
#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
#else
#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
#endif
/*
* Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM.
* To support such configurations, we "only" map the first 2GB via the TLB's. We
@ -2958,9 +2962,10 @@ static void test(void)
/*-----------------------------------------------------------------------------
* Function: initdram
* Description: Configures the PPC405EX(r) DDR1/DDR2 SDRAM memory
* banks. The configuration is performed using static, compile-
* Description: Configures the PPC4xx IBM DDR1/DDR2 SDRAM memory controller.
* The configuration is performed using static, compile-
* time parameters.
* Configures the PPC405EX(r) and PPC460EX/GT
*---------------------------------------------------------------------------*/
phys_size_t initdram(int board_type)
{
@ -2976,6 +2981,18 @@ phys_size_t initdram(int board_type)
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
unsigned long val;
#if defined(CONFIG_440)
mtdcr(SDRAM_R0BAS, CONFIG_SYS_SDRAM_R0BAS);
mtdcr(SDRAM_R1BAS, CONFIG_SYS_SDRAM_R1BAS);
mtdcr(SDRAM_R2BAS, CONFIG_SYS_SDRAM_R2BAS);
mtdcr(SDRAM_R3BAS, CONFIG_SYS_SDRAM_R3BAS);
mtdcr(SDRAM_PLBADDULL, CONFIG_SYS_SDRAM_PLBADDULL); /* MQ0_BAUL */
mtdcr(SDRAM_PLBADDUHB, CONFIG_SYS_SDRAM_PLBADDUHB); /* MQ0_BAUH */
mtdcr(SDRAM_CONF1LL, CONFIG_SYS_SDRAM_CONF1LL);
mtdcr(SDRAM_CONF1HB, CONFIG_SYS_SDRAM_CONF1HB);
mtdcr(SDRAM_CONFPATHB, CONFIG_SYS_SDRAM_CONFPATHB);
#endif
/* Set Memory Bank Configuration Registers */
mtsdram(SDRAM_MB0CF, CONFIG_SYS_SDRAM0_MB0CF);
@ -3069,6 +3086,14 @@ phys_size_t initdram(int board_type)
mfsdram(SDRAM_MCOPT2, val);
mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE);
#if defined(CONFIG_440)
/*
* Program TLB entries with caches enabled, for best performace
* while auto-calibrating and ECC generation
*/
program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), 0);
#endif
#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
/*------------------------------------------------------------------
@ -3082,6 +3107,16 @@ phys_size_t initdram(int board_type)
ecc_init(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20);
#endif /* defined(CONFIG_DDR_ECC) */
#if defined(CONFIG_440)
/*
* Now after initialization (auto-calibration and ECC generation)
* remove the TLB entries with caches enabled and program again with
* desired cache functionality
*/
remove_tlb(0, (CONFIG_SYS_MBYTES_SDRAM << 20));
program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), MY_TLB_WORD2_I_ENABLE);
#endif
ppc4xx_ibm_ddr2_register_dump();
#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)

19
cpu/ppc4xx/cpu.c
View File

@ -41,6 +41,18 @@ DECLARE_GLOBAL_DATA_PTR;
void board_reset(void);
/*
* To provide an interface to detect CPU number for boards that support
* more then one CPU, we implement the "weak" default functions here.
*
* Returns CPU number
*/
int __get_cpu_num(void)
{
return NA_OR_UNKNOWN_CPU;
}
int get_cpu_num(void) __attribute__((weak, alias("__get_cpu_num")));
#if defined(CONFIG_405GP) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
@ -274,8 +286,13 @@ int checkcpu (void)
#if !defined(CONFIG_IOP480)
char addstr[64] = "";
sys_info_t sys_info;
int cpu_num;
puts ("CPU: ");
cpu_num = get_cpu_num();
if (cpu_num >= 0)
printf("CPU%d: ", cpu_num);
else
puts("CPU: ");
get_sys_info(&sys_info);

45
cpu/ppc4xx/fdt.c
View File

@ -37,29 +37,40 @@ DECLARE_GLOBAL_DATA_PTR;
void __ft_board_setup(void *blob, bd_t *bd)
{
u32 val[4];
int rc;
int i;
u32 bxcr;
u32 ranges[EBC_NUM_BANKS * 4];
u32 *p = ranges;
char *ebc_path = "/plb/opb/ebc";
ft_cpu_setup(blob, bd);
/* Fixup NOR mapping */
val[0] = 0; /* chip select number */
val[1] = 0; /* always 0 */
val[2] = gd->bd->bi_flashstart;
val[3] = gd->bd->bi_flashsize;
if (fdt_path_offset(blob, "/plb/opb/ebc") >= 0) {
rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
val, sizeof(val), 1);
} else {
/*
* Some 405 PPC's have EBC as direct PLB child in the dts
*/
rc = fdt_find_and_setprop(blob, "/plb/ebc", "ranges",
val, sizeof(val), 1);
/*
* Read 4xx EBC bus bridge registers to get mappings of the
* peripheral banks into the OPB/PLB address space
*/
for (i = 0; i < EBC_NUM_BANKS; i++) {
mtdcr(ebccfga, EBC_BXCR(i));
bxcr = mfdcr(ebccfgd);
if ((bxcr & EBC_BXCR_BU_MASK) != EBC_BXCR_BU_NONE) {
*p++ = i;
*p++ = 0;
*p++ = bxcr & EBC_BXCR_BAS_MASK;
*p++ = EBC_BXCR_BANK_SIZE(bxcr);
}
}
if (rc)
printf("Unable to update property NOR mapping, err=%s\n",
/* Some 405 PPC's have EBC as direct PLB child in the dts */
if (fdt_path_offset(blob, "/plb/opb/ebc") < 0)
strcpy(ebc_path, "/plb/ebc");
rc = fdt_find_and_setprop(blob, ebc_path, "ranges", ranges,
(p - ranges) * sizeof(u32), 1);
if (rc) {
printf("Unable to update property EBC mappings, err=%s\n",
fdt_strerror(rc));
}
}
void ft_board_setup(void *blob, bd_t *bd) __attribute__((weak, alias("__ft_board_setup")));

31
include/asm-ppc/ppc4xx-ebc.h
View File

@ -35,7 +35,38 @@
#define CONFIG_EBC_PPC4xx_IBM_VER1
#endif
/*
* Define the max number of EBC banks (chip selects)
*/
#if defined(CONFIG_405CR) || defined(CONFIG_405GP) || \
defined(CONFIG_405EZ) || \
defined(CONFIG_440GP) || defined(CONFIG_440GX)
#define EBC_NUM_BANKS 8
#endif
#if defined(CONFIG_405EP)
#define EBC_NUM_BANKS 5
#endif
#if defined(CONFIG_405EX) || \
defined(CONFIG_460SX)
#define EBC_NUM_BANKS 4
#endif
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define EBC_NUM_BANKS 6
#endif
#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
#define EBC_NUM_BANKS 3
#endif
/* Bank Configuration Register */
#define EBC_BXCR(n) (n)
#define EBC_BXCR_BANK_SIZE(n) (0x100000 << (((n) & EBC_BXCR_BS_MASK) >> 17))
#define EBC_BXCR_BAS_MASK PPC_REG_VAL(11, 0xFFF)
#define EBC_BXCR_BAS_ENCODE(n) (((static_cast(u32, n)) & EBC_BXCR_BAS_MASK))
#define EBC_BXCR_BS_MASK PPC_REG_VAL(14, 0x7)

17
include/configs/amcc-common.h
View File

@ -159,6 +159,13 @@
#define CONFIG_USE_TTY ttyS0
#endif
/*
* Only very few boards have default netdev not set to eth0 (like Arches)
*/
#if !defined(CONFIG_USE_NETDEV)
#define CONFIG_USE_NETDEV eth0
#endif
/*
* Only some 4xx PPC's are equipped with an FPU
*/
@ -184,7 +191,7 @@
* General common environment variables shared on all AMCC eval boards
*/
#define CONFIG_AMCC_DEF_ENV \
"netdev=eth0\0" \
"netdev=" xstr(CONFIG_USE_NETDEV) "\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
@ -197,8 +204,10 @@
"initrd_high=30000000\0" \
"kernel_addr_r=400000\0" \
"fdt_addr_r=800000\0" \
"ramdisk_addr_r=C00000\0" \
"hostname=" xstr(CONFIG_HOSTNAME) "\0" \
"bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
"ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \
CONFIG_AMCC_DEF_ENV_ROOTPATH
/*
@ -214,6 +223,12 @@
"tftp ${fdt_addr_r} ${fdt_file}; " \
"run nfsargs addip addtty addmisc;" \
"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
"net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
"tftp ${fdt_addr_r} ${fdt_file};" \
"tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
"net_self=run net_self_load;" \
"run ramargs addip addtty addmisc;" \
"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \
"fdt_file=" xstr(CONFIG_HOSTNAME) "/" xstr(CONFIG_HOSTNAME) ".dtb\0"
/*

226
include/configs/canyonlands.h
View File

@ -27,14 +27,24 @@
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
/* This config file is used for Canyonlands (460EX) and Glacier (460GT) */
#ifndef CONFIG_CANYONLANDS
#define CONFIG_460GT 1 /* Specific PPC460GT */
#define CONFIG_HOSTNAME glacier
#else
/*
* This config file is used for Canyonlands (460EX) Glacier (460GT)
* and Arches dual (460GT)
*/
#ifdef CONFIG_CANYONLANDS
#define CONFIG_460EX 1 /* Specific PPC460EX */
#define CONFIG_HOSTNAME canyonlands
#else
#define CONFIG_460GT 1 /* Specific PPC460GT */
#ifdef CONFIG_GLACIER
#define CONFIG_HOSTNAME glacier
#else
#define CONFIG_HOSTNAME arches
#define CONFIG_USE_NETDEV eth1
#define CONFIG_BD_NUM_CPUS 2
#endif
#endif
#define CONFIG_440 1
#define CONFIG_4xx 1 /* ... PPC4xx family */
@ -73,15 +83,24 @@
#define CONFIG_SYS_PCIE_INBOUND_BASE 0x000000000ULL /* 36bit physical addr */
/* EBC stuff */
#define CONFIG_SYS_NAND_ADDR 0xE0000000
#if !defined(CONFIG_ARCHES)
#define CONFIG_SYS_BCSR_BASE 0xE1000000
#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space: 0xFF000000 */
#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* later mapped to this addr */
#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* later mapped to this addr */
#define CONFIG_SYS_FLASH_SIZE (64 << 20)
#else
#define CONFIG_SYS_FPGA_BASE 0xE1000000
#define CONFIG_SYS_CPLD_ADDR (CONFIG_SYS_FPGA_BASE + 0x00080000)
#define CONFIG_SYS_CPLD_DATA (CONFIG_SYS_FPGA_BASE + 0x00080002)
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* later mapped to this addr */
#define CONFIG_SYS_FLASH_SIZE (32 << 20)
#endif
#define CONFIG_SYS_NAND_ADDR 0xE0000000
#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space: 0xFF000000 */
#define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4
#define CONFIG_SYS_FLASH_BASE_PHYS_L 0xCC000000
#define CONFIG_SYS_FLASH_BASE_PHYS (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) | \
(u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
#define CONFIG_SYS_FLASH_SIZE (64 << 20)
#define CONFIG_SYS_FLASH_BASE_PHYS (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) | \
(u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 16k */
#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */
@ -223,6 +242,7 @@
* DDR SDRAM
*----------------------------------------------------------------------------*/
#if !defined(CONFIG_NAND_U_BOOT)
#if !defined(CONFIG_ARCHES)
/*
* NAND booting U-Boot version uses a fixed initialization, since the whole
* I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
@ -232,7 +252,70 @@
#define SPD_EEPROM_ADDRESS {0x50, 0x51} /* SPD i2c spd addresses*/
#define CONFIG_DDR_ECC 1 /* with ECC support */
#define CONFIG_DDR_RQDC_FIXED 0x80000038 /* fixed value for RQDC */
#endif
#else /* defined(CONFIG_ARCHES) */
#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */
#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */
#undef CONFIG_PPC4xx_DDR_METHOD_A
/* DDR1/2 SDRAM Device Control Register Data Values */
/* Memory Queue */
#define CONFIG_SYS_SDRAM_R0BAS 0x0000f000
#define CONFIG_SYS_SDRAM_R1BAS 0x00000000
#define CONFIG_SYS_SDRAM_R2BAS 0x00000000
#define CONFIG_SYS_SDRAM_R3BAS 0x00000000
#define CONFIG_SYS_SDRAM_PLBADDULL 0x00000000
#define CONFIG_SYS_SDRAM_PLBADDUHB 0x00000008
#define CONFIG_SYS_SDRAM_CONF1LL 0x00001080
#define CONFIG_SYS_SDRAM_CONF1HB 0x00001080
#define CONFIG_SYS_SDRAM_CONFPATHB 0x10a68000
/* SDRAM Controller */
#define CONFIG_SYS_SDRAM0_MB0CF 0x00000701
#define CONFIG_SYS_SDRAM0_MB1CF 0x00000000
#define CONFIG_SYS_SDRAM0_MB2CF 0x00000000
#define CONFIG_SYS_SDRAM0_MB3CF 0x00000000
#define CONFIG_SYS_SDRAM0_MCOPT1 0x05322000
#define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000
#define CONFIG_SYS_SDRAM0_MODT0 0x01000000
#define CONFIG_SYS_SDRAM0_MODT1 0x00000000
#define CONFIG_SYS_SDRAM0_MODT2 0x00000000
#define CONFIG_SYS_SDRAM0_MODT3 0x00000000
#define CONFIG_SYS_SDRAM0_CODT 0x00800021
#define CONFIG_SYS_SDRAM0_RTR 0x06180000
#define CONFIG_SYS_SDRAM0_INITPLR0 0xb5380000
#define CONFIG_SYS_SDRAM0_INITPLR1 0x82100400
#define CONFIG_SYS_SDRAM0_INITPLR2 0x80820000
#define CONFIG_SYS_SDRAM0_INITPLR3 0x80830000
#define CONFIG_SYS_SDRAM0_INITPLR4 0x80810040
#define CONFIG_SYS_SDRAM0_INITPLR5 0x80800532
#define CONFIG_SYS_SDRAM0_INITPLR6 0x82100400
#define CONFIG_SYS_SDRAM0_INITPLR7 0x8a080000
#define CONFIG_SYS_SDRAM0_INITPLR8 0x8a080000
#define CONFIG_SYS_SDRAM0_INITPLR9 0x8a080000
#define CONFIG_SYS_SDRAM0_INITPLR10 0x8a080000
#define CONFIG_SYS_SDRAM0_INITPLR11 0x80000432
#define CONFIG_SYS_SDRAM0_INITPLR12 0x808103c0
#define CONFIG_SYS_SDRAM0_INITPLR13 0x80810040
#define CONFIG_SYS_SDRAM0_INITPLR14 0x00000000
#define CONFIG_SYS_SDRAM0_INITPLR15 0x00000000
#define CONFIG_SYS_SDRAM0_RQDC 0x80000038
#define CONFIG_SYS_SDRAM0_RFDC 0x00000257
#define CONFIG_SYS_SDRAM0_RDCC 0x40000000
#define CONFIG_SYS_SDRAM0_DLCR 0x03000091
#define CONFIG_SYS_SDRAM0_CLKTR 0x40000000
#define CONFIG_SYS_SDRAM0_WRDTR 0x82000823
#define CONFIG_SYS_SDRAM0_SDTR1 0x80201000
#define CONFIG_SYS_SDRAM0_SDTR2 0x42204243
#define CONFIG_SYS_SDRAM0_SDTR3 0x090c0d1a
#define CONFIG_SYS_SDRAM0_MMODE 0x00000432
#define CONFIG_SYS_SDRAM0_MEMODE 0x00000004
#endif /* !defined(CONFIG_ARCHES) */
#endif /* !defined(CONFIG_NAND_U_BOOT) */
#define CONFIG_SYS_MBYTES_SDRAM 512 /* 512MB */
/*-----------------------------------------------------------------------
@ -254,18 +337,27 @@
#define CONFIG_SYS_DTT_LOW_TEMP -30
#define CONFIG_SYS_DTT_HYSTERESIS 3
#if defined(CONFIG_ARCHES)
#define CONFIG_SYS_I2C_DTT_ADDR 0x4a /* AD7414 I2C address */
#endif
#if !defined(CONFIG_ARCHES)
/* RTC configuration */
#define CONFIG_RTC_M41T62 1
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
#endif
/*-----------------------------------------------------------------------
* Ethernet
*----------------------------------------------------------------------*/
#define CONFIG_IBM_EMAC4_V4 1
#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
#define CONFIG_PHY1_ADDR 1
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#if !defined(CONFIG_ARCHES)
#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
#define CONFIG_PHY1_ADDR 1
/* Only Glacier (460GT) has 4 EMAC interfaces */
#ifdef CONFIG_460GT
#define CONFIG_PHY2_ADDR 2
@ -274,6 +366,30 @@
#define CONFIG_HAS_ETH3
#endif
#else /* defined(CONFIG_ARCHES) */
#define CONFIG_FIXED_PHY 0xFFFFFFFF
#define CONFIG_PHY_ADDR CONFIG_FIXED_PHY
#define CONFIG_PHY1_ADDR 0
#define CONFIG_PHY2_ADDR 1
#define CONFIG_HAS_ETH2
#define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
{devnum, speed, duplex}
#define CONFIG_SYS_FIXED_PHY_PORTS \
CONFIG_SYS_FIXED_PHY_PORT(0, 1000, FULL)
#define CONFIG_M88E1112_PHY
/*
* For the GPCS_PHYx_ADDR PHY address, choose some PHY address not
* used by CONFIG_PHYx_ADDR
*/
#define CONFIG_GPCS_PHY_ADDR 0xA
#define CONFIG_GPCS_PHY1_ADDR 0xB
#define CONFIG_GPCS_PHY2_ADDR 0xC
#endif /* !defined(CONFIG_ARCHES) */
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#define CONFIG_PHY_DYNAMIC_ANEG 1
@ -296,7 +412,8 @@
/*
* Default environment variables
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
#if !defined(CONFIG_ARCHES)
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_AMCC_DEF_ENV \
CONFIG_AMCC_DEF_ENV_POWERPC \
CONFIG_AMCC_DEF_ENV_NOR_UPD \
@ -307,20 +424,46 @@
"pciconfighost=1\0" \
"pcie_mode=RP:RP\0" \
""
#else /* defined(CONFIG_ARCHES) */
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_AMCC_DEF_ENV \
CONFIG_AMCC_DEF_ENV_POWERPC \
CONFIG_AMCC_DEF_ENV_NOR_UPD \
"kernel_addr=fe000000\0" \
"fdt_addr=fe1e0000\0" \
"ramdisk_addr=fe200000\0" \
"pciconfighost=1\0" \
"pcie_mode=RP:RP\0" \
"ethprime=ppc_4xx_eth1\0" \
""
#endif /* !defined(CONFIG_ARCHES) */
/*
* Commands additional to the ones defined in amcc-common.h
*/
#if defined(CONFIG_ARCHES)
#define CONFIG_CMD_DTT
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SDRAM
#elif defined(CONFIG_CANYONLANDS)
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DTT
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_USB
#elif defined(CONFIG_GLACIER)
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DTT
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SNTP
#ifdef CONFIG_460EX
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_USB
#else
#error "board type not defined"
#endif
/* Partitions */
@ -344,6 +487,36 @@
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
#ifdef CONFIG_460GT
#if defined(CONFIG_ARCHES)
/*-----------------------------------------------------------------------
* RapidIO I/O and Registers
*----------------------------------------------------------------------*/
#define CONFIG_RAPIDIO
#define CONFIG_SYS_460GT_SRIO_ERRATA_1
#define SRGPL0_REG_BAR 0x0000000DAA000000ull /* 16MB */
#define SRGPL0_CFG_BAR 0x0000000DAB000000ull /* 16MB */
#define SRGPL0_MNT_BAR 0x0000000DAC000000ull /* 16MB */
#define SRGPL0_MSG_BAR 0x0000000DAD000000ull /* 16MB */
#define SRGPL0_OUT_BAR 0x0000000DB0000000ull /* 256MB */
#define CONFIG_SYS_SRGPL0_REG_BAR 0xAA000000 /* 16MB */
#define CONFIG_SYS_SRGPL0_CFG_BAR 0xAB000000 /* 16MB */
#define CONFIG_SYS_SRGPL0_MNT_BAR 0xAC000000 /* 16MB */
#define CONFIG_SYS_SRGPL0_MSG_BAR 0xAD000000 /* 16MB */
#define CONFIG_SYS_I2ODMA_BASE 0xCF000000
#define CONFIG_SYS_I2ODMA_PHYS_ADDR 0x0000000400100000ull
#define CONFIG_PPC4XX_RAPIDIO_PROMISCUOUS_MODE
#undef CONFIG_PPC4XX_RAPIDIO_DEBUG
#undef CONFIG_PPC4XX_RAPIDIO_IN_BAR_USE_OCM
#define CONFIG_PPC4XX_RAPIDIO_USE_HB_PLB
#undef CONFIG_PPC4XX_RAPIDIO_LOOPBACK
#endif /* CONFIG_ARCHES */
#endif /* CONFIG_460GT */
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*----------------------------------------------------------------------*/
@ -356,6 +529,11 @@
* EBC address which accepts bigger regions:
*
* 0xfc00.0000 -> 4.cc00.0000
*
* Arches has 32MBytes of NOR FLASH (Spansion 29GL256), it will be
* remapped to:
*
* 0xfe00.0000 -> 4.ce00.0000
*/
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
@ -371,15 +549,25 @@
#define CONFIG_SYS_EBC_PB0AP 0x10055e00
#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
#if !defined(CONFIG_ARCHES)
/* Memory Bank 3 (NAND-FLASH) initialization */
#define CONFIG_SYS_EBC_PB3AP 0x018003c0
#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
#endif
#endif /*defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
#if !defined(CONFIG_ARCHES)
/* Memory Bank 2 (CPLD) initialization */
#define CONFIG_SYS_EBC_PB2AP 0x00804240
#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_BCSR_BASE | 0x18000) /* BAS=CPLD,BS=1M,BU=RW,BW=32bit */
#else /* defined(CONFIG_ARCHES) */
/* Memory Bank 1 (FPGA) initialization */
#define CONFIG_SYS_EBC_PB1AP 0x7f8ffe80
#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_FPGA_BASE | 0x3a000) /* BAS=FPGA,BS=2MB,BU=R/W,BW=16bit*/
#endif /* !defined(CONFIG_ARCHES) */
#define CONFIG_SYS_EBC_CFG 0xB8400000 /* EBC0_CFG */
/*

100
include/configs/hcu4.h
View File

@ -35,6 +35,12 @@
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_405GP 1
#define CONFIG_4xx 1
#define CONFIG_HOSTNAME hcu4
/*
* Include common defines/options for all boards produced by Netstal Maschinen
*/
#include "netstal-common.h"
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
@ -80,25 +86,12 @@
* If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
* set Linux BASE_BAUD to 403200.
*/
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
#define CONFIG_SERIAL_MULTI 1
/* needed to be able to define CONFIG_SERIAL_SOFTWARE_FIFO */
#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
#define CONFIG_SYS_BASE_BAUD 691200
/* Size (bytes) of interrupt driven serial port buffer.
* Set to 0 to use polling instead of interrupts.
* Setting to 0 will also disable RTS/CTS handshaking.
*/
#undef CONFIG_SERIAL_SOFTWARE_FIFO
/* Set console baudrate to 9600 */
#define CONFIG_BAUDRATE 9600
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
/*-----------------------------------------------------------------------
* Flash
*----------------------------------------------------------------------*/
@ -149,74 +142,12 @@
*----------------------------------------------------------------------*/
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_IPADDR 172.25.1.14
/* This is the 7bit address of the device, not including P. */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
/* The EEPROM can do 16byte ( 1 << 4 ) page writes. */
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
#undef CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_PREBOOT "echo;" \
"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
/* Setup some board specific values for the default environment variables */
#define CONFIG_HOSTNAME hcu4
#define CONFIG_IPADDR 172.25.1.99
#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */
#define CONFIG_OVERWRITE_ETHADDR_ONCE
#define CONFIG_SERVERIP 172.25.1.3
#define CONFIG_SYS_TFTP_LOADADDR 0x01000000 /* @16 MB */
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=0x01000000\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
"nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"rootpath=/home/diagnose/eldk/ppc_4xx\0" \
"bootfile=/tftpboot/hcu4/uImage\0" \
"load=tftp 100000 hcu4/u-boot.bin\0" \
"update=protect off FFFB0000 FFFFFFFF;era FFFB0000 FFFFFFFF;" \
"cp.b 100000 FFFB0000 50000\0" \
"upd=run load update\0" \
"vx_rom=hcu4/hcu4_vx_rom\0" \
"vx=tftp ${loadaddr} ${vx_rom};run vxargs; bootvx\0" \
"vxargs=setenv bootargs emac(0,0)c:${vx_rom} e=${ipaddr}" \
" h=${serverip} u=dpu pw=netstal8752 tn=hcu5 f=0x3008\0" \
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_NETSTAL_DEF_ENV \
CONFIG_NETSTAL_DEF_ENV_POWERPC \
""
#define CONFIG_BOOTCOMMAND "run vx"
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 1 /* PHY address */
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
#define CONFIG_HAS_ETH0
#define CONFIG_SYS_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & desC */
/*
* BOOTP options
@ -285,13 +216,6 @@
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
@ -348,8 +272,4 @@
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#endif /* __CONFIG_H */

118
include/configs/hcu5.h
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@ -1,5 +1,5 @@
/*
* (C) Copyright 2007 Netstal Maschinen AG
* (C) Copyright 2007-2008 Netstal Maschinen AG
* Niklaus Giger (Niklaus.Giger@netstal.com)
*
* (C) Copyright 2006-2007
@ -39,8 +39,14 @@
#define CONFIG_440EPX 1 /* Specific PPC440EPx */
#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
#define CONFIG_HOSTNAME hcu5
/*
* Include common defines/options for all boards produced by Netstal Maschinen
*/
#include "netstal-common.h"
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
@ -86,22 +92,10 @@
* Serial Port
*----------------------------------------------------------------------*/
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
#define CONFIG_BAUDRATE 9600
#define CONFIG_SERIAL_MULTI 1
/* needed to be able to define
CONFIG_SERIAL_SOFTWARE_FIFO, but
CONFIG_SERIAL_SOFTWARE_FIFO (16) does not work */
/* Size (bytes) of interrupt driven serial port buffer.
* Set to 0 to use polling instead of interrupts.
* Setting to 0 will also disable RTS/CTS handshaking.
*/
#define CONFIG_BAUDRATE 115200
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#undef CONFIG_UART1_CONSOLE
#undef CONFIG_CMD_HWFLOW
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
@ -144,93 +138,26 @@
#define PM_RESERVED_MEM ( 64) /* in kB: pmLib reserved area size */
#define CONFIG_PRAM ( USER_RESERVED_MEM + PM_RESERVED_MEM )
#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
/* 440EPx errata CHIP 11 */
/*-----------------------------------------------------------------------
* I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the
* the second internal I2C controller of the PPC440EPx
*----------------------------------------------------------------------*/
#define CONFIG_SYS_SPD_BUS_NUM 1
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
/* This is the 7bit address of the device, not including P. */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
/* The EEPROM can do 16byte ( 1 << 4 ) page writes. */
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
#undef CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run nfs\" to mount Linux root filesystem over NFS;"\
"echo"
#undef CONFIG_BOOTARGS
/* Setup some board specific values for the default environment variables */
#define CONFIG_HOSTNAME hcu5
#define CONFIG_IPADDR 172.25.1.99
#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */
#define CONFIG_OVERWRITE_ETHADDR_ONCE
#define CONFIG_SERVERIP 172.25.1.3
#define CONFIG_SYS_TFTP_LOADADDR 0x01000000 /* @16 MB */
#define CONFIG_IPADDR 172.25.1.15
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=0x01000000\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
"nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"bootfile=hcu5/uImage\0" \
"rootpath=/home/hcu/eldk/ppc_4xxFP\0" \
"load=tftp 100000 hcu5/u-boot.bin\0" \
"update=protect off FFFB0000 FFFFFFFF;era FFFB0000 FFFFFFFF;" \
"cp.b 100000 FFFB0000 50000\0" \
"upd=run load update\0" \
"vx_rom=hcu5/hcu5_vx_rom\0" \
"vx=tftp ${loadaddr} ${vx_rom};run vxargs; bootvx\0" \
"vxargs=setenv bootargs emac(0,0)c:${vx_rom} e=${ipaddr}" \
" h=${serverip} u=dpu pw=netstal8752 tn=hcu5 f=0x3008\0" \
"usbargs=setenv bootargs root=/dev/sda1 ro\0" \
"linux=usb start; ext2load usb 0 ${loadaddr} /boot/uImage;" \
"run usbargs addip addtty; bootm\0" \
"net_nfs_fdt=tftp 200000 ${bootfile};" \
"tftp ${fdt_addr} ${fdt_file};" \
"run nfsargs addip addtty;" \
"bootm 200000 - ${fdt_addr}\0" \
"fdt_file=hcu5/hcu5.dtb\0" \
"fdt_addr=400000\0" \
CONFIG_NETSTAL_DEF_ENV \
CONFIG_NETSTAL_DEF_ENV_POWERPC \
""
#define CONFIG_BOOTCOMMAND "run vx"
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_M88E1111_PHY 1
#define CONFIG_IBM_EMAC4_V4 1
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 1 /* PHY address, like on HCU4 */
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
#define CONFIG_HAS_ETH0
#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & desc. */
#define CONFIG_NET_MULTI 1
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
#define CONFIG_PHY1_ADDR 2
@ -279,7 +206,6 @@
/* POST support */
#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
CONFIG_SYS_POST_CPU | \
CONFIG_SYS_POST_UART | \
CONFIG_SYS_POST_I2C | \
CONFIG_SYS_POST_CACHE | \
@ -309,17 +235,9 @@
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
/*-----------------------------------------------------------------------
* PCI stuff
@ -409,8 +327,4 @@
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#endif /* __CONFIG_H */

92
include/configs/mcu25.h
View File

@ -35,6 +35,12 @@
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_405GP 1
#define CONFIG_4xx 1
#define CONFIG_HOSTNAME mcu25
/*
* Include common defines/options for all boards produced by Netstal Maschinen
*/
#include "netstal-common.h"
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
@ -80,8 +86,6 @@
* If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
* set Linux BASE_BAUD to 403200.
*/
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
#define CONFIG_SERIAL_MULTI 1
/* needed to be able to define CONFIG_SERIAL_SOFTWARE_FIFO */
#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
#define CONFIG_SYS_BASE_BAUD 691200
@ -95,10 +99,6 @@
/* Set console baudrate to 9600 */
#define CONFIG_BAUDRATE 9600
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
/*-----------------------------------------------------------------------
* Flash
*----------------------------------------------------------------------*/
@ -149,74 +149,13 @@
*----------------------------------------------------------------------*/
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
/* This is the 7bit address of the device, not including P. */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
/* The EEPROM can do 16byte ( 1 << 4 ) page writes. */
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
#undef CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
/* Setup some board specific values for the default environment variables */
#define CONFIG_HOSTNAME mcu25
#define CONFIG_IPADDR 172.25.1.99
#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */
#define CONFIG_OVERWRITE_ETHADDR_ONCE
#define CONFIG_SERVERIP 172.25.1.3
#define CONFIG_IPADDR 172.25.1.25
#define CONFIG_SYS_TFTP_LOADADDR 0x01000000 /* @16 MB */
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=0x01000000\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
"nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"rootpath=/home/diagnose/eldk/ppc_4xx\0" \
"bootfile=/tftpboot/mcu25/uImage\0" \
"load=tftp 100000 mcu25/u-boot.bin\0" \
"update=protect off FFFB0000 FFFFFFFF;era FFFB0000 FFFFFFFF;" \
"cp.b 100000 FFFB0000 50000\0" \
"upd=run load;run update\0" \
"vx_rom=mcu25/mcu25_vx_rom\0" \
"vx=tftp ${loadaddr} ${vx_rom};run vxargs; bootvx\0" \
"vxargs=setenv bootargs emac(0,0)c:${vx_rom} e=${ipaddr}" \
" h=${serverip} u=dpu pw=netstal8752 tn=hcu5 f=0x3008\0" \
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_NETSTAL_DEF_ENV \
CONFIG_NETSTAL_DEF_ENV_POWERPC \
""
#define CONFIG_BOOTCOMMAND "run vx"
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 1 /* PHY address */
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
#define CONFIG_HAS_ETH0
#define CONFIG_SYS_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descr */
/*
* BOOTP options
@ -285,13 +224,6 @@
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
@ -353,8 +285,4 @@
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#endif /* __CONFIG_H */

231
include/configs/neo.h Normal file
View File

@ -0,0 +1,231 @@
/*
* (C) Copyright 2007-2008
* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_405EP 1 /* this is a PPC405 CPU */
#define CONFIG_4xx 1 /* member of PPC4xx family */
#define CONFIG_NEO 1 /* on a Neo board */
/*
* Include common defines/options for all AMCC eval boards
*/
#define CONFIG_HOSTNAME neo
#include "amcc-common.h"
#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
/*
* Configure PLL
*/
#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
/* new uImage format support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
/*
* Default environment variables
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_AMCC_DEF_ENV \
CONFIG_AMCC_DEF_ENV_POWERPC \
CONFIG_AMCC_DEF_ENV_NOR_UPD \
"kernel_addr=fc000000\0" \
"fdt_addr=fc1e0000\0" \
"ramdisk_addr=fc200000\0" \
""
#define CONFIG_PHY_ADDR 4 /* PHY address */
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
/*
* Commands additional to the ones defined in amcc-common.h
*/
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DTT
#undef CONFIG_CMD_EEPROM
/*
* SDRAM configuration (please see cpu/ppc/sdram.[ch])
*/
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
/* SDRAM timings used in datasheet */
#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
/*
* If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
* If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
* Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
* The Linux BASE_BAUD define should match this configuration.
* baseBaud = cpuClock/(uartDivisor*16)
* If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
* set Linux BASE_BAUD to 403200.
*/
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
#define CONFIG_SYS_BASE_BAUD 691200
/*
* I2C stuff
*/
#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
/* RTC */
#define CONFIG_RTC_DS1337
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
/* Temp sensor/hwmon/dtt */
#define CONFIG_DTT_LM63 1 /* National LM63 */
#define CONFIG_DTT_SENSORS { 0 } /* Sensor addresses */
#define CONFIG_DTT_PWM_LOOKUPTABLE \
{ { 40, 10 }, { 50, 20 }, { 60, 40 } }
#define CONFIG_DTT_TACH_LIMIT 0xa10
/*
* FLASH organization
*/
#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CONFIG_SYS_FLASH_BASE 0xFC000000
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
#endif
/*
* PPC405 GPIO Configuration
*/
#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
{ \
/* GPIO Core 0 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO5 TS3 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
} \
}
/*
* Definitions for initial stack pointer and data area (in data cache)
*/
/* use on chip memory (OCM) for temperary stack until sdram is tested */
#define CONFIG_SYS_TEMP_STACK_OCM 1
/* On Chip Memory location */
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
* External Bus Controller (EBC) Setup
*/
/* Memory Bank 0 (NOR-FLASH) initialization */
#define CONFIG_SYS_EBC_PB0AP 0x92015480
#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000 /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */
/* Memory Bank 1 (NVRAM) initialization */
#define CONFIG_SYS_EBC_PB1AP 0x92015480
#define CONFIG_SYS_EBC_PB1CR 0xFB85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
/* Memory Bank 2 (FPGA) initialization */
#define CONFIG_FPGA_BASE 0x7f100000
#define CONFIG_SYS_EBC_PB2AP 0x92015480
#define CONFIG_SYS_EBC_PB2CR 0x7f11a000 /* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
/* Memory Bank 3 (Latches) initialization */
#define CONFIG_SYS_EBC_PB3AP 0x92015480
#define CONFIG_SYS_EBC_PB3CR 0x7f21a000 /* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
#endif /* __CONFIG_H */

255
include/configs/netstal-common.h Normal file
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@ -0,0 +1,255 @@
/*
* (C) Copyright 2008
* Niklaus Giger, Netstal Maschinen AG, niklaus.giger@netstal.com
* adapted from amcc-common.h by
* (C) Copyright 2008
* * Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* Common configuration options for all Netstal boards
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __NETSTAL_COMMON_H
#define __NETSTAL_COMMON_H
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* Start of U-Boot */
#define CONFIG_SYS_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
/*
* UART
*/
#define CONFIG_SERIAL_MULTI
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
/*
* I2C
*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
/* This is the 7bit address of the device, not including P. */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
/* The EEPROM can do 16byte ( 1 << 4 ) page writes. */
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
/*
* Ethernet/EMAC/PHY
*/
#define CONFIG_MII /* MII PHY management */
#define CONFIG_PHY_ADDR 1 /* PHY address */
#if defined(CONFIG_440)
#define CONFIG_NET_MULTI 1
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_SYS_RX_ETH_BUFFER 32 /* number of eth rx buffers */
#else
#define CONFIG_SYS_RX_ETH_BUFFER 16 /* number of eth rx buffers */
#endif
#define CONFIG_HAS_ETH0
/*
* Commands
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#if defined(CONFIG_440)
#define CONFIG_CMD_CACHE
#endif
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_BOOT_RETRY_TIME 30
#define CONFIG_RESET_TO_RETRY
/*
* Miscellaneous configurable options
*/
#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_EXTBDINFO /* To use extended board_into (bd_t) */
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_CMDLINE_EDITING /* add command line history */
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_LOOPW /* enable loopw command */
#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE /* include version env variable */
#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/
#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#endif
#define CONFIG_LOADS_ECHO /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_SUBNETMASK
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*
* Internal Definitions
*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/*
* Pass open firmware flat tree
*/
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP
/*
* Booting and default environment
*/
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run net_nfs\" to mount root filesystem over NFS;" \
"echo"
#define CONFIG_BOOTCOMMAND "run vx"
/*
* Only very few boards have default console not on ttyS0 (like Taishan)
*/
#if !defined(CONFIG_USE_TTY)
#define CONFIG_USE_TTY ttyS0
#endif
/*
* Only some 4xx PPC's are equipped with an FPU
*/
#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define CONFIG_NETSTAL_DEF_ENV_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0"
#else
#define CONFIG_NETSTAL_DEF_ENV_ROOTPATH "rootpath=/opt/eldk/ppc_4xx\0"
#endif
/*
* Only some boards need to extend the bootargs by some additional
* parameters (like Makalu)
*/
#if !defined(CONFIG_ADDMISC)
#define CONFIG_ADDMISC "addmisc=setenv bootargs ${bootargs}\0"
#endif
#define xstr(s) str(s)
#define str(s) #s
/* Setup some values for the default environment variables */
#define CONFIG_SERVERIP 172.25.1.1
#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */
#define CONFIG_OVERWRITE_ETHADDR_ONCE
#define CONFIG_SYS_TFTP_LOADADDR 0x01000000
/*
* General common environment variables shared by all boards produced by Netstal Maschinen
*/
#define CONFIG_NETSTAL_DEF_ENV \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addtty=setenv bootargs ${bootargs}" \
" console=" xstr(CONFIG_USE_TTY) ",${baudrate}\0" \
CONFIG_ADDMISC \
"initrd_high=30000000\0" \
"kernel_addr_r=400000\0" \
"fdt_addr_r=800000\0" \
"hostname=" xstr(CONFIG_HOSTNAME) "\0" \
"bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
"load=tftp 200000 " xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
"update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;" \
"era " xstr(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;" \
"cp.b ${fileaddr} " xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize};" \
"setenv filesize\0" \
"upd=run load update\0" \
"vx_rom=" xstr(CONFIG_HOSTNAME) "/" \
xstr(CONFIG_HOSTNAME) "_vx_rom\0" \
"vx=tftp " xstr(CONFIG_SYS_TFTP_LOADADDR) " ${vx_rom};run vxargs;" \
"bootvx\0" \
"vxargs=setenv bootargs emac(0,0)c:${vx_rom} e=${ipaddr}" \
" h=${serverip} u=dpu pw=netstal8752 " \
"tn=" xstr(CONFIG_HOSTNAME) " f=0x3008\0" \
CONFIG_NETSTAL_DEF_ENV_ROOTPATH
/*
* Default environment for arch/powerpc booting
* for boards that are ported to arch/powerpc
*/
#define CONFIG_NETSTAL_DEF_ENV_POWERPC \
"flash_self=run ramargs addip addtty addmisc;" \
"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
"flash_nfs=run nfsargs addip addtty addmisc;" \
"bootm ${kernel_addr} - ${fdt_addr}\0" \
"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
"tftp ${fdt_addr_r} ${fdt_file}; " \
"run nfsargs addip addtty addmisc;" \
"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
"fdt_file=" xstr(CONFIG_HOSTNAME) "/" xstr(CONFIG_HOSTNAME) ".dtb\0"
#endif /* __NETSTAL_COMMON_H */

3
include/ppc440.h
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@ -1349,6 +1349,9 @@
#define SDR0_ETH_CFG_ZMII_RMII_MODE_10M 0x10
#define SDR0_ETH_CFG_ZMII_RMII_MODE_100M 0x11
/* Ethernet Status Register */
#define SDR0_ETH_STS 0x4104
/* Miscealleneaous Function Reg. (SDR0_MFR) */
#define SDR0_MFR 0x4300
#define SDR0_MFR_T0TxFL 0x00800000 /* force parity error TAHOE0 Tx FIFO bits 0:63 */

3
include/ppc4xx.h
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@ -218,4 +218,7 @@ static inline void set_mcsr(u32 val)
#endif /* __ASSEMBLY__ */
/* for multi-cpu support */
#define NA_OR_UNKNOWN_CPU -1
#endif /* __PPC4XX_H__ */