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Improve configuration of FPGA subsystem 

This patch removes the FPGA subsystem configuration through
the CONFIG_FPGA bitmask configuration option.

See README for the new options:

	CONFIG_FPGA,
	CONFIG_FPGA_<vendor>,
	CONFIG_FPGA_<family>

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
This commit is contained in:
Matthias Fuchs 2007-12-27 17:12:34 +01:00 committed by Wolfgang Denk
parent 95c6bc7d4a
commit 0133502e39
16 changed files with 70 additions and 63 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
README
View File

@ -1377,15 +1377,24 @@ The following options need to be configured:
SPI configuration items (port pins to use, etc). For SPI configuration items (port pins to use, etc). For
an example, see include/configs/sacsng.h. an example, see include/configs/sacsng.h.
- FPGA Support: CONFIG_FPGA_COUNT - FPGA Support: CONFIG_FPGA
Enables FPGA subsystem.
CONFIG_FPGA_<vendor>
Enables support for specific chip vendors.
(ALTERA, XILINX)
CONFIG_FPGA_<family>
Enables support for FPGA family.
(SPARTAN2, SPARTAN3, VIRTEX2, CYCLONE2, ACEX1K, ACEX)
CONFIG_FPGA_COUNT
Specify the number of FPGA devices to support. Specify the number of FPGA devices to support.
CONFIG_FPGA
Used to specify the types of FPGA devices. For example,
#define CONFIG_FPGA CFG_XILINX_VIRTEX2
CFG_FPGA_PROG_FEEDBACK CFG_FPGA_PROG_FEEDBACK
Enable printing of hash marks during FPGA configuration. Enable printing of hash marks during FPGA configuration.

2
board/gen860t/fpga.c
View File

@ -34,7 +34,7 @@
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
#if (CONFIG_FPGA) #if defined(CONFIG_FPGA)
#if 0 #if 0
#define GEN860T_FPGA_DEBUG #define GEN860T_FPGA_DEBUG

2
board/gen860t/gen860t.c
View File

@ -254,7 +254,7 @@ int misc_init_r (void)
mii_init (); mii_init ();
#endif #endif
#if (CONFIG_FPGA) #if defined(CONFIG_FPGA)
gen860t_init_fpga (); gen860t_init_fpga ();
#endif #endif
return 0; return 0;

4
common/ACEX1K.c
View File

@ -28,7 +28,7 @@
#include <common.h> /* core U-Boot definitions */ #include <common.h> /* core U-Boot definitions */
#include <ACEX1K.h> /* ACEX device family */ #include <ACEX1K.h> /* ACEX device family */
#if (CONFIG_FPGA & (CFG_ALTERA | CFG_ACEX1K)) #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ALTERA) && defined(CONFIG_FPGA_ACEX1K)
/* Define FPGA_DEBUG to get debug printf's */ /* Define FPGA_DEBUG to get debug printf's */
#ifdef FPGA_DEBUG #ifdef FPGA_DEBUG
@ -363,4 +363,4 @@ static int ACEX1K_ps_reloc (Altera_desc * desc, ulong reloc_offset)
} }
#endif /* (CONFIG_FPGA & (CFG_ALTERA | CFG_ACEX1K)) */ #endif /* CONFIG_FPGA && CONFIG_FPGA_ALTERA && CONFIG_FPGA_ACEX1K */

18
common/altera.c
View File

@ -40,7 +40,7 @@
#define PRINTF(fmt,args...) #define PRINTF(fmt,args...)
#endif #endif
#if (CONFIG_FPGA & CFG_FPGA_ALTERA) #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ALTERA)
/* Local Static Functions */ /* Local Static Functions */
static int altera_validate (Altera_desc * desc, char *fn); static int altera_validate (Altera_desc * desc, char *fn);
@ -56,11 +56,11 @@ int altera_load( Altera_desc *desc, void *buf, size_t bsize )
switch (desc->family) { switch (desc->family) {
case Altera_ACEX1K: case Altera_ACEX1K:
case Altera_CYC2: case Altera_CYC2:
#if (CONFIG_FPGA & CFG_ACEX1K) #if defined(CONFIG_FPGA_ACEX1K)
PRINTF ("%s: Launching the ACEX1K Loader...\n", PRINTF ("%s: Launching the ACEX1K Loader...\n",
__FUNCTION__); __FUNCTION__);
ret_val = ACEX1K_load (desc, buf, bsize); ret_val = ACEX1K_load (desc, buf, bsize);
#elif (CONFIG_FPGA & CFG_CYCLON2) #elif defined CONFIG_FPGA_CYCLON2
PRINTF ("%s: Launching the CYCLON II Loader...\n", PRINTF ("%s: Launching the CYCLON II Loader...\n",
__FUNCTION__); __FUNCTION__);
ret_val = CYC2_load (desc, buf, bsize); ret_val = CYC2_load (desc, buf, bsize);
@ -88,7 +88,7 @@ int altera_dump( Altera_desc *desc, void *buf, size_t bsize )
} else { } else {
switch (desc->family) { switch (desc->family) {
case Altera_ACEX1K: case Altera_ACEX1K:
#if (CONFIG_FPGA & CFG_ACEX) #if defined(CONFIG_FPGA_ACEX)
PRINTF ("%s: Launching the ACEX1K Reader...\n", PRINTF ("%s: Launching the ACEX1K Reader...\n",
__FUNCTION__); __FUNCTION__);
ret_val = ACEX1K_dump (desc, buf, bsize); ret_val = ACEX1K_dump (desc, buf, bsize);
@ -156,9 +156,9 @@ int altera_info( Altera_desc *desc )
switch (desc->family) { switch (desc->family) {
case Altera_ACEX1K: case Altera_ACEX1K:
case Altera_CYC2: case Altera_CYC2:
#if (CONFIG_FPGA & CFG_ACEX1K) #if defined(CONFIG_FPGA_ACEX1K)
ACEX1K_info (desc); ACEX1K_info (desc);
#elif (CONFIG_FPGA & CFG_CYCLON2) #elif defined(CONFIG_FPGA_CYCLON2)
CYC2_info (desc); CYC2_info (desc);
#else #else
/* just in case */ /* just in case */
@ -192,7 +192,7 @@ int altera_reloc( Altera_desc *desc, ulong reloc_offset)
} else { } else {
switch (desc->family) { switch (desc->family) {
case Altera_ACEX1K: case Altera_ACEX1K:
#if (CONFIG_FPGA & CFG_ACEX1K) #if defined(CONFIG_FPGA_ACEX1K)
ret_val = ACEX1K_reloc (desc, reloc_offset); ret_val = ACEX1K_reloc (desc, reloc_offset);
#else #else
printf ("%s: No support for ACEX devices.\n", printf ("%s: No support for ACEX devices.\n",
@ -200,7 +200,7 @@ int altera_reloc( Altera_desc *desc, ulong reloc_offset)
#endif #endif
break; break;
case Altera_CYC2: case Altera_CYC2:
#if (CONFIG_FPGA & CFG_CYCLON2) #if defined(CONFIG_FPGA_CYCLON2)
ret_val = CYC2_reloc (desc, reloc_offset); ret_val = CYC2_reloc (desc, reloc_offset);
#else #else
printf ("%s: No support for CYCLON II devices.\n", printf ("%s: No support for CYCLON II devices.\n",
@ -249,4 +249,4 @@ static int altera_validate (Altera_desc * desc, char *fn)
/* ------------------------------------------------------------------------- */ /* ------------------------------------------------------------------------- */
#endif /* CONFIG_FPGA & CFG_FPGA_ALTERA */ #endif /* CONFIG_FPGA & CONFIG_FPGA_ALTERA */

2
common/cmd_fpga.c
View File

@ -58,7 +58,7 @@ static int fpga_get_op (char *opstr);
/* Convert bitstream data and load into the fpga */ /* Convert bitstream data and load into the fpga */
int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size) int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
{ {
#if (CONFIG_FPGA & CFG_FPGA_XILINX) #if defined(CONFIG_FPGA_XILINX)
unsigned int length; unsigned int length;
unsigned char* swapdata; unsigned char* swapdata;
unsigned int swapsize; unsigned int swapsize;

4
common/cyclon2.c
View File

@ -27,7 +27,7 @@
#include <altera.h> #include <altera.h>
#include <ACEX1K.h> /* ACEX device family */ #include <ACEX1K.h> /* ACEX device family */
#if (CONFIG_FPGA & (CFG_ALTERA | CFG_CYCLON2)) #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ALTERA) && defined(CONFIG_FPGA_CYCLON2)
/* Define FPGA_DEBUG to get debug printf's */ /* Define FPGA_DEBUG to get debug printf's */
#ifdef FPGA_DEBUG #ifdef FPGA_DEBUG
@ -302,4 +302,4 @@ static int CYC2_ps_reloc (Altera_desc * desc, ulong reloc_offset)
return ret_val; return ret_val;
} }
#endif /* (CONFIG_FPGA & (CFG_ALTERA | CFG_CYCLON2)) */ #endif /* CONFIG_FPGA && CONFIG_FPGA_ALTERA && CONFIG_FPGA_CYCLON2 */

30
common/fpga.c
View File

@ -67,14 +67,11 @@ static int fpga_dev_info( int devnum );
static void fpga_no_sup( char *fn, char *msg ) static void fpga_no_sup( char *fn, char *msg )
{ {
if ( fn && msg ) { if ( fn && msg ) {
printf( "%s: No support for %s. CONFIG_FPGA defined as 0x%x.\n", printf( "%s: No support for %s.\n", fn, msg);
fn, msg, CONFIG_FPGA );
} else if ( msg ) { } else if ( msg ) {
printf( "No support for %s. CONFIG_FPGA defined as 0x%x.\n", printf( "No support for %s.\n", msg);
msg, CONFIG_FPGA );
} else { } else {
printf( "No FPGA suport! CONFIG_FPGA defined as 0x%x.\n", printf( "No FPGA suport!\n");
CONFIG_FPGA );
} }
} }
@ -112,11 +109,6 @@ static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_va
printf( "%s: Null buffer.\n", fn ); printf( "%s: Null buffer.\n", fn );
return (fpga_desc * const)NULL; return (fpga_desc * const)NULL;
} }
if ( !bsize ) {
printf( "%s: Null buffer size.\n", fn );
return (fpga_desc * const)NULL;
}
return desc; return desc;
} }
@ -135,7 +127,7 @@ static int fpga_dev_info( int devnum )
switch ( desc->devtype ) { switch ( desc->devtype ) {
case fpga_xilinx: case fpga_xilinx:
#if CONFIG_FPGA & CFG_FPGA_XILINX #if defined(CONFIG_FPGA_XILINX)
printf( "Xilinx Device\nDescriptor @ 0x%p\n", desc ); printf( "Xilinx Device\nDescriptor @ 0x%p\n", desc );
ret_val = xilinx_info( desc->devdesc ); ret_val = xilinx_info( desc->devdesc );
#else #else
@ -143,7 +135,7 @@ static int fpga_dev_info( int devnum )
#endif #endif
break; break;
case fpga_altera: case fpga_altera:
#if CONFIG_FPGA & CFG_FPGA_ALTERA #if defined(CONFIG_FPGA_ALTERA)
printf( "Altera Device\nDescriptor @ 0x%p\n", desc ); printf( "Altera Device\nDescriptor @ 0x%p\n", desc );
ret_val = altera_info( desc->devdesc ); ret_val = altera_info( desc->devdesc );
#else #else
@ -175,14 +167,14 @@ int fpga_reloc( fpga_type devtype, void *desc, ulong reloc_off )
switch ( devtype ) { switch ( devtype ) {
case fpga_xilinx: case fpga_xilinx:
#if CONFIG_FPGA & CFG_FPGA_XILINX #if defined(CONFIG_FPGA_XILINX)
ret_val = xilinx_reloc( desc, reloc_off ); ret_val = xilinx_reloc( desc, reloc_off );
#else #else
fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" ); fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" );
#endif #endif
break; break;
case fpga_altera: case fpga_altera:
#if CONFIG_FPGA & CFG_FPGA_ALTERA #if defined(CONFIG_FPGA_ALTERA)
ret_val = altera_reloc( desc, reloc_off ); ret_val = altera_reloc( desc, reloc_off );
#else #else
fpga_no_sup( (char *)__FUNCTION__, "Altera devices" ); fpga_no_sup( (char *)__FUNCTION__, "Altera devices" );
@ -268,14 +260,14 @@ int fpga_load( int devnum, void *buf, size_t bsize )
if ( desc ) { if ( desc ) {
switch ( desc->devtype ) { switch ( desc->devtype ) {
case fpga_xilinx: case fpga_xilinx:
#if CONFIG_FPGA & CFG_FPGA_XILINX #if defined(CONFIG_FPGA_XILINX)
ret_val = xilinx_load( desc->devdesc, buf, bsize ); ret_val = xilinx_load( desc->devdesc, buf, bsize );
#else #else
fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" ); fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" );
#endif #endif
break; break;
case fpga_altera: case fpga_altera:
#if CONFIG_FPGA & CFG_FPGA_ALTERA #if defined(CONFIG_FPGA_ALTERA)
ret_val = altera_load( desc->devdesc, buf, bsize ); ret_val = altera_load( desc->devdesc, buf, bsize );
#else #else
fpga_no_sup( (char *)__FUNCTION__, "Altera devices" ); fpga_no_sup( (char *)__FUNCTION__, "Altera devices" );
@ -301,14 +293,14 @@ int fpga_dump( int devnum, void *buf, size_t bsize )
if ( desc ) { if ( desc ) {
switch ( desc->devtype ) { switch ( desc->devtype ) {
case fpga_xilinx: case fpga_xilinx:
#if CONFIG_FPGA & CFG_FPGA_XILINX #if defined(CONFIG_FPGA_XILINX)
ret_val = xilinx_dump( desc->devdesc, buf, bsize ); ret_val = xilinx_dump( desc->devdesc, buf, bsize );
#else #else
fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" ); fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" );
#endif #endif
break; break;
case fpga_altera: case fpga_altera:
#if CONFIG_FPGA & CFG_FPGA_ALTERA #if defined(CONFIG_FPGA_ALTERA)
ret_val = altera_dump( desc->devdesc, buf, bsize ); ret_val = altera_dump( desc->devdesc, buf, bsize );
#else #else
fpga_no_sup( (char *)__FUNCTION__, "Altera devices" ); fpga_no_sup( (char *)__FUNCTION__, "Altera devices" );

2
common/spartan2.c
View File

@ -25,7 +25,7 @@
#include <common.h> /* core U-Boot definitions */ #include <common.h> /* core U-Boot definitions */
#include <spartan2.h> /* Spartan-II device family */ #include <spartan2.h> /* Spartan-II device family */
#if (CONFIG_FPGA & (CFG_XILINX | CFG_SPARTAN2)) #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_SPARTAN2)
/* Define FPGA_DEBUG to get debug printf's */ /* Define FPGA_DEBUG to get debug printf's */
#ifdef FPGA_DEBUG #ifdef FPGA_DEBUG

2
common/spartan3.c
View File

@ -30,7 +30,7 @@
#include <common.h> /* core U-Boot definitions */ #include <common.h> /* core U-Boot definitions */
#include <spartan3.h> /* Spartan-II device family */ #include <spartan3.h> /* Spartan-II device family */
#if (CONFIG_FPGA & (CFG_XILINX | CFG_SPARTAN3)) #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_SPARTAN3)
/* Define FPGA_DEBUG to get debug printf's */ /* Define FPGA_DEBUG to get debug printf's */
#ifdef FPGA_DEBUG #ifdef FPGA_DEBUG

2
common/virtex2.c
View File

@ -31,7 +31,7 @@
#include <common.h> #include <common.h>
#include <virtex2.h> #include <virtex2.h>
#if (CONFIG_FPGA & (CFG_XILINX | CFG_VIRTEX2)) #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_VIRTEX2)
#if 0 #if 0
#define FPGA_DEBUG #define FPGA_DEBUG

28
common/xilinx.c
View File

@ -32,7 +32,7 @@
#include <spartan2.h> #include <spartan2.h>
#include <spartan3.h> #include <spartan3.h>
#if (CONFIG_FPGA & CFG_FPGA_XILINX) #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_XILINX)
#if 0 #if 0
#define FPGA_DEBUG #define FPGA_DEBUG
@ -59,7 +59,7 @@ int xilinx_load (Xilinx_desc * desc, void *buf, size_t bsize)
} else } else
switch (desc->family) { switch (desc->family) {
case Xilinx_Spartan2: case Xilinx_Spartan2:
#if (CONFIG_FPGA & CFG_SPARTAN2) #if defined(CONFIG_FPGA_SPARTAN2)
PRINTF ("%s: Launching the Spartan-II Loader...\n", PRINTF ("%s: Launching the Spartan-II Loader...\n",
__FUNCTION__); __FUNCTION__);
ret_val = Spartan2_load (desc, buf, bsize); ret_val = Spartan2_load (desc, buf, bsize);
@ -69,7 +69,7 @@ int xilinx_load (Xilinx_desc * desc, void *buf, size_t bsize)
#endif #endif
break; break;
case Xilinx_Spartan3: case Xilinx_Spartan3:
#if (CONFIG_FPGA & CFG_SPARTAN3) #if defined(CONFIG_FPGA_SPARTAN3)
PRINTF ("%s: Launching the Spartan-III Loader...\n", PRINTF ("%s: Launching the Spartan-III Loader...\n",
__FUNCTION__); __FUNCTION__);
ret_val = Spartan3_load (desc, buf, bsize); ret_val = Spartan3_load (desc, buf, bsize);
@ -79,7 +79,7 @@ int xilinx_load (Xilinx_desc * desc, void *buf, size_t bsize)
#endif #endif
break; break;
case Xilinx_Virtex2: case Xilinx_Virtex2:
#if (CONFIG_FPGA & CFG_VIRTEX2) #if defined(CONFIG_FPGA_VIRTEX2)
PRINTF ("%s: Launching the Virtex-II Loader...\n", PRINTF ("%s: Launching the Virtex-II Loader...\n",
__FUNCTION__); __FUNCTION__);
ret_val = Virtex2_load (desc, buf, bsize); ret_val = Virtex2_load (desc, buf, bsize);
@ -106,7 +106,7 @@ int xilinx_dump (Xilinx_desc * desc, void *buf, size_t bsize)
} else } else
switch (desc->family) { switch (desc->family) {
case Xilinx_Spartan2: case Xilinx_Spartan2:
#if (CONFIG_FPGA & CFG_SPARTAN2) #if defined(CONFIG_FPGA_SPARTAN2)
PRINTF ("%s: Launching the Spartan-II Reader...\n", PRINTF ("%s: Launching the Spartan-II Reader...\n",
__FUNCTION__); __FUNCTION__);
ret_val = Spartan2_dump (desc, buf, bsize); ret_val = Spartan2_dump (desc, buf, bsize);
@ -116,7 +116,7 @@ int xilinx_dump (Xilinx_desc * desc, void *buf, size_t bsize)
#endif #endif
break; break;
case Xilinx_Spartan3: case Xilinx_Spartan3:
#if (CONFIG_FPGA & CFG_SPARTAN3) #if defined(CONFIG_FPGA_SPARTAN3)
PRINTF ("%s: Launching the Spartan-III Reader...\n", PRINTF ("%s: Launching the Spartan-III Reader...\n",
__FUNCTION__); __FUNCTION__);
ret_val = Spartan3_dump (desc, buf, bsize); ret_val = Spartan3_dump (desc, buf, bsize);
@ -126,7 +126,7 @@ int xilinx_dump (Xilinx_desc * desc, void *buf, size_t bsize)
#endif #endif
break; break;
case Xilinx_Virtex2: case Xilinx_Virtex2:
#if (CONFIG_FPGA & CFG_VIRTEX2) #if defined( CONFIG_FPGA_VIRTEX2)
PRINTF ("%s: Launching the Virtex-II Reader...\n", PRINTF ("%s: Launching the Virtex-II Reader...\n",
__FUNCTION__); __FUNCTION__);
ret_val = Virtex2_dump (desc, buf, bsize); ret_val = Virtex2_dump (desc, buf, bsize);
@ -198,7 +198,7 @@ int xilinx_info (Xilinx_desc * desc)
printf ("Device Function Table @ 0x%p\n", desc->iface_fns); printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
switch (desc->family) { switch (desc->family) {
case Xilinx_Spartan2: case Xilinx_Spartan2:
#if (CONFIG_FPGA & CFG_SPARTAN2) #if defined(CONFIG_FPGA_SPARTAN2)
Spartan2_info (desc); Spartan2_info (desc);
#else #else
/* just in case */ /* just in case */
@ -207,7 +207,7 @@ int xilinx_info (Xilinx_desc * desc)
#endif #endif
break; break;
case Xilinx_Spartan3: case Xilinx_Spartan3:
#if (CONFIG_FPGA & CFG_SPARTAN3) #if defined(CONFIG_FPGA_SPARTAN3)
Spartan3_info (desc); Spartan3_info (desc);
#else #else
/* just in case */ /* just in case */
@ -216,7 +216,7 @@ int xilinx_info (Xilinx_desc * desc)
#endif #endif
break; break;
case Xilinx_Virtex2: case Xilinx_Virtex2:
#if (CONFIG_FPGA & CFG_VIRTEX2) #if defined(CONFIG_FPGA_VIRTEX2)
Virtex2_info (desc); Virtex2_info (desc);
#else #else
/* just in case */ /* just in case */
@ -249,7 +249,7 @@ int xilinx_reloc (Xilinx_desc * desc, ulong reloc_offset)
} else } else
switch (desc->family) { switch (desc->family) {
case Xilinx_Spartan2: case Xilinx_Spartan2:
#if (CONFIG_FPGA & CFG_SPARTAN2) #if defined(CONFIG_FPGA_SPARTAN2)
ret_val = Spartan2_reloc (desc, reloc_offset); ret_val = Spartan2_reloc (desc, reloc_offset);
#else #else
printf ("%s: No support for Spartan-II devices.\n", printf ("%s: No support for Spartan-II devices.\n",
@ -257,7 +257,7 @@ int xilinx_reloc (Xilinx_desc * desc, ulong reloc_offset)
#endif #endif
break; break;
case Xilinx_Spartan3: case Xilinx_Spartan3:
#if (CONFIG_FPGA & CFG_SPARTAN3) #if defined(CONFIG_FPGA_SPARTAN3)
ret_val = Spartan3_reloc (desc, reloc_offset); ret_val = Spartan3_reloc (desc, reloc_offset);
#else #else
printf ("%s: No support for Spartan-III devices.\n", printf ("%s: No support for Spartan-III devices.\n",
@ -265,7 +265,7 @@ int xilinx_reloc (Xilinx_desc * desc, ulong reloc_offset)
#endif #endif
break; break;
case Xilinx_Virtex2: case Xilinx_Virtex2:
#if (CONFIG_FPGA & CFG_VIRTEX2) #if defined(CONFIG_FPGA_VIRTEX2)
ret_val = Virtex2_reloc (desc, reloc_offset); ret_val = Virtex2_reloc (desc, reloc_offset);
#else #else
printf ("%s: No support for Virtex-II devices.\n", printf ("%s: No support for Virtex-II devices.\n",
@ -308,4 +308,4 @@ static int xilinx_validate (Xilinx_desc * desc, char *fn)
return ret_val; return ret_val;
} }
#endif /* CONFIG_FPGA & CFG_FPGA_XILINX */ #endif /* CONFIG_FPGA && CONFIG_FPGA_XILINX */

4
include/configs/GEN860T.h
View File

@ -273,7 +273,9 @@
* Virtex2 FPGA configuration support * Virtex2 FPGA configuration support
*/ */
#define CONFIG_FPGA_COUNT 1 #define CONFIG_FPGA_COUNT 1
#define CONFIG_FPGA CFG_XILINX_VIRTEX2 #define CONFIG_FPGA
#define CONFIG_FPGA_XILINX
#define CONFIG_FPGA_VIRTEX2
#define CFG_FPGA_PROG_FEEDBACK #define CFG_FPGA_PROG_FEEDBACK

4
include/configs/M54455EVB.h
View File

@ -192,7 +192,9 @@
/* FPGA - Spartan 2 */ /* FPGA - Spartan 2 */
/* experiment /* experiment
#define CONFIG_FPGA CFG_SPARTAN3 #define CONFIG_FPGA
#define CONFIG_FPGA_XILINX
#define CONFIG_FPGA_SPARTAN3
#define CONFIG_FPGA_COUNT 1 #define CONFIG_FPGA_COUNT 1
#define CFG_FPGA_PROG_FEEDBACK #define CFG_FPGA_PROG_FEEDBACK
#define CFG_FPGA_CHECK_CTRLC #define CFG_FPGA_CHECK_CTRLC

4
include/configs/alpr.h
View File

@ -296,7 +296,9 @@
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* FPGA stuff * FPGA stuff
*-----------------------------------------------------------------------*/ *-----------------------------------------------------------------------*/
#define CONFIG_FPGA CFG_ALTERA_CYCLON2 #define CONFIG_FPGA
#define CONFIG_FPGA_ALTERA
#define CONFIG_FPGA_CYCLON2
#define CFG_FPGA_CHECK_CTRLC #define CFG_FPGA_CHECK_CTRLC
#define CFG_FPGA_PROG_FEEDBACK #define CFG_FPGA_PROG_FEEDBACK
#define CONFIG_FPGA_COUNT 1 /* Ich habe 2 ... aber in #define CONFIG_FPGA_COUNT 1 /* Ich habe 2 ... aber in

4
include/xilinx.h
View File

@ -31,11 +31,11 @@
*********************************************************************/ *********************************************************************/
#define CFG_SPARTAN2 CFG_FPGA_DEV( 0x1 ) #define CFG_SPARTAN2 CFG_FPGA_DEV( 0x1 )
#define CFG_VIRTEX_E CFG_FPGA_DEV( 0x2 ) #define CFG_VIRTEX_E CFG_FPGA_DEV( 0x2 )
#define CFG_VIRTEX2 CFG_FPGA_DEV( 0x4 ) #define CFG_VIRTEX2 CFG_FPGA_DEV( 0x4 )
#define CFG_SPARTAN3 CFG_FPGA_DEV( 0x8 ) #define CFG_SPARTAN3 CFG_FPGA_DEV( 0x8 )
#define CFG_XILINX_SPARTAN2 (CFG_FPGA_XILINX | CFG_SPARTAN2) #define CFG_XILINX_SPARTAN2 (CFG_FPGA_XILINX | CFG_SPARTAN2)
#define CFG_XILINX_VIRTEX_E (CFG_FPGA_XILINX | CFG_VIRTEX_E) #define CFG_XILINX_VIRTEX_E (CFG_FPGA_XILINX | CFG_VIRTEX_E)
#define CFG_XILINX_VIRTEX2 (CFG_FPGA_XILINX | CFG_VIRTEX2) #define CFG_XILINX_VIRTEX2 (CFG_FPGA_XILINX | CFG_VIRTEX2)
#define CFG_XILINX_SPARTAN3 (CFG_FPGA_XILINX | CFG_SPARTAN3) #define CFG_XILINX_SPARTAN3 (CFG_FPGA_XILINX | CFG_SPARTAN3)
/* XXX - Add new models here */ /* XXX - Add new models here */