Add XTI support
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@2645 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo
parent
544799b3b0
commit
a36f33adf2
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@ -1104,4 +1104,8 @@
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* configs/olimex-str7p11/nettest - examples/nettest configuration using
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the ENC28J60 driver on the Olimex STMicro STR-P711.
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(unverified on original check-in)
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* configs/olimex-str7p11/src/up_enc28j60.c - Add ENC28J60 initialization
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logic.
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* arch/arm/src/str7x/str7x_xti.c - Add basic XTI support (external
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interrupts).
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@ -8,7 +8,7 @@
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<tr align="center" bgcolor="#e4e4e4">
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<td>
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<h1><big><font color="#3c34ec"><i>NuttX RTOS</i></font></big></h1>
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<p>Last Updated: May 1, 2010</p>
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<p>Last Updated: May 2, 2010</p>
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</td>
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</tr>
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</table>
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@ -1686,6 +1686,10 @@ nuttx-5.5 2010-xx-xx Gregory Nutt <spudmonkey@racsa.co.cr>
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* configs/olimex-str7p11/nettest - examples/nettest configuration using
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the ENC28J60 driver on the Olimex STMicro STR-P711.
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(unverified on original check-in)
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* configs/olimex-str7p11/src/up_enc28j60.c - Add ENC28J60 initialization
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logic.
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* arch/arm/src/str7x/str7x_xti.c - Add basic XTI support (external
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interrupts).
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pascal-2.1 2010-xx-xx Gregory Nutt <spudmonkey@racsa.co.cr>
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@ -1,7 +1,7 @@
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/************************************************************************************
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* arch/arm/include/str71x/irq.h
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*
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* Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
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* Copyright (C) 2008-2010 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -52,36 +52,68 @@
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/* IRQ channels */
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#define STR71X_IRQ_T0TIMI (0)
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#define STR71X_IRQ_FLASH (1)
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#define STR71X_IRQ_RCCU (2)
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#define STR71X_IRQ_RTC (3)
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#define STR71X_IRQ_WDG (4)
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#define STR71X_IRQ_XTI (5)
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#define STR71X_IRQ_USBHP (6)
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#define STR71X_IRQ_I2C0ITERR (7)
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#define STR71X_IRQ_I2C1ITERR (8)
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#define STR71X_IRQ_UART0 (9)
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#define STR71X_IRQ_UART1 (10)
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#define STR71X_IRQ_UART2 (11)
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#define STR71X_IRQ_UART3 (12)
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#define STR71X_IRQ_SPI0 (13)
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#define STR71X_IRQ_SPI1 (14)
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#define STR71X_IRQ_I2C0 (15)
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#define STR71X_IRQ_I2C1 (16)
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#define STR71X_IRQ_CAN (17)
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#define STR71X_IRQ_ADC (18)
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#define STR71X_IRQ_T1TIMI (19)
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#define STR71X_IRQ_T2TIMI (20)
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#define STR71X_IRQ_T3TIMI (21)
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#define STR71X_IRQ_HDLC (25)
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#define STR71X_IRQ_USBLP (26)
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#define STR71X_IRQ_T0TOI (29)
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#define STR71X_IRQ_T0OC1 (30)
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#define STR71X_IRQ_T0OC2 (31)
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#define STR71X_IRQ_T0TIMI (0) /* IRQ 0: T0.EFTI Timer 0 global interrupt */
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#define STR71X_IRQ_FLASH (1) /* IRQ 1: FLASH FLASH global interrupt */
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#define STR71X_IRQ_RCCU (2) /* IRQ 2: PRCCU PRCCU global interrupt */
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#define STR71X_IRQ_RTC (3) /* IRQ 3: RTC Real Time Clock global interrupt */
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#define STR71X_IRQ_WDG (4) /* IRQ 4: WDG.IRQ Watchdog timer interrupt */
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#define STR71X_IRQ_XTI (5) /* IRQ 5: XTI.IRQ XTI external interrupt */
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#define STR71X_IRQ_USBHP (6) /* IRQ 6: USB.HPIRQ USB high priority event interrupt */
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#define STR71X_IRQ_I2C0ITERR (7) /* IRQ 7: I2C0.ITERR I2C 0 error interrupt */
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#define STR71X_IRQ_I2C1ITERR (8) /* IRQ 8: I2C1.ITERR I2C 1 error interrupt */
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#define STR71X_IRQ_UART0 (9) /* IRQ 9: UART0.IRQ UART 0 global interrupt */
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#define STR71X_IRQ_UART1 (10) /* IRQ 10: UART1.IRQ UART 1 global interrupt */
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#define STR71X_IRQ_UART2 (11) /* IRQ 11: UART2.IRQ UART 2 global interrupt */
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#define STR71X_IRQ_UART3 (12) /* IRQ 12: UART3.IRQ UART 3 global interrupt */
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#define STR71X_IRQ_SPI0 (13) /* IRQ 13: BSPI0.IRQ BSPI 0 global interrupt */
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#define STR71X_IRQ_SPI1 (14) /* IRQ 14: BSPI1.IRQ BSPI 1 global interrupt */
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#define STR71X_IRQ_I2C0 (15) /* IRQ 15: I2C0.IRQ I2C 0 tx/rx interrupt */
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#define STR71X_IRQ_I2C1 (16) /* IRQ 16: I2C1.IRQ I2C 1 tx/rx interrupt */
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#define STR71X_IRQ_CAN (17) /* IRQ 17: CAN.IRQ CAN module global interrupt */
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#define STR71X_IRQ_ADC (18) /* IRQ 18: ADC.IRQ ADC sample ready interrupt */
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#define STR71X_IRQ_T1TIMI (19) /* IRQ 19: T1.GI Timer 1 global interrupt */
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#define STR71X_IRQ_T2TIMI (20) /* IRQ 20: T2.GI Timer 2 global interrupt */
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#define STR71X_IRQ_T3TIMI (21) /* IRQ 21: T3.GI Timer 3 global interrupt */
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/* IRQ 22-24: Reserved */
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#define STR71X_IRQ_HDLC (25) /* IRQ 25: HDLC.IRQ HDLC global interrupt */
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#define STR71X_IRQ_USBLP (26) /* IRQ 26: USB.LPIRQ USB low priority event interrupt */
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/* IRQ 27-28: Reserved */
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#define STR71X_IRQ_T0TOI (29) /* IRQ 29: T0.TOI Timer 0 Overflow interrupt */
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#define STR71X_IRQ_T0OC1 (30) /* IRQ 30: T0.OCMPA Timer 0 Output Compare A interrupt */
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#define STR71X_IRQ_T0OC2 (31) /* IRQ 31: T0.OCMPB Timer 0 Output Compare B interrupt */
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#define STR71X_NBASEIRQS (32)
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#ifdef CONFIG_STR71X_XTI
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# define STR71X_IRQ_FIRSTXTI (32)
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# define STR71X_IRQ_SW (32) /* Line 0: SW interrupt - no HW connection */
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# define STR71X_IRQ_USBWKUP (33) /* Line 1: USB wake-up event: generated while exiting
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* from suspend mode */
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# define STR71X_IRQ_PORT2p8 (34) /* Line 2: Port 2.8 - External Interrupt */
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# define STR71X_IRQ_PORT2p9 (35) /* Line 3: Port 2.9 - External Interrupt */
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# define STR71X_IRQ_PORT2p10 (36) /* Line 4: Port 2.10 - External Interrupt */
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# define STR71X_IRQ_PORT2p11 (37) /* Line 5: Port 2.11 - External Interrupt */
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# define STR71X_IRQ_PORT1p11 (38) /* Line 6: Port 1.11 - CAN module receive pin (CANRX). */
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# define STR71X_IRQ_PORT1p13 (39) /* Line 7: Port 1.13 - HDLC clock (HCLK) or I2C.0 Clock
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* (I0.SCL) */
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# define STR71X_IRQ_PORT1p14 (40) /* Line 8: Port 1.14 - HDLC receive pin (HRXD) or I2C.0
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* Data (SDA) */
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# define STR71X_IRQ_PORT0p1 (41) /* Line 9: Port 0.1 - BSPI0 Slave Input data (S0.MOSI)
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* or UART3 Receive Data Input (U3.Rx) */
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# define STR71X_IRQ_PORT0p2 (42) /* Line 10: Port 0.2 - BSPI0 Slave Input serial clock
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* (S0.SCLK) or I2C.1 Clock (I1.SCL) */
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# define STR71X_IRQ_PORT0p6 (43) /* Line 11: Port 0.6 - BSPI1 Slave Input serial clock
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* (S1.SCLK) */
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# define STR71X_IRQ_PORT0p8 (44) /* Line 12: Port 0.8 - UART0 Receive Data Input (U0.Rx) */
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# define STR71X_IRQ_PORT0p10 (45) /* Line 13: Port 0.10 - UART1 Receive Data Input (U1.Rx) */
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# define STR71X_IRQ_PORT0p13 (46) /* Line 14: Port 0.13 - UART2 Receive Data Input (U2.Rx) */
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# define STR71X_IRQ_PORT0p15 (47) /* Line 15: Port 0.15 - WAKEUP pin or RTC ALARM */
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# define NR_IRQS (48)
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#else
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# define NR_IRQS (32)
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#endif
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#define STR71X_IRQ_SYSTIMER STR71X_IRQ_T0TIMI
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#define NR_IRQS 32
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/* FIQ channels */
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@ -113,7 +145,7 @@ extern "C" {
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_ARM_INCLUDE_STR71X_IRQ_H */
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@ -54,4 +54,7 @@ CHIP_CSRCS = str71x_prccu.c str71x_lowputc.c str71x_decodeirq.c str71x_irq.c \
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ifeq ($(CONFIG_USBDEV),y)
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CHIP_CSRCS += str71x_usbdev.c
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endif
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ifeq ($(CONFIG_STR71X_XTI),y)
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CHIP_CSRCS += str71x_xti.c
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endif
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@ -42,6 +42,8 @@
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#include <nuttx/config.h>
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#include <stdbool.h>
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#include <arch/board/board.h>
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/************************************************************************************
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@ -92,4 +94,34 @@
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* Public Functions
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************************************************************************************/
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/********************************************************************************
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* Name: str7x_xtiinitialize
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*
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* Description:
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* Configure XTI for operation. Note that the lines are not used as wake-up
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* sources in this implementation. Some extensions would be required for that
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* capability.
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*
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********************************************************************************/
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#ifdef CONFIG_STR71X_XTI
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extern int str7x_xtiinitialize(void);
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#else
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# define str7x_xtiinitialize()
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#endif /* CONFIG_STR71X_XTI */
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/********************************************************************************
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* Name: str7x_xticonfig
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*
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* Description:
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* Configure an external line to provide interrupts.
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*
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********************************************************************************/
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#ifdef CONFIG_STR71X_XTI
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extern int str7x_xticonfig(int irq, bool rising);
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#else
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# define str7x_xticonfig(irq,rising)
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#endif /* CONFIG_STR71X_XTI */
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#endif /* __ARCH_ARM_SRC_STR71X_STR71X_INTERNAL_H */
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@ -0,0 +1,230 @@
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/********************************************************************************
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* arch/arm/src/str71x/str71x_xti.c
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*
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* Copyright (C) 2010 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************************/
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/********************************************************************************
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* Included Files
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********************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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#include <assert.h>
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#include <errno.h>
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#include <debug.h>
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#include <arch/board/board.h>
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#include "chip.h"
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#include "up_arch.h"
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#include "os_internal.h"
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#include "up_internal.h"
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#ifdef CONFIG_STR71X_XTI
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/********************************************************************************
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* Pre-procesor Definitions
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********************************************************************************/
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/********************************************************************************
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* Private Types
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********************************************************************************/
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struct xtiregs_s
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{
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uint32_t mr; /* Mask register */
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uint32_t tr; /* Trigger polarity register */
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};
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/********************************************************************************
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* Public Data
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********************************************************************************/
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static const struct xtiregs_s g_xtiregs[2] =
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{
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{ STR71X_XTI_MRL, STR71X_XTI_TRL },
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{ STR71X_XTI_MRH, STR71X_XTI_TRH }
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};
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/********************************************************************************
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* Private Data
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********************************************************************************/
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/********************************************************************************
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* Private Functions
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********************************************************************************/
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static int str7x_xtiinterrupt(int irq, FAR void *context)
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{
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uint16_t enabled = (uint16_t)getreg8(STR71X_XTI_MRH) << 8 |
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(uint16_t)getreg8(STR71X_XTI_MRL);
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uint16_t pending = (uint16_t)getreg8(STR71X_XTI_PRH) << 8 |
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(uint16_t)getreg8(STR71X_XTI_PRL);
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uint16_t mask;
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/* Clear the interrupts now. This seems unsafe? Couldn't this cause lost
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* interupts?
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*/
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mask = ~pending;
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putreg8(mask >> 8, STR71X_XTI_PRH);
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putreg8(mask & 0xff, STR71X_XTI_PRH);
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/* Then dispatch the interrupts */
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pending &= enabled;
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for (irq = STR71X_IRQ_FIRSTXTI, mask = 0x0001;
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irq < NR_IRQS && pending != 0;
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irq++, mask <<= 1)
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{
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/* Is this interrupt pending? */
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if ((pending & mask) != 0)
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{
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/* Deliver the IRQ */
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irq_dispatch(irq, context);
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pending &= ~mask;
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}
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}
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return OK;
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}
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/********************************************************************************
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* Public Functions
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********************************************************************************/
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/********************************************************************************
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* Name: str7x_xtiinitialize
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*
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* Description:
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* Configure XTI for operation. Note that the lines are not used as wake-up
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* sources in this implementation. Some extensions would be required for that
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* capability.
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*
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********************************************************************************/
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int str7x_xtiinitialize(void)
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{
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int ret;
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/* Mask all interrupts by setting XTI MRH/L to zero */
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putreg8(0, STR71X_XTI_MRH);
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putreg8(0, STR71X_XTI_MRL);
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/* Clear any pending interrupts by setting XTI PRH/L to zero */
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putreg8(0, STR71X_XTI_PRH);
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putreg8(0, STR71X_XTI_PRL);
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/* Attach the XTI interrupt */
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ret = irq_attach(STR71X_IRQ_XTI, str7x_xtiinterrupt);
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if (ret == OK)
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{
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/* Enable the XTI interrupt at the XTI */
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putreg8(STR71X_XTICTRL_ID1S, STR71X_XTI_CTRL);
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/* And enable the XTI interrupt at the interrupt controller */
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up_enable_irq(STR71X_IRQ_XTI);
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}
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return ret;
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}
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/********************************************************************************
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* Name: str7x_xticonfig
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*
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* Description:
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* Configure an external line to provide interrupts.
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*
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********************************************************************************/
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int str7x_xticonfig(int irq, bool rising)
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{
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uint8_t regval;
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int bit;
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int ndx;
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int ret = -EINVAL;
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/* Configure one of the 16 lines as an interrupt source */
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if (irq > STR71X_IRQ_FIRSTXTI && irq <= NR_IRQS)
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{
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/* Decide if we use the lower or upper regiser */
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bit = irq - STR71X_IRQ_FIRSTXTI;
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ndx = 0;
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if (bit > 7)
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{
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/* Select the high register */
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bit -= 8;
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ndx = 1;
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}
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/* Set the rising or trailing edge */
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regval = getreg8(g_xtiregs[ndx].tr);
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if (rising)
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{
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regval |= (1 << bit);
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}
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else
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{
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regval &= ~(1 << bit);
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}
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putreg8(regval, g_xtiregs[ndx].tr);
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/* Enable the interrupt be setting the corresponding mask bit
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* the XTI_MRL/H register.
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*/
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regval = getreg8(g_xtiregs[ndx].mr);
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regval |= (1 << bit);
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putreg8(regval, g_xtiregs[ndx].mr);
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/* Return success */
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||||
ret = OK;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_STR71X_XTI */
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
/************************************************************************************
|
||||
* arch/arm/src/str71x/str71x_xti.h
|
||||
*
|
||||
* Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2008-2010 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
|
|
|
|||
|
|
@ -118,7 +118,7 @@ CONFIG_STR71X_CAN=n
|
|||
CONFIG_STR71X_BSPI0=y
|
||||
CONFIG_STR71X_BSPI1=n
|
||||
CONFIG_STR71X_HDLC=n
|
||||
CONFIG_STR71X_XTI=n
|
||||
CONFIG_STR71X_XTI=y
|
||||
CONFIG_STR71X_GPIO0=y
|
||||
CONFIG_STR71X_GPIO1=y
|
||||
CONFIG_STR71X_GPIO2=n
|
||||
|
|
|
|||
|
|
@ -71,6 +71,7 @@
|
|||
* UART3, I2C cannot be used with SPI0. The GPIOs selected for the ENC28J60
|
||||
* interrupt conflict with TMR1.
|
||||
*/
|
||||
#warning "Need to select differnt interrupt pin.. XTI doesn't support this one"
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
|
|
@ -90,6 +91,7 @@
|
|||
#include "chip.h"
|
||||
#include "up_arch.h"
|
||||
#include "up_internal.h"
|
||||
#include "str71x_internal.h"
|
||||
|
||||
#ifdef CONFIG_NET_ENC28J60
|
||||
|
||||
|
|
@ -105,6 +107,10 @@
|
|||
# error "Need CONFIG_STR71X_BSPI0 in the configuration"
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_STR71X_XTI
|
||||
# error "Need CONFIG_STR71X_XTI in the configuration"
|
||||
#endif
|
||||
|
||||
/* UART3, I2C cannot be used with SPI0. The GPIOs selected for the ENC28J60
|
||||
* interrupt conflict with TIM1.
|
||||
*/
|
||||
|
|
@ -123,7 +129,7 @@
|
|||
#define ENC28J60_DEVNO 0 /* Only one ENC28J60 */
|
||||
#define ENC28J60_IRQ 0 /* NEEDED!!!!!!!!!!!!!!!! */
|
||||
|
||||
/* Debug ********************************************************************/
|
||||
#warning "Eventually need to fix XTI IRQ number!"
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
|
|
@ -148,34 +154,42 @@ void up_netinitialize(void)
|
|||
|
||||
/* Get the SPI port */
|
||||
|
||||
nvdbg("up_netinitialize: Initializing SPI port %d\n", ENC28J60_SPI_PORTNO);
|
||||
nvdbg("Initializing SPI port %d\n", ENC28J60_SPI_PORTNO);
|
||||
|
||||
spi = up_spiinitialize(ENC28J60_SPI_PORTNO);
|
||||
if (!spi)
|
||||
{
|
||||
ndbg("up_netinitialize: Failed to initialize SPI port %d\n",
|
||||
ndbg("Failed to initialize SPI port %d\n",
|
||||
ENC28J60_SPI_PORTNO);
|
||||
return;
|
||||
}
|
||||
|
||||
nvdbg("up_netinitialize: Successfully initialized SPI port %d\n",
|
||||
/* Configure the XTI for the ENC28J60 interrupt. */
|
||||
|
||||
ret = str7x_xticonfig(ENC28J60_IRQ, false);
|
||||
if (ret < 0)
|
||||
{
|
||||
ndbg("Failed configure interrupt for IRQ %d: %d\n", ENC28J60_IRQ, ret);
|
||||
return;
|
||||
}
|
||||
|
||||
nvdbg("Successfully initialized SPI port %d\n",
|
||||
ENC28J60_SPI_PORTNO);
|
||||
|
||||
/* Bind the SPI port to the ENC28J60 driver */
|
||||
|
||||
nvdbg("up_netinitialize: Binding SPI port %d to ENC28J60 device %d\n",
|
||||
nvdbg("Binding SPI port %d to ENC28J60 device %d\n",
|
||||
ENC28J60_SPI_PORTNO, ENC28J60_DEVNO);
|
||||
|
||||
#warning "Need to implement IRQ interrupt before we can use this"
|
||||
ret = enc_initialize(spi, ENC28J60_DEVNO, ENC28J60_IRQ);
|
||||
if (ret < 0)
|
||||
{
|
||||
ndbg("up_netinitialize: Failed to bind SPI port %d ENC28J60 device %d: %d\n",
|
||||
ndbg("Failed to bind SPI port %d ENC28J60 device %d: %d\n",
|
||||
ENC28J60_SPI_PORTNO, ENC28J60_DEVNO, ret);
|
||||
return;
|
||||
}
|
||||
|
||||
nvdbg("up_netinitialize: Successfuly bound SPI port %d ENC28J60 device %d\n",
|
||||
nvdbg("Successfuly bound SPI port %d ENC28J60 device %d\n",
|
||||
ENC28J60_SPI_PORTNO, ENC28J60_DEVNO);
|
||||
}
|
||||
#endif /* CONFIG_NET_ENC28J60 */
|
||||
|
|
|
|||
Loading…
Reference in New Issue