Mirtoo update
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4860 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo
parent
1f611da86e
commit
606ac72441
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@ -189,7 +189,7 @@ static void pic32mx_uartsetbaud(uintptr_t uart_base, uint32_t baudrate)
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if (brg > 65536)
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{
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/* Nope, too big.. try BRGH=1 */
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/* Nope, too big.. try BRGH=0 */
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brg = (tmp + 8) >> 4;
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mode = PIC32MX_UART_MODECLR_OFFSET;
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@ -194,7 +194,11 @@
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#define UART_MODE_RTSMD (1 << 11) /* Bit 11: Mode selection for ~UxRTS pin */
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#define UART_MODE_IREN (1 << 12) /* Bit 12: IrDA encoder and decoder enable */
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#define UART_MODE_SIDL (1 << 13) /* Bit 13: Stop in idle mode */
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#if !defined(CHIP_PIC32MX1) && !defined(CHIP_PIC32MX2)
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# define UART_MODE_FRZ (1 << 14) /* Bit 14: Freeze in debug exception mode */
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#endif
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#define UART_MODE_ON (1 << 15) /* Bit 15: UARTx enable */
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/* UARTx status and control register */
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@ -12,6 +12,7 @@ Contents
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Toolchains
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Loading NuttX with ICD3
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LED Usage
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UART Usage
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PIC32MX Configuration Options
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Configurations
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@ -442,6 +443,29 @@ LED Usage
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LED_ASSERTION 4 ON N/C OFF N/C
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LED_PANIC 4 ON N/C OFF N/C
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UART Usage
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==========
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When mounted on the DTX1-4000L EV-kit1 board, serial output is avaiable through
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an FT230X device via the FUNC0 and FUNC1 module outputs. If CONFIG_PIC32MX_UART2
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is enabled, the src/up_boot will configure the UART2 pins as follows:
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---------- ------ ----- ------ -------------------------
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BOARD MODULE PIN SIGNAL NOTES
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---------- ------ ----- ------ -------------------------
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FT230X RXD FUNC0 RPB11 U2RX UART2 RX (Also PGEC2)
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FT230X TXD FUNC1 RPB10 U2TX UART2 TX (Also PGED2)
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If CONFIG_PIC32MX_UART1 is enabled, the src/up_boot will configure the UART
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pins as follows. This will support communictions (via an external RS-232
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driver) through X3 pins 4 and 5:
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---------- ------ ----- ------ -------------------------
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BOARD MODULE PIN SIGNAL NOTES
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---------- ------ ----- ------ -------------------------
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X3, pin 4 FUNC4 RPBC5 U1TX UART1 TX
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X3, pin 5 FUNC5 RPBC6 U1RX UART1 RX
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PIC32MX Configuration Options
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=============================
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@ -79,13 +79,13 @@ ifeq ($(WINTOOL),y)
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MKDEP = $(TOPDIR)/tools/mknulldeps.sh
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ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
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ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
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ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/ostest/ld.script}"
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ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/ostest/debug.ld}"
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else
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# Linux/Cygwin-native toolchain
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MKDEP = $(TOPDIR)/tools/mkdeps.sh
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ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
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ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
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ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/ostest/ld.script
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ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/ostest/debug.ld
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endif
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CC = $(CROSSDEV)gcc
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@ -0,0 +1,313 @@
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/****************************************************************************
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* configs/mirtoo/ostest/ld.script
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*
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* Copyright (C) 2012 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/* Memory Regions ***********************************************************/
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MEMORY
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{
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/* The PIC32MX250F128D has 128Kb of program FLASH at physical address
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* 0x1d000000 but is always accessed at KSEG0 address 0x9d00:0000
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*/
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kseg0_progmem (rx) : ORIGIN = 0x9d000000, LENGTH = 128K
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/* The PIC32MX250F128D has 3Kb of boot FLASH at physical addresses
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* 0x1fc00000-0x1fc00c00. The initial reset vector is in KSEG1, but
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* all other accesses are in KSEG0.
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*
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* REGION PHYSICAL KSEG SIZE
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* DESCRIPTION START ADDR (BYTES)
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* --------------- ---------- ------ ----------------------
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* Exceptions:*
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* Reset 0x1fc00000 KSEG1 384 384 (0.375Kb)
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* Gen exception 0x1fc00000 KSEG1 128 512 (0.500Kb)
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* TLB Refill 0x1fc00200 KSEG1 256 768 (0.750Kb)
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* Cache Error 0x1fc00300 KSEG1 128 896 (0.875Kb)
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* Others 0x1fc00380 KSEG1 128 1024 (1.000Kb)
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* Interrupt 0x1fc00400 KSEG1 128 1152 (1.125Kb)
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* Debug code 0x1fc00480 KSEG1 3072-1152-16 3056 (2.984Kb)
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* DEVCFG3-0 0x1fc00bf0 KSEG1 16 3072 (3Kb)
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*
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* Exceptions assume:
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*
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* STATUS: BEV=0/1 and EXL=0
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* CAUSE: IV=1
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* JTAG: ProbEn=0
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* And multi-vector support disabled
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*/
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kseg1_reset (rx) : ORIGIN = 0xbfc00000, LENGTH = 384
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kseg1_genexcpt (rx) : ORIGIN = 0xbfc00180, LENGTH = 128
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kseg1_ebexcpt (rx) : ORIGIN = 0xbfc00200, LENGTH = 256
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kseg1_cacherr (rx) : ORIGIN = 0xbfc00300, LENGTH = 128
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kseg1_bevexcpt (rx) : ORIGIN = 0xbfc00380, LENGTH = 128
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kseg1_intexcpt (rx) : ORIGIN = 0xbfc00400, LENGTH = 128
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kseg1_dbgexcpt (rx) : ORIGIN = 0xbfc00480, LENGTH = 3072-1152-16
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kseg1_devcfg (r) : ORIGIN = 0xbfc00bf0, LENGTH = 16
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/* The PIC32MX250F128D has 32Kb of data memory at physical address
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* 0x00000000. Since the PIC32MX has no data cache, this memory is
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* always accessed through KSEG1.
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*
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* NOTE: When used with MPLAB, we need to set aside 512 bytes of memory
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* at the beginning of this region for use by MPLAB.
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*/
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kseg1_datamem (w!x) : ORIGIN = 0xa0000200, LENGTH = 32K - 512
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}
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OUTPUT_FORMAT("elf32-tradlittlemips")
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OUTPUT_ARCH(pic32mx)
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ENTRY(__start)
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SECTIONS
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{
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/* Boot FLASH sections */
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.reset :
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{
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KEEP (*(.reset))
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} > kseg1_reset
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/* Exception handlers. The following is assumed:
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*
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* STATUS: BEV=1 and EXL=0
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* CAUSE: IV=1
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* JTAG: ProbEn=0
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* And multi-vector support disabled
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*
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* In that configuration, the vector locations become:
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*
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* Reset, Soft Reset bfc0:0000
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* TLB Refill bfc0:0200
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* Cache Error bfc0:0300
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* All others bfc0:0380
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* Interrupt bfc0:0400
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* EJTAG Debug bfc0:0480
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*/
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/* KSEG1 exception handler "trampolines" */
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.gen_excpt :
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{
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KEEP (*(.gen_excpt))
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} > kseg1_genexcpt
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.ebase_excpt :
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{
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KEEP (*(.ebase_excpt))
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} > kseg1_ebexcpt
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.bev_excpt :
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{
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KEEP (*(.bev_excpt))
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} > kseg1_bevexcpt
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.int_excpt :
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{
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KEEP (*(.int_excpt))
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} > kseg1_intexcpt
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.dbg_excpt = ORIGIN(kseg1_dbgexcpt);
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.devcfg :
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{
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KEEP (*(.devcfg))
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} > kseg1_devcfg
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/* Program FLASH sections */
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.start :
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{
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/* KSEG0 Reset startup logic */
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*(.start)
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/* KSEG0 exception handlers */
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*(.nmi_handler)
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*(.bev_handler)
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*(.int_handler)
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} > kseg0_progmem
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.text :
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{
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_stext = ABSOLUTE(.);
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*(.text .text.*)
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*(.stub)
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KEEP (*(.text.*personality*))
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*(.gnu.linkonce.t.*)
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*(.gnu.warning)
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*(.mips16.fn.*)
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*(.mips16.call.*)
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/* Read-only data is included in the text section */
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*(.rodata .rodata.*)
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*(.rodata1)
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*(.gnu.linkonce.r.*)
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/* Small initialized constant global and static data */
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*(.sdata2 .sdata2.*)
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*(.gnu.linkonce.s2.*)
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/* Uninitialized constant global and static data */
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*(.sbss2 .sbss2.*)
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*(.gnu.linkonce.sb2.*)
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_etext = ABSOLUTE(.);
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} > kseg0_progmem
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/* Initialization data begins here in progmem */
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_data_loaddr = LOADADDR(.data);
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.eh_frame_hdr : { *(.eh_frame_hdr) }
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.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
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/* RAM functions are positioned at the beginning of RAM so that
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* they can be guaranteed to satisfy the 2Kb alignment requirement.
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*/
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/* This causes failures if there are no RAM functions
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.ramfunc ALIGN(2K) :
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{
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_sramfunc = ABSOLUTE(.);
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*(.ramfunc .ramfunc.*)
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_eramfunc = ABSOLUTE(.);
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} > kseg1_datamem AT > kseg0_progmem
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_ramfunc_loadaddr = LOADADDR(.ramfunc);
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_ramfunc_sizeof = SIZEOF(.ramfunc);
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_bmxdkpba_address = _sramfunc - ORIGIN(kseg1_datamem) ;
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_bmxdudba_address = LENGTH(kseg1_datamem) ;
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_bmxdupba_address = LENGTH(kseg1_datamem) ;
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*/
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.data :
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{
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_sdata = ABSOLUTE(.);
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*(.data .data.*)
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*(.gnu.linkonce.d.*)
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KEEP (*(.gnu.linkonce.d.*personality*))
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*(.data1)
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} > kseg1_datamem AT > kseg0_progmem
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.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) }
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_gp = ALIGN(16) + 0x7FF0 ;
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.got :
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{
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*(.got.plt) *(.got)
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} > kseg1_datamem AT > kseg0_progmem
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.sdata :
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{
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*(.sdata .sdata.* .gnu.linkonce.s.*)
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} > kseg1_datamem AT > kseg0_progmem
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.lit8 :
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{
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*(.lit8)
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} > kseg1_datamem AT > kseg0_progmem
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.lit4 :
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{
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*(.lit4)
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_edata = ABSOLUTE(.);
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} >kseg1_datamem AT>kseg0_progmem
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.sbss :
|
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{
|
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_sbss = ABSOLUTE(.);
|
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*(.dynsbss)
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*(.sbss .sbss.* .gnu.linkonce.sb.*)
|
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*(.scommon)
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} >kseg1_datamem
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.bss :
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{
|
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*(.dynbss)
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*(.bss .bss.*)
|
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*(.gnu.linkonce.b.*)
|
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*(COMMON)
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_ebss = ABSOLUTE(.);
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} > kseg1_datamem
|
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|
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/* Stabs debugging sections */
|
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|
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.stab 0 : { *(.stab) }
|
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.stabstr 0 : { *(.stabstr) }
|
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.stab.excl 0 : { *(.stab.excl) }
|
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.stab.exclstr 0 : { *(.stab.exclstr) }
|
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.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
|
||||
/* DWARF debug sections */
|
||||
/* DWARF 1 */
|
||||
|
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.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
|
||||
/* GNU DWARF 1 extensions */
|
||||
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
|
||||
/* DWARF 1.1 and DWARF 2 */
|
||||
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
|
||||
/* DWARF 2 */
|
||||
|
||||
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
|
||||
/* SGI/MIPS DWARF 2 extensions */
|
||||
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
|
||||
/DISCARD/ : { *(.note.GNU-stack) }
|
||||
}
|
||||
|
|
@ -55,6 +55,9 @@
|
|||
* Definitions
|
||||
************************************************************************************/
|
||||
|
||||
#define GPIO_U1TX (GPIO_OUTPUT|GPIO_PORTC|GPIO_PIN5)
|
||||
#define GPIO_U1RX (GPIO_INPUT|GPIO_PORTC|GPIO_PIN6)
|
||||
|
||||
#define GPIO_U2TX (GPIO_OUTPUT|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_U2RX (GPIO_INPUT|GPIO_PORTB|GPIO_PIN11)
|
||||
|
||||
|
|
@ -67,7 +70,8 @@
|
|||
*
|
||||
* Description:
|
||||
* When mounted on the DTX1-4000L EV-kit1 board, serial output is avaiable through
|
||||
* an FT230X device via the FUNC0 and FUNC1 module outputs
|
||||
* an FT230X device via the FUNC0 and FUNC1 module outputs. If CONFIG_PIC32MX_UART2
|
||||
* is enabled, the src/up_boot will configure the UART2 pins as follows.
|
||||
*
|
||||
* ---------- ------ ----- ------ -------------------------
|
||||
* BOARD OUTPUT PIN SIGNAL NOTES
|
||||
|
|
@ -75,6 +79,16 @@
|
|||
* FT230X RXD FUNC0 RPB11 U2RX UART2 RX (Also PGEC2)
|
||||
* FT230X TXD FUNC1 RPB10 U2TX UART2 TX (Also PGED2)
|
||||
*
|
||||
* If CONFIG_PIC32MX_UART1 is enabled, the src/up_boot will configure the UART
|
||||
* pins as follows. This will support communictions (via an external RS-232
|
||||
* driver) through X3 pins 4 and 5:
|
||||
*
|
||||
* ---------- ------ ----- ------ -------------------------
|
||||
* BOARD MODULE PIN SIGNAL NOTES
|
||||
* ---------- ------ ----- ------ -------------------------
|
||||
* X3, pin 4 FUNC4 RPBC5 U1TX UART1 TX
|
||||
* X3, pin 5 FUNC5 RPBC6 U1RX UART1 RX
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
static inline void pic32mx_uartinitialize(void)
|
||||
|
|
@ -92,6 +106,20 @@ static inline void pic32mx_uartinitialize(void)
|
|||
putreg32(PPS_INSEL_RPB11, PIC32MX_PPS_U2RXR);
|
||||
putreg32(PPS_OUTSEL_U2TX, PIC32MX_PPS_RPB10R);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PIC32MX_UART1
|
||||
/* Make sure that TRIS pins are set correctly. Configure the UART pins as digital
|
||||
* inputs and outputs first.
|
||||
*/
|
||||
|
||||
pic32mx_configgpio(GPIO_U1TX);
|
||||
pic32mx_configgpio(GPIO_U1RX);
|
||||
|
||||
/* Configure UART TX and RX pins to RPB10 and 11, respectively */
|
||||
|
||||
putreg32(PPS_INSEL_RPC6, PIC32MX_PPS_U1RXR);
|
||||
putreg32(PPS_OUTSEL_U1TX, PIC32MX_PPS_RPC5R);
|
||||
#endif
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
|
|
|
|||
Loading…
Reference in New Issue