Add LPC43 GPIO interrupt configurtion logic
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4913 7fd9a85b-ad96-42d3-883c-3090e2eb8679
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patacongo
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@ -50,64 +50,40 @@
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/* Pin interrupt registers (relative to LPC43_GPIOINT_BASE) */
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#define LPC43_GPIOINT_ISEL_OFFSET 0x000 /* Pin Interrupt Mode register */
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#define LPC43_GPIOINT_IENR_OFFSET 0x004 /* Pin interrupt level (rising edge) interrupt enable register */
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#define LPC43_GPIOINT_SIENR_OFFSET 0x008 /* Pin interrupt level (rising edge) interrupt set register */
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#define LPC43_GPIOINT_CIENR_OFFSET 0x00c /* Pin interrupt level (rising edge interrupt) clear register */
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#define LPC43_GPIOINT_IENF_OFFSET 0x010 /* Pin interrupt active level (falling edge) interrupt enable register */
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#define LPC43_GPIOINT_SIENF_OFFSET 0x014 /* Pin interrupt active level (falling edge) interrupt set register */
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#define LPC43_GPIOINT_CIENF_OFFSET 0x018 /* Pin interrupt active level (falling edge) interrupt clear register */
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#define LPC43_GPIOINT_RISE_OFFSET 0x01c /* Pin interrupt rising edge register */
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#define LPC43_GPIOINT_FALL_OFFSET 0x020 /* Pin interrupt falling edge register */
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#define LPC43_GPIOINT_IST_OFFSET 0x024 /* Pin interrupt status register */
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#define LPC43_GPIOINT_ISEL_OFFSET 0x0000 /* Pin Interrupt Mode register */
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#define LPC43_GPIOINT_IENR_OFFSET 0x0004 /* Pin interrupt level (rising edge) interrupt enable register */
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#define LPC43_GPIOINT_SIENR_OFFSET 0x0008 /* Pin interrupt level (rising edge) interrupt set register */
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#define LPC43_GPIOINT_CIENR_OFFSET 0x000c /* Pin interrupt level (rising edge interrupt) clear register */
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#define LPC43_GPIOINT_IENF_OFFSET 0x0010 /* Pin interrupt active level (falling edge) interrupt enable register */
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#define LPC43_GPIOINT_SIENF_OFFSET 0x0014 /* Pin interrupt active level (falling edge) interrupt set register */
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#define LPC43_GPIOINT_CIENF_OFFSET 0x0018 /* Pin interrupt active level (falling edge) interrupt clear register */
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#define LPC43_GPIOINT_RISE_OFFSET 0x001c /* Pin interrupt rising edge register */
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#define LPC43_GPIOINT_FALL_OFFSET 0x0020 /* Pin interrupt falling edge register */
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#define LPC43_GPIOINT_IST_OFFSET 0x0024 /* Pin interrupt status register */
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/* GPIO GROUP0 interrupt registers (relative to LPC43_GRP0INT_BASE) */
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/* GPIO GROUP interrupt registers (relative to either LPC43_GRP0INT_BASE or LPC43_GRP1INT_BASE) */
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#define LPC43_GRP0INT_CTRL_OFFSET 0x000 /* GPIO grouped interrupt control register */
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#define LPC43_GRPINT_CTRL_OFFSET 0x0000 /* GPIO grouped interrupt control register */
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#define LPC43_GRP0INT_POL_OFFSET(p) (0x020 + ((p) << 2 ))
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#define LPC43_GRP0INT_POL0_OFFSET 0x020 /* GPIO grouped interrupt port 0 polarity register */
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#define LPC43_GRP0INT_POL1_OFFSET 0x024 /* GPIO grouped interrupt port 1 polarity register */
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#define LPC43_GRP0INT_POL2_OFFSET 0x028 /* GPIO grouped interrupt port 2 polarity register */
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#define LPC43_GRP0INT_POL3_OFFSET 0x02c /* GPIO grouped interrupt port 3 polarity register */
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#define LPC43_GRP0INT_POL4_OFFSET 0x030 /* GPIO grouped interrupt port 4 polarity register */
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#define LPC43_GRP0INT_POL5_OFFSET 0x034 /* GPIO grouped interrupt port 5 polarity register */
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#define LPC43_GRP0INT_POL6_OFFSET 0x038 /* GPIO grouped interrupt port 6 polarity register */
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#define LPC43_GRP0INT_POL7_OFFSET 0x03c /* GPIO grouped interrupt port 7 polarity register */
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#define LPC43_GRPINT_POL_OFFSET(p) (0x0020 + ((p) << 2 ))
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#define LPC43_GRPINT_POL0_OFFSET 0x0020 /* GPIO grouped interrupt port 0 polarity register */
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#define LPC43_GRPINT_POL1_OFFSET 0x0024 /* GPIO grouped interrupt port 1 polarity register */
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#define LPC43_GRPINT_POL2_OFFSET 0x0028 /* GPIO grouped interrupt port 2 polarity register */
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#define LPC43_GRPINT_POL3_OFFSET 0x002c /* GPIO grouped interrupt port 3 polarity register */
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#define LPC43_GRPINT_POL4_OFFSET 0x0030 /* GPIO grouped interrupt port 4 polarity register */
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#define LPC43_GRPINT_POL5_OFFSET 0x0034 /* GPIO grouped interrupt port 5 polarity register */
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#define LPC43_GRPINT_POL6_OFFSET 0x0038 /* GPIO grouped interrupt port 6 polarity register */
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#define LPC43_GRPINT_POL7_OFFSET 0x003c /* GPIO grouped interrupt port 7 polarity register */
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#define LPC43_GRP0INT_ENA_OFFSET(p) (0x040 + ((p) << 2 ))
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#define LPC43_GRP0INT_ENA0_OFFSET 0x040 /* GPIO grouped interrupt port 0 enable register */
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#define LPC43_GRP0INT_ENA1_OFFSET 0x044 /* GPIO grouped interrupt port 1 enable register */
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#define LPC43_GRP0INT_ENA2_OFFSET 0x048 /* GPIO grouped interrupt port 2 enable register */
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#define LPC43_GRP0INT_ENA3_OFFSET 0x04c /* GPIO grouped interrupt port 3 enable register */
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#define LPC43_GRP0INT_ENA4_OFFSET 0x050 /* GPIO grouped interrupt port 4 enable register */
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#define LPC43_GRP0INT_ENA5_OFFSET 0x054 /* GPIO grouped interrupt port 5 enable register */
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#define LPC43_GRP0INT_ENA6_OFFSET 0x058 /* GPIO grouped interrupt port 5 enable register */
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#define LPC43_GRP0INT_ENA7_OFFSET 0x05c /* GPIO grouped interrupt port 5 enable register */
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/* GPIO GROUP1 interrupt registers (relative to LPC43_GRP1INT_BASE) */
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#define LPC43_GRP1INT_CTRL_OFFSET 0x000 /* GPIO grouped interrupt control register */
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#define LPC43_GRP1INT_POL_OFFSET(p) (0x020 + ((p) << 2 ))
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#define LPC43_GRP1INT_POL0_OFFSET 0x020 /* GPIO grouped interrupt port 0 polarity register */
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#define LPC43_GRP1INT_POL1_OFFSET 0x024 /* GPIO grouped interrupt port 1 polarity register */
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#define LPC43_GRP1INT_POL2_OFFSET 0x028 /* GPIO grouped interrupt port 2 polarity register */
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#define LPC43_GRP1INT_POL3_OFFSET 0x02c /* GPIO grouped interrupt port 3 polarity register */
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#define LPC43_GRP1INT_POL4_OFFSET 0x030 /* GPIO grouped interrupt port 4 polarity register */
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#define LPC43_GRP1INT_POL5_OFFSET 0x034 /* GPIO grouped interrupt port 5 polarity register */
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#define LPC43_GRP1INT_POL6_OFFSET 0x038 /* GPIO grouped interrupt port 6 polarity register */
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#define LPC43_GRP1INT_POL7_OFFSET 0x03c /* GPIO grouped interrupt port 7 polarity register */
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#define LPC43_GRP1INT_ENA_OFFSET(p) (0x040 + ((p) << 2 ))
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#define LPC43_GRP1INT_ENA0_OFFSET 0x040 /* GPIO grouped interrupt port 0 enable register */
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#define LPC43_GRP1INT_ENA1_OFFSET 0x044 /* GPIO grouped interrupt port 1 enable register */
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#define LPC43_GRP1INT_ENA2_OFFSET 0x048 /* GPIO grouped interrupt port 2 enable register */
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#define LPC43_GRP1INT_ENA3_OFFSET 0x04c /* GPIO grouped interrupt port 3 enable register */
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#define LPC43_GRP1INT_ENA4_OFFSET 0x050 /* GPIO grouped interrupt port 4 enable register */
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#define LPC43_GRP1INT_ENA5_OFFSET 0x054 /* GPIO grouped interrupt port 5 enable register */
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#define LPC43_GRP1INT_ENA6_OFFSET 0x058 /* GPIO grouped interrupt port 5 enable register */
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#define LPC43_GRP1INT_ENA7_OFFSET 0x05c /* GPIO grouped interrupt port 5 enable register */
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#define LPC43_GRPINT_ENA_OFFSET(p) (0x0040 + ((p) << 2 ))
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#define LPC43_GRPINT_ENA0_OFFSET 0x0040 /* GPIO grouped interrupt port 0 enable register */
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#define LPC43_GRPINT_ENA1_OFFSET 0x0044 /* GPIO grouped interrupt port 1 enable register */
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#define LPC43_GRPINT_ENA2_OFFSET 0x0048 /* GPIO grouped interrupt port 2 enable register */
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#define LPC43_GRPINT_ENA3_OFFSET 0x004c /* GPIO grouped interrupt port 3 enable register */
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#define LPC43_GRPINT_ENA4_OFFSET 0x0050 /* GPIO grouped interrupt port 4 enable register */
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#define LPC43_GRPINT_ENA5_OFFSET 0x0054 /* GPIO grouped interrupt port 5 enable register */
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#define LPC43_GRPINT_ENA6_OFFSET 0x0058 /* GPIO grouped interrupt port 5 enable register */
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#define LPC43_GRPINT_ENA7_OFFSET 0x005c /* GPIO grouped interrupt port 5 enable register */
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/* GPIO Port Registers (relative to LPC43_GPIO_BASE) */
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/* GPIO GROUP0 interrupt registers (relative to LPC43_GRP0INT_BASE) */
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#define LPC43_GRP0INT_CTRL (LPC43_GRP0INT_BASE+LPC43_GRP0INT_CTRL_OFFSET)
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#define LPC43_GRP0INT_CTRL (LPC43_GRP0INT_BASE+LPC43_GRPINT_CTRL_OFFSET)
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#define LPC43_GRP0INT_POL(p) (LPC43_GRP0INT_BASE+LPC43_GRP0INT_POL_OFFSET(p))
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#define LPC43_GRP0INT_POL0 (LPC43_GRP0INT_BASE+LPC43_GRP0INT_POL0_OFFSET)
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#define LPC43_GRP0INT_POL1 (LPC43_GRP0INT_BASE+LPC43_GRP0INT_POL1_OFFSET)
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#define LPC43_GRP0INT_POL2 (LPC43_GRP0INT_BASE+LPC43_GRP0INT_POL2_OFFSET)
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#define LPC43_GRP0INT_POL3 (LPC43_GRP0INT_BASE+LPC43_GRP0INT_POL3_OFFSET)
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#define LPC43_GRP0INT_POL4 (LPC43_GRP0INT_BASE+LPC43_GRP0INT_POL4_OFFSET)
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#define LPC43_GRP0INT_POL5 (LPC43_GRP0INT_BASE+LPC43_GRP0INT_POL5_OFFSET)
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#define LPC43_GRP0INT_POL6 (LPC43_GRP0INT_BASE+LPC43_GRP0INT_POL6_OFFSET)
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#define LPC43_GRP0INT_POL7 (LPC43_GRP0INT_BASE+LPC43_GRP0INT_POL7_OFFSET)
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#define LPC43_GRP0INT_POL(p) (LPC43_GRP0INT_BASE+LPC43_GRPINT_POL_OFFSET(p))
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#define LPC43_GRP0INT_POL0 (LPC43_GRP0INT_BASE+LPC43_GRPINT_POL0_OFFSET)
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#define LPC43_GRP0INT_POL1 (LPC43_GRP0INT_BASE+LPC43_GRPINT_POL1_OFFSET)
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#define LPC43_GRP0INT_POL2 (LPC43_GRP0INT_BASE+LPC43_GRPINT_POL2_OFFSET)
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#define LPC43_GRP0INT_POL3 (LPC43_GRP0INT_BASE+LPC43_GRPINT_POL3_OFFSET)
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#define LPC43_GRP0INT_POL4 (LPC43_GRP0INT_BASE+LPC43_GRPINT_POL4_OFFSET)
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#define LPC43_GRP0INT_POL5 (LPC43_GRP0INT_BASE+LPC43_GRPINT_POL5_OFFSET)
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#define LPC43_GRP0INT_POL6 (LPC43_GRP0INT_BASE+LPC43_GRPINT_POL6_OFFSET)
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#define LPC43_GRP0INT_POL7 (LPC43_GRP0INT_BASE+LPC43_GRPINT_POL7_OFFSET)
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#define LPC43_GRP0INT_ENA(p) (LPC43_GRP0INT_BASE+LPC43_GRP0INT_ENA_OFFSET(p))
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#define LPC43_GRP0INT_ENA0 (LPC43_GRP0INT_BASE+LPC43_GRP0INT_ENA0_OFFSET)
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#define LPC43_GRP0INT_ENA1 (LPC43_GRP0INT_BASE+LPC43_GRP0INT_ENA1_OFFSET)
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#define LPC43_GRP0INT_ENA2 (LPC43_GRP0INT_BASE+LPC43_GRP0INT_ENA2_OFFSET)
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#define LPC43_GRP0INT_ENA3 (LPC43_GRP0INT_BASE+LPC43_GRP0INT_ENA3_OFFSET)
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#define LPC43_GRP0INT_ENA4 (LPC43_GRP0INT_BASE+LPC43_GRP0INT_ENA4_OFFSET)
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#define LPC43_GRP0INT_ENA5 (LPC43_GRP0INT_BASE+LPC43_GRP0INT_ENA5_OFFSET)
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#define LPC43_GRP0INT_ENA6 (LPC43_GRP0INT_BASE+LPC43_GRP0INT_ENA6_OFFSET)
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#define LPC43_GRP0INT_ENA7 (LPC43_GRP0INT_BASE+LPC43_GRP0INT_ENA7_OFFSET)
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#define LPC43_GRP0INT_ENA(p) (LPC43_GRP0INT_BASE+LPC43_GRPINT_ENA_OFFSET(p))
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#define LPC43_GRP0INT_ENA0 (LPC43_GRP0INT_BASE+LPC43_GRPINT_ENA0_OFFSET)
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#define LPC43_GRP0INT_ENA1 (LPC43_GRP0INT_BASE+LPC43_GRPINT_ENA1_OFFSET)
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#define LPC43_GRP0INT_ENA2 (LPC43_GRP0INT_BASE+LPC43_GRPINT_ENA2_OFFSET)
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#define LPC43_GRP0INT_ENA3 (LPC43_GRP0INT_BASE+LPC43_GRPINT_ENA3_OFFSET)
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#define LPC43_GRP0INT_ENA4 (LPC43_GRP0INT_BASE+LPC43_GRPINT_ENA4_OFFSET)
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#define LPC43_GRP0INT_ENA5 (LPC43_GRP0INT_BASE+LPC43_GRPINT_ENA5_OFFSET)
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#define LPC43_GRP0INT_ENA6 (LPC43_GRP0INT_BASE+LPC43_GRPINT_ENA6_OFFSET)
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#define LPC43_GRP0INT_ENA7 (LPC43_GRP0INT_BASE+LPC43_GRPINT_ENA7_OFFSET)
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/* GPIO GROUP1 interrupt registers (relative to LPC43_GRP1INT_BASE) */
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#define LPC43_GRP1INT_CTRL (LPC43_GRP1INT_BASE+LPC43_GRP1INT_CTRL_OFFSET)
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#define LPC43_GRP1INT_CTRL (LPC43_GRP1INT_BASE+LPC43_GRPINT_CTRL_OFFSET)
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#define LPC43_GRP1INT_POL(p) (LPC43_GRP1INT_BASE+LPC43_GRP1INT_POL_OFFSET(p))
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#define LPC43_GRP1INT_POL0 (LPC43_GRP1INT_BASE+LPC43_GRP1INT_POL0_OFFSET)
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#define LPC43_GRP1INT_POL1 (LPC43_GRP1INT_BASE+LPC43_GRP1INT_POL1_OFFSET)
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#define LPC43_GRP1INT_POL2 (LPC43_GRP1INT_BASE+LPC43_GRP1INT_POL2_OFFSET)
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#define LPC43_GRP1INT_POL3 (LPC43_GRP1INT_BASE+LPC43_GRP1INT_POL3_OFFSET)
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#define LPC43_GRP1INT_POL4 (LPC43_GRP1INT_BASE+LPC43_GRP1INT_POL4_OFFSET)
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#define LPC43_GRP1INT_POL5 (LPC43_GRP1INT_BASE+LPC43_GRP1INT_POL5_OFFSET)
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#define LPC43_GRP1INT_POL6 (LPC43_GRP1INT_BASE+LPC43_GRP1INT_POL6_OFFSET)
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#define LPC43_GRP1INT_POL7 (LPC43_GRP1INT_BASE+LPC43_GRP1INT_POL7_OFFSET)
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#define LPC43_GRP1INT_POL(p) (LPC43_GRP1INT_BASE+LPC43_GRPINT_POL_OFFSET(p))
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#define LPC43_GRP1INT_POL0 (LPC43_GRP1INT_BASE+LPC43_GRPINT_POL0_OFFSET)
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#define LPC43_GRP1INT_POL1 (LPC43_GRP1INT_BASE+LPC43_GRPINT_POL1_OFFSET)
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#define LPC43_GRP1INT_POL2 (LPC43_GRP1INT_BASE+LPC43_GRPINT_POL2_OFFSET)
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#define LPC43_GRP1INT_POL3 (LPC43_GRP1INT_BASE+LPC43_GRPINT_POL3_OFFSET)
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#define LPC43_GRP1INT_POL4 (LPC43_GRP1INT_BASE+LPC43_GRPINT_POL4_OFFSET)
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#define LPC43_GRP1INT_POL5 (LPC43_GRP1INT_BASE+LPC43_GRPINT_POL5_OFFSET)
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#define LPC43_GRP1INT_POL6 (LPC43_GRP1INT_BASE+LPC43_GRPINT_POL6_OFFSET)
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#define LPC43_GRP1INT_POL7 (LPC43_GRP1INT_BASE+LPC43_GRPINT_POL7_OFFSET)
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#define LPC43_GRP1INT_ENA(p) (LPC43_GRP1INT_BASE+LPC43_GRP1INT_ENA_OFFSET(p))
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#define LPC43_GRP1INT_ENA0 (LPC43_GRP1INT_BASE+LPC43_GRP1INT_ENA0_OFFSET)
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#define LPC43_GRP1INT_ENA1 (LPC43_GRP1INT_BASE+LPC43_GRP1INT_ENA1_OFFSET)
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#define LPC43_GRP1INT_ENA2 (LPC43_GRP1INT_BASE+LPC43_GRP1INT_ENA2_OFFSET)
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#define LPC43_GRP1INT_ENA3 (LPC43_GRP1INT_BASE+LPC43_GRP1INT_ENA3_OFFSET)
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#define LPC43_GRP1INT_ENA4 (LPC43_GRP1INT_BASE+LPC43_GRP1INT_ENA4_OFFSET)
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#define LPC43_GRP1INT_ENA5 (LPC43_GRP1INT_BASE+LPC43_GRP1INT_ENA5_OFFSET)
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#define LPC43_GRP1INT_ENA6 (LPC43_GRP1INT_BASE+LPC43_GRP1INT_ENA6_OFFSET)
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#define LPC43_GRP1INT_ENA7 (LPC43_GRP1INT_BASE+LPC43_GRP1INT_ENA7_OFFSET)
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#define LPC43_GRP1INT_ENA(p) (LPC43_GRP1INT_BASE+LPC43_GRPINT_ENA_OFFSET(p))
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#define LPC43_GRP1INT_ENA0 (LPC43_GRP1INT_BASE+LPC43_GRPINT_ENA0_OFFSET)
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#define LPC43_GRP1INT_ENA1 (LPC43_GRP1INT_BASE+LPC43_GRPINT_ENA1_OFFSET)
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#define LPC43_GRP1INT_ENA2 (LPC43_GRP1INT_BASE+LPC43_GRPINT_ENA2_OFFSET)
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#define LPC43_GRP1INT_ENA3 (LPC43_GRP1INT_BASE+LPC43_GRPINT_ENA3_OFFSET)
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#define LPC43_GRP1INT_ENA4 (LPC43_GRP1INT_BASE+LPC43_GRPINT_ENA4_OFFSET)
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#define LPC43_GRP1INT_ENA5 (LPC43_GRP1INT_BASE+LPC43_GRPINT_ENA5_OFFSET)
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#define LPC43_GRP1INT_ENA6 (LPC43_GRP1INT_BASE+LPC43_GRPINT_ENA6_OFFSET)
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#define LPC43_GRP1INT_ENA7 (LPC43_GRP1INT_BASE+LPC43_GRPINT_ENA7_OFFSET)
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/* GPIO Port Registers (relative to LPC43_GPIO_BASE) */
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/* Pin Groups */
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#define SPSP0 0
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#define SPSP1 1
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#define SPSP2 2
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#define SPSP3 3
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#define SPSP4 4
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#define SPSP5 5
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#define SPSP6 6
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#define SPSP7 7
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#define SPSP8 8
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#define SPSP9 9
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#define SPSP10 10
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#define SPSP11 11
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#define SPSP12 12
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#define SPSP13 13
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#define SPSP14 14
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#define SPSP15 15
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#define SPSP0 0
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#define SPSP1 1
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#define SPSP2 2
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#define SPSP3 3
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#define SPSP4 4
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#define SPSP5 5
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#define SPSP6 6
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#define SPSP7 7
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#define SPSP8 8
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#define SPSP9 9
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#define SPSP10 10
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#define SPSP11 11
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#define SPSP12 12
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#define SPSP13 13
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#define SPSP14 14
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#define SPSP15 15
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#define LPC43_SCU_SFSP_OFFSET(p,n) (((p) << 7) | ((n) << 2))
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#define LPC43_SCU_SFSP0_OFFSET(n) (0x0000 | ((n) << 2))
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#define LPC43_SCU_SFSP1_OFFSET(n) (0x0080 | ((n) << 2))
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#define LPC43_SCU_SFSP2_OFFSET(n) (0x0100 | ((n) << 2))
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#define LPC43_SCU_SFSP3_OFFSET(n) (0x0180 | ((n) << 2))
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#define LPC43_SCU_SFSP4_OFFSET(n) (0x0200 | ((n) << 2))
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#define LPC43_SCU_SFSP5_OFFSET(n) (0x0280 | ((n) << 2))
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#define LPC43_SCU_SFSP6_OFFSET(n) (0x0300 | ((n) << 2))
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#define LPC43_SCU_SFSP7_OFFSET(n) (0x0380 | ((n) << 2))
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#define LPC43_SCU_SFSP8_OFFSET(n) (0x0400 | ((n) << 2))
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#define LPC43_SCU_SFSP9_OFFSET(n) (0x0480 | ((n) << 2))
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#define LPC43_SCU_SFSPA_OFFSET(n) (0x0500 | ((n) << 2))
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#define LPC43_SCU_SFSPB_OFFSET(n) (0x0580 | ((n) << 2))
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#define LPC43_SCU_SFSPC_OFFSET(n) (0x0600 | ((n) << 2))
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#define LPC43_SCU_SFSPD_OFFSET(n) (0x0680 | ((n) << 2))
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#define LPC43_SCU_SFSPE_OFFSET(n) (0x0700 | ((n) << 2))
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#define LPC43_SCU_SFSPF_OFFSET(n) (0x0780 | ((n) << 2))
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#define LPC43_SCU_SFSP_OFFSET(p,n) (((p) << 7) | ((n) << 2))
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#define LPC43_SCU_SFSP0_OFFSET(n) (0x0000 | ((n) << 2))
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#define LPC43_SCU_SFSP1_OFFSET(n) (0x0080 | ((n) << 2))
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#define LPC43_SCU_SFSP2_OFFSET(n) (0x0100 | ((n) << 2))
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#define LPC43_SCU_SFSP3_OFFSET(n) (0x0180 | ((n) << 2))
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#define LPC43_SCU_SFSP4_OFFSET(n) (0x0200 | ((n) << 2))
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#define LPC43_SCU_SFSP5_OFFSET(n) (0x0280 | ((n) << 2))
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#define LPC43_SCU_SFSP6_OFFSET(n) (0x0300 | ((n) << 2))
|
||||
#define LPC43_SCU_SFSP7_OFFSET(n) (0x0380 | ((n) << 2))
|
||||
#define LPC43_SCU_SFSP8_OFFSET(n) (0x0400 | ((n) << 2))
|
||||
#define LPC43_SCU_SFSP9_OFFSET(n) (0x0480 | ((n) << 2))
|
||||
#define LPC43_SCU_SFSPA_OFFSET(n) (0x0500 | ((n) << 2))
|
||||
#define LPC43_SCU_SFSPB_OFFSET(n) (0x0580 | ((n) << 2))
|
||||
#define LPC43_SCU_SFSPC_OFFSET(n) (0x0600 | ((n) << 2))
|
||||
#define LPC43_SCU_SFSPD_OFFSET(n) (0x0680 | ((n) << 2))
|
||||
#define LPC43_SCU_SFSPE_OFFSET(n) (0x0700 | ((n) << 2))
|
||||
#define LPC43_SCU_SFSPF_OFFSET(n) (0x0780 | ((n) << 2))
|
||||
|
||||
/* CLKn pins */
|
||||
|
||||
#define SFSCLK0 0
|
||||
#define SFSCLK1 1
|
||||
#define SFSCLK2 2
|
||||
#define SFSCLK3 3
|
||||
#define SFSCLK0 0
|
||||
#define SFSCLK1 1
|
||||
#define SFSCLK2 2
|
||||
#define SFSCLK3 3
|
||||
|
||||
#define LPC43_SCU_SFSCLK_OFFSET(n) (0x0c00 | ((n) << 2))
|
||||
#define LPC43_SCU_SFSCLK0_OFFSET 0x0c00
|
||||
#define LPC43_SCU_SFSCLK1_OFFSET 0x0c04
|
||||
#define LPC43_SCU_SFSCLK2_OFFSET 0x0c08
|
||||
#define LPC43_SCU_SFSCLK3_OFFSET 0x0c0c
|
||||
#define LPC43_SCU_SFSCLK_OFFSET(n) (0x0c00 | ((n) << 2))
|
||||
#define LPC43_SCU_SFSCLK0_OFFSET 0x0c00
|
||||
#define LPC43_SCU_SFSCLK1_OFFSET 0x0c04
|
||||
#define LPC43_SCU_SFSCLK2_OFFSET 0x0c08
|
||||
#define LPC43_SCU_SFSCLK3_OFFSET 0x0c0c
|
||||
|
||||
/* USB1 USB1_DP/USB1_DM pins and I2C-bus open-drain pins */
|
||||
|
||||
#define LPC43_SCU_SFSUSB_OFFSET 0x0c80
|
||||
#define LPC43_SCU_SFSI2C0_OFFSET 0x0c84
|
||||
#define LPC43_SCU_SFSUSB_OFFSET 0x0c80
|
||||
#define LPC43_SCU_SFSI2C0_OFFSET 0x0c84
|
||||
|
||||
/* ADC pin select registers */
|
||||
|
||||
#define ENAIO0 0
|
||||
#define ENAIO1 1
|
||||
#define ENAIO2 2
|
||||
#define ENAIO0 0
|
||||
#define ENAIO1 1
|
||||
#define ENAIO2 2
|
||||
|
||||
#define LPC43_SCU_ENAIO_OFFSET(n) (0x0c88 | ((n) << 2))
|
||||
#define LPC43_SCU_ENAIO0_OFFSET 0x0c88
|
||||
#define LPC43_SCU_ENAIO1_OFFSET 0x0c8c
|
||||
#define LPC43_SCU_ENAIO2_OFFSET 0x0c90
|
||||
#define LPC43_SCU_ENAIO_OFFSET(n) (0x0c88 | ((n) << 2))
|
||||
#define LPC43_SCU_ENAIO0_OFFSET 0x0c88
|
||||
#define LPC43_SCU_ENAIO1_OFFSET 0x0c8c
|
||||
#define LPC43_SCU_ENAIO2_OFFSET 0x0c90
|
||||
|
||||
/* EMC delay register */
|
||||
|
||||
#define LPC43_SCU_EMCDELAYCLK_OFFSET 0x0d00
|
||||
#define LPC43_SCU_EMCDELAYCLK_OFFSET 0x0d00
|
||||
|
||||
/* Pin interrupt select registers */
|
||||
|
||||
#define PINTSEL0 0
|
||||
#define PINTSEL1 1
|
||||
#define PINTSEL0 0
|
||||
#define PINTSEL1 1
|
||||
|
||||
#define LPC43_SCU_PINTSEL_OFFSET(n) (0x0e00 | ((n) << 2))
|
||||
#define LPC43_SCU_PINTSEL0_OFFSET 0x0e00
|
||||
#define LPC43_SCU_PINTSEL1_OFFSET 0x0e04
|
||||
#define LPC43_SCU_PINTSEL_OFFSET(n) (0x0e00 | ((n) << 2))
|
||||
#define LPC43_SCU_PINTSEL0_OFFSET 0x0e00
|
||||
#define LPC43_SCU_PINTSEL1_OFFSET 0x0e04
|
||||
|
||||
/* Register Addresses *******************************************************************************/
|
||||
|
||||
/* Pin Groups */
|
||||
|
||||
#define LPC43_SCU_SFSP(p,n) (LPC43_SCU_BASE+LPC43_SCU_SFSP_OFFSET(p,n))
|
||||
#define LPC43_SCU_SFSP0(n) (LPC43_SCU_BASE+LPC43_SCU_SFSP0_OFFSET(n))
|
||||
#define LPC43_SCU_SFSP1(n) (LPC43_SCU_BASE+LPC43_SCU_SFSP1_OFFSET(n))
|
||||
#define LPC43_SCU_SFSP2(n) (LPC43_SCU_BASE+LPC43_SCU_SFSP2_OFFSET(n))
|
||||
#define LPC43_SCU_SFSP3(n) (LPC43_SCU_BASE+LPC43_SCU_SFSP3_OFFSET(n))
|
||||
#define LPC43_SCU_SFSP4(n) (LPC43_SCU_BASE+LPC43_SCU_SFSP4_OFFSET(n))
|
||||
#define LPC43_SCU_SFSP5(n) (LPC43_SCU_BASE+LPC43_SCU_SFSP5_OFFSET(n))
|
||||
#define LPC43_SCU_SFSP6(n) (LPC43_SCU_BASE+LPC43_SCU_SFSP6_OFFSET(n))
|
||||
#define LPC43_SCU_SFSP7(n) (LPC43_SCU_BASE+LPC43_SCU_SFSP7_OFFSET(n))
|
||||
#define LPC43_SCU_SFSP8(n) (LPC43_SCU_BASE+LPC43_SCU_SFSP8_OFFSET(n))
|
||||
#define LPC43_SCU_SFSP9(n) (LPC43_SCU_BASE+LPC43_SCU_SFSP9_OFFSET(n))
|
||||
#define LPC43_SCU_SFSPA(n) (LPC43_SCU_BASE+LPC43_SCU_SFSPA_OFFSET(n))
|
||||
#define LPC43_SCU_SFSPB(n) (LPC43_SCU_BASE+LPC43_SCU_SFSPB_OFFSET(n))
|
||||
#define LPC43_SCU_SFSPC(n) (LPC43_SCU_BASE+LPC43_SCU_SFSPC_OFFSET(n))
|
||||
#define LPC43_SCU_SFSPD(n) (LPC43_SCU_BASE+LPC43_SCU_SFSPD_OFFSET(n))
|
||||
#define LPC43_SCU_SFSPE(n) (LPC43_SCU_BASE+LPC43_SCU_SFSPE_OFFSET(n))
|
||||
#define LPC43_SCU_SFSPF(n) (LPC43_SCU_BASE+LPC43_SCU_SFSPF_OFFSET(n))
|
||||
#define LPC43_SCU_SFSP(p,n) (LPC43_SCU_BASE+LPC43_SCU_SFSP_OFFSET(p,n))
|
||||
#define LPC43_SCU_SFSP0(n) (LPC43_SCU_BASE+LPC43_SCU_SFSP0_OFFSET(n))
|
||||
#define LPC43_SCU_SFSP1(n) (LPC43_SCU_BASE+LPC43_SCU_SFSP1_OFFSET(n))
|
||||
#define LPC43_SCU_SFSP2(n) (LPC43_SCU_BASE+LPC43_SCU_SFSP2_OFFSET(n))
|
||||
#define LPC43_SCU_SFSP3(n) (LPC43_SCU_BASE+LPC43_SCU_SFSP3_OFFSET(n))
|
||||
#define LPC43_SCU_SFSP4(n) (LPC43_SCU_BASE+LPC43_SCU_SFSP4_OFFSET(n))
|
||||
#define LPC43_SCU_SFSP5(n) (LPC43_SCU_BASE+LPC43_SCU_SFSP5_OFFSET(n))
|
||||
#define LPC43_SCU_SFSP6(n) (LPC43_SCU_BASE+LPC43_SCU_SFSP6_OFFSET(n))
|
||||
#define LPC43_SCU_SFSP7(n) (LPC43_SCU_BASE+LPC43_SCU_SFSP7_OFFSET(n))
|
||||
#define LPC43_SCU_SFSP8(n) (LPC43_SCU_BASE+LPC43_SCU_SFSP8_OFFSET(n))
|
||||
#define LPC43_SCU_SFSP9(n) (LPC43_SCU_BASE+LPC43_SCU_SFSP9_OFFSET(n))
|
||||
#define LPC43_SCU_SFSPA(n) (LPC43_SCU_BASE+LPC43_SCU_SFSPA_OFFSET(n))
|
||||
#define LPC43_SCU_SFSPB(n) (LPC43_SCU_BASE+LPC43_SCU_SFSPB_OFFSET(n))
|
||||
#define LPC43_SCU_SFSPC(n) (LPC43_SCU_BASE+LPC43_SCU_SFSPC_OFFSET(n))
|
||||
#define LPC43_SCU_SFSPD(n) (LPC43_SCU_BASE+LPC43_SCU_SFSPD_OFFSET(n))
|
||||
#define LPC43_SCU_SFSPE(n) (LPC43_SCU_BASE+LPC43_SCU_SFSPE_OFFSET(n))
|
||||
#define LPC43_SCU_SFSPF(n) (LPC43_SCU_BASE+LPC43_SCU_SFSPF_OFFSET(n))
|
||||
|
||||
/* CLKn pins */
|
||||
|
||||
#define LPC43_SCU_SFSCLK(n) (LPC43_SCU_BASE+LPC43_SCU_SFSCLK_OFFSET(n))
|
||||
#define LPC43_SCU_SFSCLK0 (LPC43_SCU_BASE+LPC43_SCU_SFSCLK0_OFFSET)
|
||||
#define LPC43_SCU_SFSCLK1 (LPC43_SCU_BASE+LPC43_SCU_SFSCLK1_OFFSET)
|
||||
#define LPC43_SCU_SFSCLK2 (LPC43_SCU_BASE+LPC43_SCU_SFSCLK2_OFFSET)
|
||||
#define LPC43_SCU_SFSCLK3 (LPC43_SCU_BASE+LPC43_SCU_SFSCLK3_OFFSET)
|
||||
#define LPC43_SCU_SFSCLK(n) (LPC43_SCU_BASE+LPC43_SCU_SFSCLK_OFFSET(n))
|
||||
#define LPC43_SCU_SFSCLK0 (LPC43_SCU_BASE+LPC43_SCU_SFSCLK0_OFFSET)
|
||||
#define LPC43_SCU_SFSCLK1 (LPC43_SCU_BASE+LPC43_SCU_SFSCLK1_OFFSET)
|
||||
#define LPC43_SCU_SFSCLK2 (LPC43_SCU_BASE+LPC43_SCU_SFSCLK2_OFFSET)
|
||||
#define LPC43_SCU_SFSCLK3 (LPC43_SCU_BASE+LPC43_SCU_SFSCLK3_OFFSET)
|
||||
|
||||
/* USB1 USB1_DP/USB1_DM pins and I2C-bus open-drain pins */
|
||||
|
||||
#define LPC43_SCU_SFSUSB (LPC43_SCU_BASE+LPC43_SCU_SFSUSB_OFFSET)
|
||||
#define LPC43_SCU_SFSI2C0 (LPC43_SCU_BASE+LPC43_SCU_SFSI2C0_OFFSET)
|
||||
#define LPC43_SCU_SFSUSB (LPC43_SCU_BASE+LPC43_SCU_SFSUSB_OFFSET)
|
||||
#define LPC43_SCU_SFSI2C0 (LPC43_SCU_BASE+LPC43_SCU_SFSI2C0_OFFSET)
|
||||
|
||||
/* ADC pin select registers */
|
||||
|
||||
#define LPC43_SCU_ENAIO(n) (LPC43_SCU_BASE+LPC43_SCU_ENAIO_OFFSET(n))
|
||||
#define LPC43_SCU_ENAIO0 (LPC43_SCU_BASE+LPC43_SCU_ENAIO0_OFFSET)
|
||||
#define LPC43_SCU_ENAIO1 (LPC43_SCU_BASE+LPC43_SCU_ENAIO1_OFFSET)
|
||||
#define LPC43_SCU_ENAIO2 (LPC43_SCU_BASE+LPC43_SCU_ENAIO2_OFFSET)
|
||||
#define LPC43_SCU_ENAIO(n) (LPC43_SCU_BASE+LPC43_SCU_ENAIO_OFFSET(n))
|
||||
#define LPC43_SCU_ENAIO0 (LPC43_SCU_BASE+LPC43_SCU_ENAIO0_OFFSET)
|
||||
#define LPC43_SCU_ENAIO1 (LPC43_SCU_BASE+LPC43_SCU_ENAIO1_OFFSET)
|
||||
#define LPC43_SCU_ENAIO2 (LPC43_SCU_BASE+LPC43_SCU_ENAIO2_OFFSET)
|
||||
|
||||
/* EMC delay register */
|
||||
|
||||
#define LPC43_SCU_EMCDELAYCLK (LPC43_SCU_BASE+LPC43_SCU_EMCDELAYCLK_OFFSET)
|
||||
#define LPC43_SCU_EMCDELAYCLK (LPC43_SCU_BASE+LPC43_SCU_EMCDELAYCLK_OFFSET)
|
||||
|
||||
/* Pin interrupt select registers */
|
||||
|
||||
#define LPC43_SCU_PINTSEL(n) (LPC43_SCU_BASE+LPC43_SCU_PINTSEL_OFFSET(n))
|
||||
#define LPC43_SCU_PINTSEL0 (LPC43_SCU_BASE+LPC43_SCU_PINTSEL0_OFFSET)
|
||||
#define LPC43_SCU_PINTSEL1 (LPC43_SCU_BASE+LPC43_SCU_PINTSEL1_OFFSET)
|
||||
#define LPC43_SCU_PINTSEL(n) (LPC43_SCU_BASE+LPC43_SCU_PINTSEL_OFFSET(n))
|
||||
#define LPC43_SCU_PINTSEL0 (LPC43_SCU_BASE+LPC43_SCU_PINTSEL0_OFFSET)
|
||||
#define LPC43_SCU_PINTSEL1 (LPC43_SCU_BASE+LPC43_SCU_PINTSEL1_OFFSET)
|
||||
|
||||
/* Register Bit Definitions *************************************************************************/
|
||||
/* Common Pin configuration register bit settings */
|
||||
|
||||
#define SCU_PIN_MODE_SHIFT (0) /* Bits 0-2: Select pin function */
|
||||
#define SCU_PIN_MODE_MASK (7 << SCU_PIN_MODE_SHIFT)
|
||||
# define SCU_PIN_MODE_FUNC(n) ((n) << SCU_PIN_MODE_SHIFT)
|
||||
# define SCU_PIN_MODE_FUNC0 (0 << SCU_PIN_MODE_SHIFT) /* Function 0 (default) */
|
||||
# define SCU_PIN_MODE_FUNC1 (1 << SCU_PIN_MODE_SHIFT) /* Function 1 */
|
||||
# define SCU_PIN_MODE_FUNC2 (2 << SCU_PIN_MODE_SHIFT) /* Function 2 */
|
||||
# define SCU_PIN_MODE_FUNC3 (3 << SCU_PIN_MODE_SHIFT) /* Function 3 */
|
||||
# define SCU_PIN_MODE_FUNC4 (4 << SCU_PIN_MODE_SHIFT) /* Function 4 */
|
||||
# define SCU_PIN_MODE_FUNC5 (5 << SCU_PIN_MODE_SHIFT) /* Function 5 */
|
||||
# define SCU_PIN_MODE_FUNC6 (6 << SCU_PIN_MODE_SHIFT) /* Function 6 */
|
||||
# define SCU_PIN_MODE_FUNC7 (7 << SCU_PIN_MODE_SHIFT) /* Function 7 */
|
||||
#define SCU_PIN_EPD (1 << 3) /* Bit 3: Enable pull-down resistor at pad */
|
||||
#define SCU_PIN_EPUN (1 << 4) /* Bit 4: Disable pull-up resistor at pad */
|
||||
/* Bit 5: Usage varies with pin type */
|
||||
#define SCU_PIN_EZI (1 << 6) /* Bit 6: Input buffer enable */
|
||||
#define SCU_PIN_ZIF (1 << 7) /* Bit 7: Input glitch filter */
|
||||
/* Bits 8-9: Usage varies with pin type */
|
||||
/* Bits 10-31: Reserved */
|
||||
#define SCU_PIN_MODE_SHIFT (0) /* Bits 0-2: Select pin function */
|
||||
#define SCU_PIN_MODE_MASK (7 << SCU_PIN_MODE_SHIFT)
|
||||
# define SCU_PIN_MODE_FUNC(n) ((n) << SCU_PIN_MODE_SHIFT)
|
||||
# define SCU_PIN_MODE_FUNC0 (0 << SCU_PIN_MODE_SHIFT) /* Function 0 (default) */
|
||||
# define SCU_PIN_MODE_FUNC1 (1 << SCU_PIN_MODE_SHIFT) /* Function 1 */
|
||||
# define SCU_PIN_MODE_FUNC2 (2 << SCU_PIN_MODE_SHIFT) /* Function 2 */
|
||||
# define SCU_PIN_MODE_FUNC3 (3 << SCU_PIN_MODE_SHIFT) /* Function 3 */
|
||||
# define SCU_PIN_MODE_FUNC4 (4 << SCU_PIN_MODE_SHIFT) /* Function 4 */
|
||||
# define SCU_PIN_MODE_FUNC5 (5 << SCU_PIN_MODE_SHIFT) /* Function 5 */
|
||||
# define SCU_PIN_MODE_FUNC6 (6 << SCU_PIN_MODE_SHIFT) /* Function 6 */
|
||||
# define SCU_PIN_MODE_FUNC7 (7 << SCU_PIN_MODE_SHIFT) /* Function 7 */
|
||||
#define SCU_PIN_EPD (1 << 3) /* Bit 3: Enable pull-down resistor at pad */
|
||||
#define SCU_PIN_EPUN (1 << 4) /* Bit 4: Disable pull-up resistor at pad */
|
||||
/* Bit 5: Usage varies with pin type */
|
||||
#define SCU_PIN_EZI (1 << 6) /* Bit 6: Input buffer enable */
|
||||
#define SCU_PIN_ZIF (1 << 7) /* Bit 7: Input glitch filter */
|
||||
/* Bits 8-9: Usage varies with pin type */
|
||||
/* Bits 10-31: Reserved */
|
||||
/* Pin configuration registers for normal-drive pins (only):
|
||||
*
|
||||
* P0_0 and P0_1
|
||||
|
|
@ -217,9 +217,9 @@
|
|||
* PE_0 to PE_15
|
||||
* PF_0 to PF_11
|
||||
*/
|
||||
/* Bits 0-4: Same as common bit definitions */
|
||||
#define SCU_NDPIN_EHS (1 << 5) /* Bit 5: EHS Select Slew rate */
|
||||
/* Bits 6-31: Same as common bit definitions */
|
||||
/* Bits 0-4: Same as common bit definitions */
|
||||
#define SCU_NDPIN_EHS (1 << 5) /* Bit 5: EHS Select Slew rate */
|
||||
/* Bits 6-31: Same as common bit definitions */
|
||||
/* Pin configuration registers for high-speed pins
|
||||
*
|
||||
* P1_17
|
||||
|
|
@ -227,45 +227,45 @@
|
|||
* P8_0 to P8_2
|
||||
* PA_1 to PA_3
|
||||
*/
|
||||
/* Bits 0-7: Same as common bit definitions */
|
||||
#define SCU_HDPIN_EHD_SHIFT (8) /* Bits 8-9: Select drive strength */
|
||||
#define SCU_HDPIN_EHD_MASK (3 << SCU_HDPIN_EHD_SHIFT)
|
||||
# define SCU_HDPIN_EHD_NORMAL (0 << SCU_HDPIN_EHD_SHIFT) /* Normal-drive: 4 mA drive strength */
|
||||
# define SCU_HDPIN_EHD_MEDIUM (1 << SCU_HDPIN_EHD_SHIFT) /* Medium-drive: 8 mA drive strength */
|
||||
# define SCU_HDPIN_EHD_HIGH (2 << SCU_HDPIN_EHD_SHIFT) /* High-drive: 14 mA drive strength */
|
||||
# define SCU_HDPIN_EHD_ULTRA (3 << SCU_HDPIN_EHD_SHIFT) /* Ultra high-drive: 20 mA drive strength */
|
||||
/* Bits 10-31: Reserved */
|
||||
/* Bits 0-7: Same as common bit definitions */
|
||||
#define SCU_HDPIN_EHD_SHIFT (8) /* Bits 8-9: Select drive strength */
|
||||
#define SCU_HDPIN_EHD_MASK (3 << SCU_HDPIN_EHD_SHIFT)
|
||||
# define SCU_HDPIN_EHD_NORMAL (0 << SCU_HDPIN_EHD_SHIFT) /* Normal-drive: 4 mA drive strength */
|
||||
# define SCU_HDPIN_EHD_MEDIUM (1 << SCU_HDPIN_EHD_SHIFT) /* Medium-drive: 8 mA drive strength */
|
||||
# define SCU_HDPIN_EHD_HIGH (2 << SCU_HDPIN_EHD_SHIFT) /* High-drive: 14 mA drive strength */
|
||||
# define SCU_HDPIN_EHD_ULTRA (3 << SCU_HDPIN_EHD_SHIFT) /* Ultra high-drive: 20 mA drive strength */
|
||||
/* Bits 10-31: Reserved */
|
||||
/* Pin configuration registers for high-speed pins
|
||||
*
|
||||
* P3_3 and pins CLK0 to CLK3
|
||||
*/
|
||||
/* Bits 0-4: Same as common bit definitions */
|
||||
#define SCU_HSPIN_EHS (1 << 5) /* Bit 5: EHS Select Slew rate */
|
||||
/* Bits 6-31: Same as common bit definitions */
|
||||
/* Bits 0-4: Same as common bit definitions */
|
||||
#define SCU_HSPIN_EHS (1 << 5) /* Bit 5: EHS Select Slew rate */
|
||||
/* Bits 6-31: Same as common bit definitions */
|
||||
/* Pin configuration register for USB1 pins USB1_DP/USB1_DM */
|
||||
|
||||
#define SCU_SFSUSB_AIM (1 << 0) /* Bit 0: Differential data input AIP/AIM */
|
||||
#define SCU_SFSUSB_ESEA (1 << 1) /* Bit 1: Control signal for differential input or single input */
|
||||
#define SCU_SFSUSB_EPD (1 << 2) /* Bit 2: Enable pull-down connect */
|
||||
/* Bit 3: Reserved */
|
||||
#define SCU_SFSUSB_EPWR (1 << 4) /* Bit 4: Power mode */
|
||||
#define SCU_SFSUSB_VBUS (1 << 5) /* Bit 5: Enable the vbus_valid signal */
|
||||
/* Bits 6-31: Reserved */
|
||||
#define SCU_SFSUSB_AIM (1 << 0) /* Bit 0: Differential data input AIP/AIM */
|
||||
#define SCU_SFSUSB_ESEA (1 << 1) /* Bit 1: Control signal for differential input or single input */
|
||||
#define SCU_SFSUSB_EPD (1 << 2) /* Bit 2: Enable pull-down connect */
|
||||
/* Bit 3: Reserved */
|
||||
#define SCU_SFSUSB_EPWR (1 << 4) /* Bit 4: Power mode */
|
||||
#define SCU_SFSUSB_VBUS (1 << 5) /* Bit 5: Enable the vbus_valid signal */
|
||||
/* Bits 6-31: Reserved */
|
||||
/* Pin configuration register for open-drain I2C-bus pins */
|
||||
|
||||
#define SCU_SFSI2C0_SCL_EFP (1 << 0) /* Bit 0: Select input glitch filter time constant for the SCL pin */
|
||||
/* Bit 1: Reserved */
|
||||
#define SCU_SFSI2C0_SCL_EHD (1 << 2) /* Bit 2: Select I2C mode for the SCL pin */
|
||||
#define SCU_SFSI2C0_SCL_EZI (1 << 3) /* Bit 3: Enable the input receiver for the SCL pin */
|
||||
/* Bits 4-6: Reserved */
|
||||
#define SCU_SFSI2C0_SCL_ZIF (1 << 7) /* Bit 7: Enable or disable input glitch filter for the SCL pin */
|
||||
#define SCU_SFSI2C0_SDA_EFP (1 << 8) /* Bit 8: Select input glitch filter time constant for the SDA pin */
|
||||
/* Bit 9: Reserved */
|
||||
#define SCU_SFSI2C0_SDA_EHD (1 << 10) /* Bit 10: Select I2C mode for the SDA pin */
|
||||
#define SCU_SFSI2C0_SDA_EZI (1 << 11) /* Bit 11: Enable the input receiver for the SDA pin */
|
||||
/* Bits 12-14: Reserved */
|
||||
#define SCU_SFSI2C0_SDA_ZIF (1 << 15) /* Bit 15: Enable or disable input glitch filter for the SDA pin */
|
||||
/* Bits 16-31: Reserved */
|
||||
#define SCU_SFSI2C0_SCL_EFP (1 << 0) /* Bit 0: Select input glitch filter time constant for the SCL pin */
|
||||
/* Bit 1: Reserved */
|
||||
#define SCU_SFSI2C0_SCL_EHD (1 << 2) /* Bit 2: Select I2C mode for the SCL pin */
|
||||
#define SCU_SFSI2C0_SCL_EZI (1 << 3) /* Bit 3: Enable the input receiver for the SCL pin */
|
||||
/* Bits 4-6: Reserved */
|
||||
#define SCU_SFSI2C0_SCL_ZIF (1 << 7) /* Bit 7: Enable or disable input glitch filter for the SCL pin */
|
||||
#define SCU_SFSI2C0_SDA_EFP (1 << 8) /* Bit 8: Select input glitch filter time constant for the SDA pin */
|
||||
/* Bit 9: Reserved */
|
||||
#define SCU_SFSI2C0_SDA_EHD (1 << 10) /* Bit 10: Select I2C mode for the SDA pin */
|
||||
#define SCU_SFSI2C0_SDA_EZI (1 << 11) /* Bit 11: Enable the input receiver for the SDA pin */
|
||||
/* Bits 12-14: Reserved */
|
||||
#define SCU_SFSI2C0_SDA_ZIF (1 << 15) /* Bit 15: Enable or disable input glitch filter for the SDA pin */
|
||||
/* Bits 16-31: Reserved */
|
||||
/* ADC0 function select register. The following pins are controlled by the ENAIO0 register:
|
||||
*
|
||||
* Pin ADC function ENAIO0 register bit
|
||||
|
|
@ -278,14 +278,14 @@
|
|||
* PB_6 ADC0_6 6
|
||||
*/
|
||||
|
||||
#define SCU_ENAI00_ADC0(n) (1 << (n))
|
||||
#define SCU_ENAI00_ADC0_0 (1 << 0) /* Select ADC0_0 */
|
||||
#define SCU_ENAI00_ADC0_1 (1 << 1) /* Select ADC0_1 */
|
||||
#define SCU_ENAI00_ADC0_2 (1 << 2) /* Select ADC0_2 */
|
||||
#define SCU_ENAI00_ADC0_3 (1 << 3) /* Select ADC0_3 */
|
||||
#define SCU_ENAI00_ADC0_4 (1 << 4) /* Select ADC0_4 */
|
||||
#define SCU_ENAI00_ADC0_5 (1 << 5) /* Select ADC0_5 */
|
||||
#define SCU_ENAI00_ADC0_6 (1 << 6) /* Select ADC0_6 */
|
||||
#define SCU_ENAI00_ADC0(n) (1 << (n))
|
||||
#define SCU_ENAI00_ADC0_0 (1 << 0) /* Select ADC0_0 */
|
||||
#define SCU_ENAI00_ADC0_1 (1 << 1) /* Select ADC0_1 */
|
||||
#define SCU_ENAI00_ADC0_2 (1 << 2) /* Select ADC0_2 */
|
||||
#define SCU_ENAI00_ADC0_3 (1 << 3) /* Select ADC0_3 */
|
||||
#define SCU_ENAI00_ADC0_4 (1 << 4) /* Select ADC0_4 */
|
||||
#define SCU_ENAI00_ADC0_5 (1 << 5) /* Select ADC0_5 */
|
||||
#define SCU_ENAI00_ADC0_6 (1 << 6) /* Select ADC0_6 */
|
||||
|
||||
/* ADC1 function select register. The following pins are controlled by the ENAIO1 register:
|
||||
*
|
||||
|
|
@ -300,15 +300,15 @@
|
|||
* PF_7 ADC1_7 7
|
||||
*/
|
||||
|
||||
#define SCU_ENAI01_ADC1(n) (1 << (n))
|
||||
#define SCU_ENAI01_ADC1_0 (1 << 0) /* Select ADC1_0 */
|
||||
#define SCU_ENAI01_ADC1_1 (1 << 1) /* Select ADC1_1 */
|
||||
#define SCU_ENAI01_ADC1_2 (1 << 2) /* Select ADC1_2 */
|
||||
#define SCU_ENAI01_ADC1_3 (1 << 3) /* Select ADC1_3 */
|
||||
#define SCU_ENAI01_ADC1_4 (1 << 4) /* Select ADC1_4 */
|
||||
#define SCU_ENAI01_ADC1_5 (1 << 5) /* Select ADC1_5 */
|
||||
#define SCU_ENAI01_ADC1_6 (1 << 6) /* Select ADC1_6 */
|
||||
#define SCU_ENAI01_ADC1_7 (1 << 7) /* Select ADC1_7 */
|
||||
#define SCU_ENAI01_ADC1(n) (1 << (n))
|
||||
#define SCU_ENAI01_ADC1_0 (1 << 0) /* Select ADC1_0 */
|
||||
#define SCU_ENAI01_ADC1_1 (1 << 1) /* Select ADC1_1 */
|
||||
#define SCU_ENAI01_ADC1_2 (1 << 2) /* Select ADC1_2 */
|
||||
#define SCU_ENAI01_ADC1_3 (1 << 3) /* Select ADC1_3 */
|
||||
#define SCU_ENAI01_ADC1_4 (1 << 4) /* Select ADC1_4 */
|
||||
#define SCU_ENAI01_ADC1_5 (1 << 5) /* Select ADC1_5 */
|
||||
#define SCU_ENAI01_ADC1_6 (1 << 6) /* Select ADC1_6 */
|
||||
#define SCU_ENAI01_ADC1_7 (1 << 7) /* Select ADC1_7 */
|
||||
|
||||
/* Analog function select register. The following pins are controlled by the ENAIO2 register:
|
||||
*
|
||||
|
|
@ -317,94 +317,108 @@
|
|||
* PF_7 BG (band gap output) 4
|
||||
*/
|
||||
|
||||
#define SCU_ENAI02_DAC (1 << 0) /* Select DAC */
|
||||
#define SCU_ENAI02_BG (1 << 4) /* Select band gap output */
|
||||
#define SCU_ENAI02_DAC (1 << 0) /* Select DAC */
|
||||
#define SCU_ENAI02_BG (1 << 4) /* Select band gap output */
|
||||
|
||||
/* EMC clock delay register. The value 0x1111 corresponds to about 0.5 ns of delay */
|
||||
|
||||
#define SCU_EMCDELAYCLK_SHIFT (0) /* Bits 0-15: EMC_CLKn SDRAM clock output delay */
|
||||
#define SCU_EMCDELAYCLK_MASK (0xffff << SCU_EMCDELAYCLK_SHIFT)
|
||||
# define SCU_EMCDELAYCLK(n) ((n) << SCU_EMCDELAYCLK_SHIFT) /* 0=no delay, N*0x1111 = N*0.5 ns delay */
|
||||
/* Bits 16-31: Reserved */
|
||||
#define SCU_EMCDELAYCLK_SHIFT (0) /* Bits 0-15: EMC_CLKn SDRAM clock output delay */
|
||||
#define SCU_EMCDELAYCLK_MASK (0xffff << SCU_EMCDELAYCLK_SHIFT)
|
||||
# define SCU_EMCDELAYCLK(n) ((n) << SCU_EMCDELAYCLK_SHIFT) /* 0=no delay, N*0x1111 = N*0.5 ns delay */
|
||||
/* Bits 16-31: Reserved */
|
||||
/* Pin interrupt select register 0 */
|
||||
|
||||
#define SCU_GPIO_PORT0 0
|
||||
#define SCU_GPIO_PORT1 1
|
||||
#define SCU_GPIO_PORT2 2
|
||||
#define SCU_GPIO_PORT3 3
|
||||
#define SCU_GPIO_PORT4 4
|
||||
#define SCU_GPIO_PORT5 5
|
||||
#define SCU_GPIO_PORT6 6
|
||||
#define SCU_GPIO_PORT7 7
|
||||
#define SCU_GPIO_PORT0 0
|
||||
#define SCU_GPIO_PORT1 1
|
||||
#define SCU_GPIO_PORT2 2
|
||||
#define SCU_GPIO_PORT3 3
|
||||
#define SCU_GPIO_PORT4 4
|
||||
#define SCU_GPIO_PORT5 5
|
||||
#define SCU_GPIO_PORT6 6
|
||||
#define SCU_GPIO_PORT7 7
|
||||
|
||||
#define SCU_GPIO_PIN0 0
|
||||
#define SCU_GPIO_PIN1 1
|
||||
#define SCU_GPIO_PIN2 2
|
||||
#define SCU_GPIO_PIN3 3
|
||||
#define SCU_GPIO_PIN4 4
|
||||
#define SCU_GPIO_PIN5 5
|
||||
#define SCU_GPIO_PIN6 6
|
||||
#define SCU_GPIO_PIN7 7
|
||||
#define SCU_GPIO_PIN8 8
|
||||
#define SCU_GPIO_PIN9 9
|
||||
#define SCU_GPIO_PIN10 10
|
||||
#define SCU_GPIO_PIN11 11
|
||||
#define SCU_GPIO_PIN12 12
|
||||
#define SCU_GPIO_PIN13 13
|
||||
#define SCU_GPIO_PIN14 14
|
||||
#define SCU_GPIO_PIN15 15
|
||||
#define SCU_GPIO_PIN16 16
|
||||
#define SCU_GPIO_PIN17 17
|
||||
#define SCU_GPIO_PIN18 18
|
||||
#define SCU_GPIO_PIN19 19
|
||||
#define SCU_GPIO_PIN20 20
|
||||
#define SCU_GPIO_PIN21 21
|
||||
#define SCU_GPIO_PIN22 22
|
||||
#define SCU_GPIO_PIN23 23
|
||||
#define SCU_GPIO_PIN24 24
|
||||
#define SCU_GPIO_PIN25 25
|
||||
#define SCU_GPIO_PIN26 26
|
||||
#define SCU_GPIO_PIN27 27
|
||||
#define SCU_GPIO_PIN28 28
|
||||
#define SCU_GPIO_PIN29 29
|
||||
#define SCU_GPIO_PIN30 30
|
||||
#define SCU_GPIO_PIN31 31
|
||||
#define SCU_GPIO_PIN0 0
|
||||
#define SCU_GPIO_PIN1 1
|
||||
#define SCU_GPIO_PIN2 2
|
||||
#define SCU_GPIO_PIN3 3
|
||||
#define SCU_GPIO_PIN4 4
|
||||
#define SCU_GPIO_PIN5 5
|
||||
#define SCU_GPIO_PIN6 6
|
||||
#define SCU_GPIO_PIN7 7
|
||||
#define SCU_GPIO_PIN8 8
|
||||
#define SCU_GPIO_PIN9 9
|
||||
#define SCU_GPIO_PIN10 10
|
||||
#define SCU_GPIO_PIN11 11
|
||||
#define SCU_GPIO_PIN12 12
|
||||
#define SCU_GPIO_PIN13 13
|
||||
#define SCU_GPIO_PIN14 14
|
||||
#define SCU_GPIO_PIN15 15
|
||||
#define SCU_GPIO_PIN16 16
|
||||
#define SCU_GPIO_PIN17 17
|
||||
#define SCU_GPIO_PIN18 18
|
||||
#define SCU_GPIO_PIN19 19
|
||||
#define SCU_GPIO_PIN20 20
|
||||
#define SCU_GPIO_PIN21 21
|
||||
#define SCU_GPIO_PIN22 22
|
||||
#define SCU_GPIO_PIN23 23
|
||||
#define SCU_GPIO_PIN24 24
|
||||
#define SCU_GPIO_PIN25 25
|
||||
#define SCU_GPIO_PIN26 26
|
||||
#define SCU_GPIO_PIN27 27
|
||||
#define SCU_GPIO_PIN28 28
|
||||
#define SCU_GPIO_PIN29 29
|
||||
#define SCU_GPIO_PIN30 30
|
||||
#define SCU_GPIO_PIN31 31
|
||||
|
||||
#define SCU_PINTSEL0_INTPIN0_SHIFT (0) /* Bits 0-4: Pint interrupt 0 */
|
||||
#define SCU_PINTSEL0_INTPIN0_MASK (31 << SCU_PINTSEL0_INTPIN0_SHIFT)
|
||||
#define SCU_PINTSEL0_PORTSEL0_SHIFT (5) /* Bits 5-7: Pin interrupt 0 */
|
||||
#define SCU_PINTSEL0_PORTSEL0_MASK (7 << SCU_PINTSEL0_PORTSEL0_SHIFT)
|
||||
#define SCU_PINTSEL0_INTPIN1_SHIFT (8) /* Bits 8-12: Pint interrupt 1 */
|
||||
#define SCU_PINTSEL0_INTPIN1_MASK (31 << SCU_PINTSEL0_INTPIN1_SHIFT)
|
||||
#define SCU_PINTSEL0_PORTSEL1_SHIFT (13) /* Bits 13-15: Pin interrupt 1 */
|
||||
#define SCU_PINTSEL0_PORTSEL1_MASK (7 << SCU_PINTSEL0_PORTSEL1_SHIFT)
|
||||
#define SCU_PINTSEL0_INTPIN2_SHIFT (16) /* Bits 16-20: Pint interrupt 2 */
|
||||
#define SCU_PINTSEL0_INTPIN2_MASK (31 << SCU_PINTSEL0_INTPIN2_SHIFT)
|
||||
#define SCU_PINTSEL0_PORTSEL2_SHIFT (21) /* Bits 21-23: Pin interrupt 2 */
|
||||
#define SCU_PINTSEL0_PORTSEL2_MASK (7 << SCU_PINTSEL0_PORTSEL2_SHIFT)
|
||||
#define SCU_PINTSEL0_INTPIN3_SHIFT (24) /* Bits 24-28: Pint interrupt 3 */
|
||||
#define SCU_PINTSEL0_INTPIN3_MASK (31 << SCU_PINTSEL0_INTPIN3_SHIFT)
|
||||
#define SCU_PINTSEL0_PORTSEL3_SHIFT (29) /* Bits 29-31: Pin interrupt 3 */
|
||||
#define SCU_PINTSEL0_PORTSEL3_MASK (7 << SCU_PINTSEL0_PORTSEL3_SHIFT)
|
||||
#define SCU_PINTSEL0_SHIFT(n) ((n) << 3)
|
||||
#define SCU_PINTSEL0_MASK(n) (0xff << SCU_PINTSEL0_SHIFT(n)))
|
||||
#define SCU_PINTSEL0_INTPIN_SHIFT(n) ((n) << 3)
|
||||
#define SCU_PINTSEL0_INTPIN_MASK(n) (31 << SCU_PINTSEL0_INTPIN_SHIFT(n))
|
||||
#define SCU_PINTSEL0_PORTSEL_SHIFT(n) (((n) << 3) + 5)
|
||||
#define SCU_PINTSEL0_PORTSEL_MASK(n) (7 << SCU_PINTSEL0_PORTSEL_SHIFT(n))
|
||||
|
||||
#define SCU_PINTSEL0_INTPIN0_SHIFT (0) /* Bits 0-4: Pint interrupt 0 */
|
||||
#define SCU_PINTSEL0_INTPIN0_MASK (31 << SCU_PINTSEL0_INTPIN0_SHIFT)
|
||||
#define SCU_PINTSEL0_PORTSEL0_SHIFT (5) /* Bits 5-7: Pin interrupt 0 */
|
||||
#define SCU_PINTSEL0_PORTSEL0_MASK (7 << SCU_PINTSEL0_PORTSEL0_SHIFT)
|
||||
#define SCU_PINTSEL0_INTPIN1_SHIFT (8) /* Bits 8-12: Pint interrupt 1 */
|
||||
#define SCU_PINTSEL0_INTPIN1_MASK (31 << SCU_PINTSEL0_INTPIN1_SHIFT)
|
||||
#define SCU_PINTSEL0_PORTSEL1_SHIFT (13) /* Bits 13-15: Pin interrupt 1 */
|
||||
#define SCU_PINTSEL0_PORTSEL1_MASK (7 << SCU_PINTSEL0_PORTSEL1_SHIFT)
|
||||
#define SCU_PINTSEL0_INTPIN2_SHIFT (16) /* Bits 16-20: Pint interrupt 2 */
|
||||
#define SCU_PINTSEL0_INTPIN2_MASK (31 << SCU_PINTSEL0_INTPIN2_SHIFT)
|
||||
#define SCU_PINTSEL0_PORTSEL2_SHIFT (21) /* Bits 21-23: Pin interrupt 2 */
|
||||
#define SCU_PINTSEL0_PORTSEL2_MASK (7 << SCU_PINTSEL0_PORTSEL2_SHIFT)
|
||||
#define SCU_PINTSEL0_INTPIN3_SHIFT (24) /* Bits 24-28: Pint interrupt 3 */
|
||||
#define SCU_PINTSEL0_INTPIN3_MASK (31 << SCU_PINTSEL0_INTPIN3_SHIFT)
|
||||
#define SCU_PINTSEL0_PORTSEL3_SHIFT (29) /* Bits 29-31: Pin interrupt 3 */
|
||||
#define SCU_PINTSEL0_PORTSEL3_MASK (7 << SCU_PINTSEL0_PORTSEL3_SHIFT)
|
||||
|
||||
/* Pin interrupt select register 1 */
|
||||
|
||||
#define SCU_PINTSEL1_INTPIN4_SHIFT (0) /* Bits 0-4: Pint interrupt 4 */
|
||||
#define SCU_PINTSEL1_INTPIN4_MASK (31 << SCU_PINTSEL1_INTPIN4_SHIFT)
|
||||
#define SCU_PINTSEL1_PORTSEL4_SHIFT (5) /* Bits 5-7: Pin interrupt 4 */
|
||||
#define SCU_PINTSEL1_PORTSEL4_MASK (7 << SCU_PINTSEL1_PORTSEL4_SHIFT)
|
||||
#define SCU_PINTSEL1_INTPIN5_SHIFT (8) /* Bits 8-12: Pint interrupt 5 */
|
||||
#define SCU_PINTSEL1_INTPIN5_MASK (31 << SCU_PINTSEL1_INTPIN5_SHIFT)
|
||||
#define SCU_PINTSEL1_PORTSEL5_SHIFT (13) /* Bits 13-15: Pin interrupt 5 */
|
||||
#define SCU_PINTSEL1_PORTSEL5_MASK (7 << SCU_PINTSEL1_PORTSEL5_SHIFT)
|
||||
#define SCU_PINTSEL1_INTPIN6_SHIFT (16) /* Bits 16-20: Pint interrupt 6 */
|
||||
#define SCU_PINTSEL1_INTPIN6_MASK (31 << SCU_PINTSEL1_INTPIN6_SHIFT)
|
||||
#define SCU_PINTSEL1_PORTSEL6_SHIFT (21) /* Bits 21-23: Pin interrupt 6 */
|
||||
#define SCU_PINTSEL1_PORTSEL6_MASK (7 << SCU_PINTSEL1_PORTSEL6_SHIFT)
|
||||
#define SCU_PINTSEL1_INTPIN7_SHIFT (24) /* Bits 24-28: Pint interrupt 7 */
|
||||
#define SCU_PINTSEL1_INTPIN7_MASK (31 << SCU_PINTSEL1_INTPIN7_SHIFT)
|
||||
#define SCU_PINTSEL1_PORTSEL7_SHIFT (29) /* Bits 29-31: Pin interrupt 7 */
|
||||
#define SCU_PINTSEL1_PORTSEL7_MASK (7 << SCU_PINTSEL1_PORTSEL7_SHIFT)
|
||||
#define SCU_PINTSEL1_SHIFT(n) (((n) - 4) << 3)
|
||||
#define SCU_PINTSEL1_MASK(n) (0xff << SCU_PINTSEL1_SHIFT(n))
|
||||
#define SCU_PINTSEL1_INTPIN_SHIFT(n) (((n) - 4) << 3)
|
||||
#define SCU_PINTSEL1_INTPIN_MASK(n) (31 << SCU_PINTSEL0_INTPIN_SHIFT(n))
|
||||
#define SCU_PINTSEL1_PORTSEL_SHIFT(n) ((((n) - 4) << 3) + 5)
|
||||
#define SCU_PINTSEL1_PORTSEL_MASK(n) (7 << SCU_PINTSEL0_PORTSEL_SHIFT(n))
|
||||
|
||||
#define SCU_PINTSEL1_INTPIN4_SHIFT (0) /* Bits 0-4: Pint interrupt 4 */
|
||||
#define SCU_PINTSEL1_INTPIN4_MASK (31 << SCU_PINTSEL1_INTPIN4_SHIFT)
|
||||
#define SCU_PINTSEL1_PORTSEL4_SHIFT (5) /* Bits 5-7: Pin interrupt 4 */
|
||||
#define SCU_PINTSEL1_PORTSEL4_MASK (7 << SCU_PINTSEL1_PORTSEL4_SHIFT)
|
||||
#define SCU_PINTSEL1_INTPIN5_SHIFT (8) /* Bits 8-12: Pint interrupt 5 */
|
||||
#define SCU_PINTSEL1_INTPIN5_MASK (31 << SCU_PINTSEL1_INTPIN5_SHIFT)
|
||||
#define SCU_PINTSEL1_PORTSEL5_SHIFT (13) /* Bits 13-15: Pin interrupt 5 */
|
||||
#define SCU_PINTSEL1_PORTSEL5_MASK (7 << SCU_PINTSEL1_PORTSEL5_SHIFT)
|
||||
#define SCU_PINTSEL1_INTPIN6_SHIFT (16) /* Bits 16-20: Pint interrupt 6 */
|
||||
#define SCU_PINTSEL1_INTPIN6_MASK (31 << SCU_PINTSEL1_INTPIN6_SHIFT)
|
||||
#define SCU_PINTSEL1_PORTSEL6_SHIFT (21) /* Bits 21-23: Pin interrupt 6 */
|
||||
#define SCU_PINTSEL1_PORTSEL6_MASK (7 << SCU_PINTSEL1_PORTSEL6_SHIFT)
|
||||
#define SCU_PINTSEL1_INTPIN7_SHIFT (24) /* Bits 24-28: Pint interrupt 7 */
|
||||
#define SCU_PINTSEL1_INTPIN7_MASK (31 << SCU_PINTSEL1_INTPIN7_SHIFT)
|
||||
#define SCU_PINTSEL1_PORTSEL7_SHIFT (29) /* Bits 29-31: Pin interrupt 7 */
|
||||
#define SCU_PINTSEL1_PORTSEL7_MASK (7 << SCU_PINTSEL1_PORTSEL7_SHIFT)
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Types
|
||||
|
|
|
|||
|
|
@ -84,12 +84,6 @@ static inline void lpc43_configinput(uint16_t gpiocfg,
|
|||
uintptr_t regaddr;
|
||||
uint32_t regval;
|
||||
|
||||
/* Make sure that the pin is *not* configured as an interrupt */
|
||||
|
||||
#ifdef CONFIG_GPIO_IRQ
|
||||
(void)lpc43_gpioint_unconfig(gpiocfg)
|
||||
#endif
|
||||
|
||||
/* Then configure the pin as a normal input by clearing the corresponding
|
||||
* bit in the GPIO DIR register for the port.
|
||||
*/
|
||||
|
|
@ -125,12 +119,6 @@ static inline void lpc43_configoutput(uint16_t gpiocfg,
|
|||
uintptr_t regaddr;
|
||||
uint32_t regval;
|
||||
|
||||
/* Make sure that the pin is *not* configured as an interrupt */
|
||||
|
||||
#ifdef CONFIG_GPIO_IRQ
|
||||
(void)lpc43_gpioint_unconfig(gpiocfg)
|
||||
#endif
|
||||
|
||||
/* Then configure the pin as an output by setting the corresponding
|
||||
* bit in the GPIO DIR register for the port.
|
||||
*/
|
||||
|
|
@ -181,18 +169,25 @@ int lpc43_gpio_config(uint16_t gpiocfg)
|
|||
flags = irqsave();
|
||||
switch (gpiocfg & GPIO_PORT_MASK)
|
||||
{
|
||||
case GPIO_MODE_INPUT:
|
||||
case GPIO_MODE_INPUT: /* GPIO input pin */
|
||||
lpc43_configinput(gpiocfg, port, pin);
|
||||
break;
|
||||
|
||||
case GPIO_MODE_OUTPUT:
|
||||
case GPIO_MODE_OUTPUT: /* GPIO output pin */
|
||||
lpc43_configoutput(gpiocfg, port, pin);
|
||||
break;
|
||||
|
||||
case GPIO_MODE_INTERRUPT:
|
||||
case GPIO_MODE_PININTR: /* GPIO pin interrupt */
|
||||
lpc43_configinput(gpiocfg, port, pin);
|
||||
#ifdef CONFIG_GPIO_IRQ
|
||||
ret = lpc43_gpiointconfig(gpiocfg, port, pin);
|
||||
ret = lpc43_gpioint_pinconfig(gpiocfg);
|
||||
#endif
|
||||
break;
|
||||
|
||||
case GPIO_MODE_GRPINTR: /* GPIO group interrupt */
|
||||
lpc43_configinput(gpiocfg, port, pin);
|
||||
#ifdef CONFIG_GPIO_IRQ
|
||||
ret = lpc43_gpioint_grpconfig(gpiocfg);
|
||||
#endif
|
||||
break;
|
||||
|
||||
|
|
|
|||
|
|
@ -56,17 +56,19 @@
|
|||
|
||||
#define NUM_GPIO_PORTS 8
|
||||
#define NUM_GPIO_PINS 32
|
||||
#define NUM_GPIO_NGROUPS 2
|
||||
|
||||
/* Each configurable pin can be individually configured by software in several modes. The
|
||||
* following definitions provide the bit encoding that is used to define a pin configuration.
|
||||
* Note that these pins do not corresponding GPIO ports and pins.
|
||||
*
|
||||
* 16-bit Encoding:
|
||||
* 1111 1100 0000 0000
|
||||
* 5432 1098 7654 3210
|
||||
* ---- ---- ---- ----
|
||||
* Normal: .MMV .... PPPB BBBB
|
||||
* Interrupt: .MMG GPII PPPB BBBB
|
||||
* 1111 1100 0000 0000
|
||||
* 5432 1098 7654 3210
|
||||
* ---- ---- ---- ----
|
||||
* Normal GPIO: MMV. .... PPPB BBBB
|
||||
* Normal Interrupt: MMCC CIII PPPB BBBB
|
||||
* Group Interrupt: MM.N P.. PPPB BBBB
|
||||
*/
|
||||
|
||||
/* GPIO mode:
|
||||
|
|
@ -74,91 +76,108 @@
|
|||
* 1111 1100 0000 0000
|
||||
* 5432 1098 7654 3210
|
||||
* ---- ---- ---- ----
|
||||
* .MM. .... .... ....
|
||||
* MM.. .... .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_MODE_SHIFT (13) /* Bits 13-14: Mode of the GPIO pin */
|
||||
#define GPIO_MODE_SHIFT (14) /* Bits 14-15: Mode of the GPIO pin */
|
||||
#define GPIO_MODE_MASK (3 << GPIO_MODE_SHIFT)
|
||||
# define GPIO_MODE_INPUT (1 << GPIO_MODE_SHIFT)
|
||||
# define GPIO_MODE_OUTPUT (2 << GPIO_MODE_SHIFT)
|
||||
# define GPIO_MODE_INTERRUPT (3 << GPIO_MODE_SHIFT)
|
||||
# define GPIO_MODE_INPUT (0 << GPIO_MODE_SHIFT) /* GPIO input */
|
||||
# define GPIO_MODE_OUTPUT (1 << GPIO_MODE_SHIFT) /* GPIO output */
|
||||
# define GPIO_MODE_PININTR (2 << GPIO_MODE_SHIFT) /* GPIO pin interrupt */
|
||||
# define GPIO_MODE_GRPINTR (3 << GPIO_MODE_SHIFT) /* GPIO group interrupt */
|
||||
|
||||
#define GPIO_IS_OUTPUT(p) (((p) & GPIO_MODE_MASK) == GPIO_MODE_INPUT)
|
||||
#define GPIO_IS_INPUT(p) (((p) & GPIO_MODE_MASK) == GPIO_MODE_OUTPUT)
|
||||
#define GPIO_IS_INTERRUPT(p) (((p) & GPIO_MODE_MASK) == GPIO_MODE_INTERRUPT)
|
||||
#define GPIO_IS_PININT(p) (((p) & GPIO_MODE_MASK) == GPIO_MODE_PININTR)
|
||||
#define GPIO_IS_GRPINTR(p) (((p) & GPIO_MODE_MASK) == GPIO_MODE_GRPINTR)
|
||||
|
||||
/* Initial value (for GPIO outputs only)
|
||||
*
|
||||
* 1111 1100 0000 0000
|
||||
* 5432 1098 7654 3210
|
||||
* ---- ---- ---- ----
|
||||
* ...V .... .... ....
|
||||
* ..V. .... .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_VALUE_ONE (1 << 12) /* Bit 12: 1=High */
|
||||
#define GPIO_VALUE_ZERO (0) /* Bit 12: 0=Low */
|
||||
#define GPIO_VALUE_ONE (1 << 13) /* Bit 13: 1=High */
|
||||
#define GPIO_VALUE_ZERO (0) /* Bit 13: 0=Low */
|
||||
|
||||
#define GPIO_IS_ONE(p) (((p) & GPIO_VALUE_ONE) != 0)
|
||||
#define GPIO_IS_ZERO(p) (((p) & GPIO_VALUE_ONE) == 0)
|
||||
|
||||
/* Group Interrupt Selection (valid only for interrupt GPIO pins):
|
||||
/* Group Interrupt Group Selection (valid only for GPIO group interrupts):
|
||||
*
|
||||
* 1111 1100 0000 0000
|
||||
* 5432 1098 7654 3210
|
||||
* ---- ---- ---- ----
|
||||
* ...G G... .... ....
|
||||
* ...N .... .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_GRPINT_SHIFT (11) /* Bits 11-12: Group interrupt selection */
|
||||
#define GPIO_GRPINT_MASK (3 << GPIO_GRPINT_SHIFT)
|
||||
# define GPIO_GRPINT_NOGROUP (0 << GPIO_GRPINT_SHIFT) /* 00 Not a member of a group */
|
||||
# define GPIO_GRPINT_GROUP0 (2 << GPIO_GRPINT_SHIFT) /* 10 Member of group 0 */
|
||||
# define GPIO_GRPINT_GROUP1 (3 << GPIO_GRPINT_SHIFT) /* 11 Member of group 1 */
|
||||
#define GPIO_GRPINT_GROUPNO (1 << 12) /* Bit 12: 1=Member of group 1 */
|
||||
#define GPIO_GRPINT_GROUP0 (0)
|
||||
#define GPIO_GRPINT_GROUP1 GPIO_GRPINT_GROUPNO
|
||||
|
||||
#define _GPIO_GRPINT (1 << (GPIO_GRPINT_SHIFT+1)) /* Bit 12: 1=Member of a group */
|
||||
#define _GPIO_GRPNO (1 << GPIO_GRPINT_SHIFT) /* Bit 11: Group number */
|
||||
#define GPIO_IS_GROUP0(p) (((p) & GPIO_GRPINT_GROUPNO) == 0)
|
||||
#define GPIO_IS_GROUP1(p) (((p) & GPIO_GRPINT_GROUPNO) != 0)
|
||||
|
||||
#define GPIO_IS_GRPINT(p) (((p) & _GPIO_GRPINT) != 0)
|
||||
#define GPIO_GRPPNO(p) (((p) & _GPIO_GRPNO) >> GPIO_GRPINT_SHIFT)
|
||||
|
||||
/* Group Interrupt Polarity (valid only for interrupt GPIO group interrupts ):
|
||||
/* Group Interrupt Polarity (valid only for GPIO group interrupts):
|
||||
*
|
||||
* 1111 1100 0000 0000
|
||||
* 5432 1098 7654 3210
|
||||
* ---- ---- ---- ----
|
||||
* .... .P.. .... ....
|
||||
* .... P... .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_POLARITY (1 << 10) /* Bit 10: Group Polarity */
|
||||
|
||||
#define GPIO_POLARITY (1 << 11) /* Bit 11: Group Polarity */
|
||||
#define GPIO_POLARITY_HI GPIO_POLARITY
|
||||
#define GPIO_POLARITY_LOW 0
|
||||
|
||||
#define GPIO_IS_POLARITY_HI(p) (((p) & GPIO_POLARITY) != 0)
|
||||
#define GPIO_IS_POLARITY_LOW(p) (((p) & GPIO_POLARITY) == 0)
|
||||
|
||||
/* Interrupt Configuration (valid only for interrupt GPIO pins):
|
||||
/* Pin interrupt number (valid only for GPIO pin interrupts)
|
||||
*
|
||||
* 1111 1100 0000 0000
|
||||
* 5432 1098 7654 3210
|
||||
* ---- ---- ---- ----
|
||||
* .... ..II .... ....
|
||||
* ..CC C... .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_INT_SHIFT (8) /* Bits 8-9: Interrupt mode */
|
||||
#define GPIO_INT_MASK (3 << GPIO_INT_SHIFT)
|
||||
# define GPIO_INT_LEVEL_LOW (0 << GPIO_INT_SHIFT) /* 00 Edge=NO, Active=LOW */
|
||||
# define GPIO_INT_LEVEL_HI (1 << GPIO_INT_SHIFT) /* 01 Edge=NO, Active=HIGH */
|
||||
# define GPIO_INT_EDGE_FALLING (2 << GPIO_INT_SHIFT) /* 10 Edge=YES, Active=LOW */
|
||||
# define GPIO_INT_EDGE_RISING (3 << GPIO_INT_SHIFT) /* 11 Edge=YES, Active=LOW */
|
||||
#define GPIO_PININT_SHIFT (10) /* Bits 11-13: Pin interrupt number */
|
||||
#define GPIO_PININT_MASK (7 << GPIO_PININT_SHIFT)
|
||||
# define GPIO_PININT0 (0 << GPIO_PININT_SHIFT)
|
||||
# define GPIO_PININT1 (1 << GPIO_PININT_SHIFT)
|
||||
# define GPIO_PININT2 (2 << GPIO_PININT_SHIFT)
|
||||
# define GPIO_PININT3 (3 << GPIO_PININT_SHIFT)
|
||||
# define GPIO_PININT4 (4 << GPIO_PININT_SHIFT)
|
||||
# define GPIO_PININT5 (5 << GPIO_PININT_SHIFT)
|
||||
# define GPIO_PININT6 (6 << GPIO_PININT_SHIFT)
|
||||
# define GPIO_PININT7 (7 << GPIO_PININT_SHIFT)
|
||||
|
||||
#define _GPIO_ACTIVE_HI (1 << GPIO_INT_SHIFT)
|
||||
#define _GPIO_EDGE (1 << (GPIO_INT_SHIFT+1))
|
||||
/* Pin interrupt configuration (valid only for GPIO pin interrupts)
|
||||
*
|
||||
* 1111 1100 0000 0000
|
||||
* 5432 1098 7654 3210
|
||||
* ---- ---- ---- ----
|
||||
* .... .III .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_IS_ACTIVE_HI(p) (((p) & _GPIO_ACTIVE_HI) != 0)
|
||||
#define GPIO_IS_ACTIVE_LOW(p) (((p) & _GPIO_ACTIVE_HI) == 0)
|
||||
#define GPIO_IS_EDGE(p) (((p) & _GPIO_EDGE) != 0)
|
||||
#define GPIO_IS_LEVEL(p) (((p) & _GPIO_EDGE) == 0)
|
||||
#define _GPIO_INT_LEVEL (1 << 10) /* Bit 10: 1=Level (vs edge) */
|
||||
#define _GPIO_INT_HIGH (1 << 9) /* Bit 9: 1=High level or rising edge */
|
||||
#define _GPIO_INT_LOW (1 << 8) /* Bit 8: 1=Low level or falling edge */
|
||||
|
||||
#define GPIO_INT_SHIFT (8) /* Bits 8-10: Interrupt mode */
|
||||
#define GPIO_INT_MASK (7 << GPIO_INT_SHIFT)
|
||||
# define GPIO_INT_LEVEL_HI (1 << GPIO_INT_SHIFT) /* 001 Edge=NO LOW=0 HIGH=1 */
|
||||
# define GPIO_INT_LEVEL_LOW (2 << GPIO_INT_SHIFT) /* 010 Edge=NO LOW=1 HIGH=0 */
|
||||
# define GPIO_INT_EDGE_RISING (5 << GPIO_INT_SHIFT) /* 101 Edge=YES LOW=0 HIGH=1 */
|
||||
# define GPIO_INT_EDGE_FALLING (6 << GPIO_INT_SHIFT) /* 110 Edge=YES LOW=1 HIGH=0 */
|
||||
# define GPIO_INT_EDGE_BOTH (7 << GPIO_INT_SHIFT) /* 111 Edge=YES LOW=1 HIGH=1 */
|
||||
|
||||
#define GPIO_IS_ACTIVE_HI(p) (((p) & _GPIO_INT_HIGH) != 0)
|
||||
#define GPIO_IS_ACTIVE_LOW(p) (((p) & _GPIO_INT_LOW) != 0)
|
||||
#define GPIO_IS_EDGE(p) (((p) & _GPIO_INT_LEVEL) == 0)
|
||||
#define GPIO_IS_LEVEL(p) (((p) & _GPIO_INT_LEVEL) != 0)
|
||||
|
||||
/* GPIO Port Number:
|
||||
*
|
||||
|
|
|
|||
|
|
@ -59,6 +59,8 @@
|
|||
#include <nuttx/arch.h>
|
||||
#include <errno.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "chip/lpc43_scu.h"
|
||||
#include "lpc43_gpioint.h"
|
||||
|
||||
#ifdef CONFIG_GPIO_IRQ
|
||||
|
|
@ -80,77 +82,235 @@
|
|||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc43_gpioint_initialize
|
||||
* Name: lpc43_gpioint_grpinitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize logic to interrupting GPIO pins GPIO pins
|
||||
* Initialize the properties of a GPIO group. The properties of the group
|
||||
* should be configured before any pins are added to the group by
|
||||
* lpc32_gpioint_grpconfig(). As side effects, this call also removes
|
||||
* all pins from the group and disables the group interrupt. On return,
|
||||
* this is a properly configured, empty GPIO interrupt group.
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero on success; a negated errno value on failure.
|
||||
*
|
||||
* Assumptions:
|
||||
* Interrupts are disabled so that read-modify-write operations are safe.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void lpc43_gpioint_initialize(void)
|
||||
int lpc43_gpioint_grpinitialize(int group, bool anded, bool level)
|
||||
{
|
||||
#warning "Missing logic"
|
||||
irqstate_t flags;
|
||||
uintptr_t grpbase;
|
||||
uint32_t regval;
|
||||
int i;
|
||||
|
||||
DEBUGASSERT(group >= 0 && group < NUM_GPIO_NGROUPS);
|
||||
|
||||
/* Select the group register base address and disable the group interrupt */
|
||||
|
||||
flags = irqsave();
|
||||
if (group == 0)
|
||||
{
|
||||
grpbase = LPC43_GRP0INT_BASE;
|
||||
up_disable_irq(LPC43M4_IRQ_GINT0);
|
||||
}
|
||||
else
|
||||
{
|
||||
grpbase = LPC43_GRP1INT_BASE;
|
||||
up_disable_irq(LPC43M4_IRQ_GINT1);
|
||||
}
|
||||
|
||||
/* Clear all group polarity and membership settings */
|
||||
|
||||
for (i = 0; i < NUM_GPIO_PORTS; i++)
|
||||
{
|
||||
putreg32(0, grpbase + LPC43_GRPINT_POL_OFFSET(i));
|
||||
putreg32(0, grpbase + LPC43_GRPINT_ENA_OFFSET(i));
|
||||
}
|
||||
|
||||
/* Configure the group. Note that writing "1" to the status bit will also
|
||||
* clear any pending group interrupts.
|
||||
*/
|
||||
|
||||
regval = GRPINT_CTRL_INT;
|
||||
if (anded)
|
||||
{
|
||||
regval |= GRPINT_CTRL_COMB;
|
||||
}
|
||||
|
||||
if (level)
|
||||
{
|
||||
regval |= GRPINT_CTRL_TRIG;
|
||||
}
|
||||
putreg32(regbal, grpbase + LPC43_GRP1INT_CTRL_OFFSET);
|
||||
|
||||
irqrestore(flags);
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc43_gpioint_config
|
||||
* Name: lpc43_gpioint_pinconfig
|
||||
*
|
||||
* Description:
|
||||
* Configure a GPIO pin as an interrupt source (after it has been
|
||||
* Configure a GPIO pin as an GPIO pin interrupt source (after it has been
|
||||
* configured as an input).
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero on success; a negated errno value on failure.
|
||||
*
|
||||
* Assumptions:
|
||||
* Interrupts are disabled so that read-modify-write operations are safe.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int lpc43_gpioint_config(uint16_t gpiocfg)
|
||||
int lpc43_gpioint_pinconfig(uint16_t gpiocfg)
|
||||
{
|
||||
#warning "Missing logic"
|
||||
return -ENOSYS;
|
||||
unsigned int port = ((gpiocfg & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT);
|
||||
unsigned int pin = ((gpiocfg & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT);
|
||||
unsigned int pinint = ((gpiocfg & GPIO_PININT_MASK) >> GPIO_PININT_SHIFT);
|
||||
uint32_t bitmask = (1 << pinint);
|
||||
uint32_t regval;
|
||||
int ret = OK;
|
||||
|
||||
DEBUGASSERT(port < NUM_GPIO_PORTS && pin < NUM_GPIO_PINS && GPIO_IS_PININT(gpiocfg));
|
||||
|
||||
/* Make sure that pin interrupts are initially disabled at the NVIC.
|
||||
* After the pin is configured, the caller will need to manually enable
|
||||
* the pin interrupt.
|
||||
*/
|
||||
|
||||
up_disable_irq(LPC43M4_IRQ_PININT0 + pinint);
|
||||
|
||||
/* Select the pin as the input in the SCU PINTSELn register (overwriting any
|
||||
* previous selection).
|
||||
*/
|
||||
|
||||
if (pinint < 4)
|
||||
{
|
||||
regval = getreg32(LPC43_SCU_PINTSEL0);
|
||||
regval &= ~SCU_PINTSEL0_MASK(pinint);
|
||||
regval |= ((pin << SCU_PINTSEL0_INTPIN_SHIFT(pinint)) |
|
||||
(port << SCU_PINTSEL0_PORTSEL_SHIFT(pinint)));
|
||||
putreg32(regval, LPC43_SCU_PINTSEL0);
|
||||
}
|
||||
else
|
||||
{
|
||||
regval = getreg32(LPC43_SCU_PINTSEL1);
|
||||
regval &= ~SCU_PINTSEL1_MASK(pinint);
|
||||
regval |= ((pin << SCU_PINTSEL1_INTPIN_SHIFT(pinint)) |
|
||||
(port << SCU_PINTSEL1_PORTSEL_SHIFT(pinint)));
|
||||
putreg32(regval, LPC43_SCU_PINTSEL1);
|
||||
}
|
||||
|
||||
/* Set level or edge sensitive */
|
||||
|
||||
regval = getreg32(LPC43_GPIOINT_ISEL);
|
||||
if (GPIO_IS_LEVEL(gpiocfg))
|
||||
{
|
||||
regval |= bitmask;
|
||||
}
|
||||
else
|
||||
{
|
||||
regval &= ~bitmask;
|
||||
}
|
||||
putreg32(regval, LPC43_GPIOINT_ISEL);
|
||||
|
||||
/* Configure the active high level or rising edge */
|
||||
|
||||
regval = getreg32(LPC43_GPIOINT_IENR);
|
||||
if (GPIO_IS_ACTIVE_HI(gpiocfg))
|
||||
{
|
||||
regval |= bitmask;
|
||||
}
|
||||
else
|
||||
{
|
||||
regval &= ~bitmask;
|
||||
}
|
||||
putreg32(regval, LPC43_GPIOINT_IENR);
|
||||
|
||||
/* Configure the active high low or falling edge */
|
||||
|
||||
regval = getreg32(LPC43_GPIOINT_IENF);
|
||||
if (GPIO_IS_ACTIVE_LOW(gpiocfg))
|
||||
{
|
||||
regval |= bitmask;
|
||||
}
|
||||
else
|
||||
{
|
||||
regval &= ~bitmask;
|
||||
}
|
||||
putreg32(regval, LPC43_GPIOINT_IENF);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc43_gpiointconfig
|
||||
* Name: lpc43_gpioint_grpconfig
|
||||
*
|
||||
* Description:
|
||||
* Un-configure a GPIO pin as an interrupt source.
|
||||
* Configure a GPIO pin as an GPIO group interrupt member (after it has been
|
||||
* configured as an input).
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero on success; a negated errno value on failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int lpc43_gpioint_unconfig(uint16_t gpiocfg)
|
||||
{
|
||||
#warning "Missing logic"
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc43_gpioint_enable
|
||||
*
|
||||
* Description:
|
||||
* Enable the interrupt for specified GPIO IRQ
|
||||
* Assumptions:
|
||||
* Interrupts are disabled so that read-modify-write operations are safe.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void lpc43_gpioint_enable(int irq)
|
||||
int lpc43_gpioint_grpconfig(uint16_t gpiocfg)
|
||||
{
|
||||
#warning "Missing logic"
|
||||
}
|
||||
unsigned int port = ((gpiocfg & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT);
|
||||
unsigned int pin = ((gpiocfg & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT);
|
||||
irqstate_t flags;
|
||||
uintptr_t grpbase;
|
||||
uintptr_t regaddr;
|
||||
uint32_t regval;
|
||||
uint32_t bitmask = (1 << pin);
|
||||
int ret = OK;
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc43_gpioint_disable
|
||||
*
|
||||
* Description:
|
||||
* Disable the interrupt for specified GPIO IRQ
|
||||
*
|
||||
****************************************************************************/
|
||||
/* Select the group register base address */
|
||||
|
||||
void lpc43_gpioint_disable(int irq)
|
||||
{
|
||||
#warning "Missing logic"
|
||||
flags = irqsave();
|
||||
if (GPIO_IS_GROUP0(gpiocfg))
|
||||
{
|
||||
grpbase = LPC43_GRP0INT_BASE;
|
||||
}
|
||||
else
|
||||
{
|
||||
grpbase = LPC43_GRP1INT_BASE;
|
||||
}
|
||||
|
||||
/* Set/clear the polarity for this pin */
|
||||
|
||||
regaddr = grpbase + LPC43_GRPINT_POL_OFFSET(port);
|
||||
regval = getreg32(regaddr);
|
||||
|
||||
if (GPIO_IS_POLARITY_HI(gpiocfg))
|
||||
{
|
||||
regval |= bitmask;
|
||||
}
|
||||
else
|
||||
{
|
||||
regval &= ~bitmask;
|
||||
}
|
||||
|
||||
putreg32(regval, regaddr);
|
||||
|
||||
/* Set the corresponding bit in the port enable register so that this pin
|
||||
* will contribute to the group interrupt.
|
||||
*/
|
||||
|
||||
regaddr = grpbase + LPC43_GRPINT_ENA_OFFSET(port);
|
||||
regval = getreg32(regaddr);
|
||||
regval |= bitmask;
|
||||
putreg32(regval, regaddr);
|
||||
|
||||
irqrestore(flags);
|
||||
return OK;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_GPIO_IRQ */
|
||||
|
|
|
|||
|
|
@ -78,62 +78,63 @@
|
|||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: lpc43_gpioint_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize logic to interrupting GPIO pins GPIO pins
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
EXTERN void lpc43_gpioint_initialize(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc43_gpioint_config
|
||||
* Name: lpc43_gpioint_grpinitialize
|
||||
*
|
||||
* Description:
|
||||
* Configure a GPIO pin as an interrupt source (after it has been
|
||||
* configured as an input).
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
EXTERN int lpc43_gpioint_config(uint16_t gpiocfg);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc43_gpiointconfig
|
||||
*
|
||||
* Description:
|
||||
* Un-configure a GPIO pin as an interrupt source.
|
||||
* Initialize the properties of a GPIO group. The properties of the group
|
||||
* should be configured before any pins are added to the group by
|
||||
* lpc32_gpioint_grpconfig(). As side effects, this call also removes
|
||||
* all pins from the group and disables the group interrupt. On return,
|
||||
* this is a properly configured, empty GPIO interrupt group.
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero on success; a negated errno value on failure.
|
||||
*
|
||||
* Assumptions:
|
||||
* Interrupts are disabled so that read-modify-write operations are safe.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
EXTERN int lpc43_gpioint_unconfig(uint16_t gpiocfg);
|
||||
EXTERN int lpc43_gpioint_grpinitialize(int group, bool anded, bool level);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: lpc43_gpioint_enable
|
||||
/****************************************************************************
|
||||
* Name: lpc43_gpioint_pinconfig
|
||||
*
|
||||
* Description:
|
||||
* Configure a GPIO pin as an GPIO pin interrupt source (after it has been
|
||||
* configured as an input). This function should *not* be called directly
|
||||
* from user application code; user code should call this function only
|
||||
* indirectly through lpc32_gpio_config().
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero on success; a negated errno value on failure.
|
||||
*
|
||||
************************************************************************************/
|
||||
* Assumptions:
|
||||
* Interrupts are disabled so that read-modify-write operations are safe.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
EXTERN int lpc43_gpioint_enable(int irq);
|
||||
EXTERN int lpc43_gpioint_pinconfig(uint16_t gpiocfg);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: lpc43_gpioint_disable
|
||||
/****************************************************************************
|
||||
* Name: lpc43_gpioint_grpconfig
|
||||
*
|
||||
* Description:
|
||||
* Disable the interrupt for specified GPIO IRQ
|
||||
* Configure a GPIO pin as an GPIO group interrupt member (after it has been
|
||||
* configured as an input). This function should *not* be called directly
|
||||
* from user application code; user code should call this function only
|
||||
* indirectly through lpc32_gpio_config().
|
||||
*
|
||||
************************************************************************************/
|
||||
* Returned Value:
|
||||
* Zero on success; a negated errno value on failure.
|
||||
*
|
||||
* Assumptions:
|
||||
* Interrupts are disabled so that read-modify-write operations are safe.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
EXTERN void lpc43_gpioint_disable(int irq);
|
||||
EXTERN int lpc43_gpioint_grpconfig(uint16_t gpiocfg);
|
||||
|
||||
#endif /* CONFIG_GPIO_IRQ */
|
||||
#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_GPIOINT_H */
|
||||
|
|
|
|||
|
|
@ -357,12 +357,6 @@ void up_irqinitialize(void)
|
|||
|
||||
lpc43_dumpnvic("initial", LPC43M4_IRQ_NIRQS);
|
||||
|
||||
/* Initialize logic to interrupting GPIO pins GPIO pins */
|
||||
|
||||
#ifdef CONFIG_GPIO_IRQ
|
||||
lpc43_gpioint_initialize();
|
||||
#endif
|
||||
|
||||
/* And finally, enable interrupts */
|
||||
|
||||
#ifndef CONFIG_SUPPRESS_INTERRUPTS
|
||||
|
|
|
|||
Loading…
Reference in New Issue