NAS 5GS: upgrade remaining 5GSM IEs to v16.6.0
- IP header compression configuration - DS-TT Ethernet port MAC address - UE-DS-TT residence time - Port management information container - Ethernet header compression configuration
This commit is contained in:
Pascal Quantin
parent
533f21edfd
commit
d75fef88fb
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@ -381,6 +381,20 @@ static int hf_nas_5gs_sm_ept_s1 = -1;
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static int hf_nas_5gs_sm_abo = -1;
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static int hf_nas_5gs_sm_atsss_cont = -1;
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static int hf_nas_5gs_sm_cpoi = -1;
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static int hf_nas_5gs_sm_ip_hdr_comp_config_p0104 = -1;
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static int hf_nas_5gs_sm_ip_hdr_comp_config_p0103 = -1;
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static int hf_nas_5gs_sm_ip_hdr_comp_config_p0102 = -1;
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static int hf_nas_5gs_sm_ip_hdr_comp_config_p0006 = -1;
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static int hf_nas_5gs_sm_ip_hdr_comp_config_p0004 = -1;
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static int hf_nas_5gs_sm_ip_hdr_comp_config_p0003 = -1;
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static int hf_nas_5gs_sm_ip_hdr_comp_config_p0002 = -1;
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static int hf_nas_5gs_sm_ip_hdr_comp_config_max_cid = -1;
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static int hf_nas_5gs_sm_ip_hdr_comp_config_add_ip_hdr_compr_cxt_setup_params_type = -1;
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static int hf_nas_5gs_sm_ip_hdr_comp_config_add_ip_hdr_compr_cxt_setup_params_cont = -1;
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static int hf_nas_5gs_sm_ds_tt_eth_port_mac_addr = -1;
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static int hf_nas_5gs_sm_ue_ds_tt_residence_time = -1;
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static int hf_nas_5gs_sm_port_mgmt_info_cont = -1;
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static int hf_nas_5gs_sm_eth_hdr_comp_config_cid_len = -1;
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static int hf_nas_5gs_sm_sel_sc_mode = -1;
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static int hf_nas_5gs_sm_tpmic_b7 = -1;
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static int hf_nas_5gs_sm_atsss_st_b3_b6 = -1;
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@ -4770,14 +4784,52 @@ de_nas_5gs_sm_ctl_plane_only_ind(tvbuff_t* tvb, proto_tree* tree, packet_info* p
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return 1;
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}
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/*
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* 9.11.4.24 Header compression configuration
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* 9.11.4.24 IP header compression configuration
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*/
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static const value_string nas_5gs_sm_ip_hdr_comp_config_add_ip_hdr_compr_cxt_setup_params_type_vals[] = {
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{ 0x00, "0x0000 (No Compression)" },
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{ 0x01, "0x0002 (UDP/IP)" },
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{ 0x02, "0x0003 (ESP/IP)" },
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{ 0x03, "0x0004 (IP)" },
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{ 0x04, "0x0006 (TCP/IP)" },
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{ 0x05, "0x0102 (UDP/IP)" },
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{ 0x06, "0x0103 (ESP/IP)" },
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{ 0x07, "0x0104 (IP)" },
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{ 0x08, "Other" },
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{ 0x0, NULL }
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};
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static guint16
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de_nas_5gs_sm_ip_hdr_comp_conf(tvbuff_t* tvb, proto_tree* tree, packet_info* pinfo,
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de_nas_5gs_sm_ip_hdr_comp_conf(tvbuff_t* tvb, proto_tree* tree, packet_info* pinfo _U_,
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guint32 offset, guint len,
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gchar* add_string _U_, int string_len _U_)
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{
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proto_tree_add_expert(tree, pinfo, &ei_nas_5gs_ie_not_dis, tvb, offset, len);
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guint32 curr_offset = offset;
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static int * const flags[] = {
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&hf_nas_5gs_spare_b7,
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&hf_nas_5gs_sm_ip_hdr_comp_config_p0104,
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&hf_nas_5gs_sm_ip_hdr_comp_config_p0103,
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&hf_nas_5gs_sm_ip_hdr_comp_config_p0102,
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&hf_nas_5gs_sm_ip_hdr_comp_config_p0006,
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&hf_nas_5gs_sm_ip_hdr_comp_config_p0004,
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&hf_nas_5gs_sm_ip_hdr_comp_config_p0003,
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&hf_nas_5gs_sm_ip_hdr_comp_config_p0002,
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NULL
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};
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proto_tree_add_bitmask_list(tree, tvb, curr_offset, 1, flags, ENC_NA);
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curr_offset++;
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proto_tree_add_item(tree, hf_nas_5gs_sm_ip_hdr_comp_config_max_cid, tvb, curr_offset, 2, ENC_BIG_ENDIAN);
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curr_offset += 2;
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if ((curr_offset - offset) >= len) {
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return len;
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}
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proto_tree_add_item(tree, hf_nas_5gs_sm_ip_hdr_comp_config_add_ip_hdr_compr_cxt_setup_params_type, tvb, curr_offset, 1, ENC_BIG_ENDIAN);
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curr_offset++;
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proto_tree_add_item(tree, hf_nas_5gs_sm_ip_hdr_comp_config_add_ip_hdr_compr_cxt_setup_params_cont, tvb, curr_offset, len - (curr_offset - offset), ENC_NA);
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return len;
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}
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@ -4785,24 +4837,24 @@ de_nas_5gs_sm_ip_hdr_comp_conf(tvbuff_t* tvb, proto_tree* tree, packet_info* pin
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* 9.11.4.25 DS-TT Ethernet port MAC address
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*/
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static guint16
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de_nas_5gs_sm_ds_tt_eth_port_mac_addr(tvbuff_t* tvb, proto_tree* tree, packet_info* pinfo,
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de_nas_5gs_sm_ds_tt_eth_port_mac_addr(tvbuff_t* tvb, proto_tree* tree, packet_info* pinfo _U_,
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guint32 offset, guint len,
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gchar* add_string _U_, int string_len _U_)
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{
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proto_tree_add_expert(tree, pinfo, &ei_nas_5gs_ie_not_dis, tvb, offset, len);
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proto_tree_add_item(tree, hf_nas_5gs_sm_ds_tt_eth_port_mac_addr, tvb, offset, 6, ENC_NA);
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return len;
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}
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/*
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* 9.11.4.26 DS-TT residence time
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* 9.11.4.26 UE-DS-TT residence time
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*/
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static guint16
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de_nas_5gs_sm_ue_ds_tt_residence_t(tvbuff_t* tvb, proto_tree* tree, packet_info* pinfo,
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de_nas_5gs_sm_ue_ds_tt_residence_t(tvbuff_t* tvb, proto_tree* tree, packet_info* pinfo _U_,
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guint32 offset, guint len,
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gchar* add_string _U_, int string_len _U_)
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{
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proto_tree_add_expert(tree, pinfo, &ei_nas_5gs_ie_not_dis, tvb, offset, len);
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proto_tree_add_item(tree, hf_nas_5gs_sm_ue_ds_tt_residence_time, tvb, offset, 8, ENC_NA);
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return len;
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}
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@ -4811,11 +4863,11 @@ de_nas_5gs_sm_ue_ds_tt_residence_t(tvbuff_t* tvb, proto_tree* tree, packet_info*
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* 9.11.4.27 Port management information container
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*/
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static guint16
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de_nas_5gs_sm_port_mgnt_inf_cont(tvbuff_t* tvb, proto_tree* tree, packet_info* pinfo,
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de_nas_5gs_sm_port_mgnt_inf_cont(tvbuff_t* tvb, proto_tree* tree, packet_info* pinfo _U_,
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guint32 offset, guint len,
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gchar* add_string _U_, int string_len _U_)
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{
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proto_tree_add_expert(tree, pinfo, &ei_nas_5gs_ie_not_dis, tvb, offset, len);
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proto_tree_add_item(tree, hf_nas_5gs_sm_port_mgmt_info_cont, tvb, offset, len, ENC_NA);
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return len;
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}
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@ -4823,12 +4875,30 @@ de_nas_5gs_sm_port_mgnt_inf_cont(tvbuff_t* tvb, proto_tree* tree, packet_info* p
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/*
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* 9.11.4.28 Ethernet header compression configuration
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*/
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static const value_string nas_5gs_sm_eth_hdr_comp_config_cid_len_vals[] = {
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{ 0x0, "Ethernet header compression not used" },
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{ 0x1, "7 bits" },
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{ 0x2, "15 bits" },
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{ 0x0, NULL }
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};
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static guint16
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de_nas_5gs_sm_eth_hdr_comp_conf(tvbuff_t* tvb, proto_tree* tree, packet_info* pinfo,
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de_nas_5gs_sm_eth_hdr_comp_conf(tvbuff_t* tvb, proto_tree* tree, packet_info* pinfo _U_,
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guint32 offset, guint len,
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gchar* add_string _U_, int string_len _U_)
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{
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proto_tree_add_expert(tree, pinfo, &ei_nas_5gs_ie_not_dis, tvb, offset, len);
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static int * const flags[] = {
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&hf_nas_5gs_spare_b7,
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&hf_nas_5gs_spare_b6,
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&hf_nas_5gs_spare_b5,
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&hf_nas_5gs_spare_b4,
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&hf_nas_5gs_spare_b3,
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&hf_nas_5gs_spare_b2,
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&hf_nas_5gs_sm_eth_hdr_comp_config_cid_len,
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NULL
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};
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proto_tree_add_bitmask_list(tree, tvb, offset, 1, flags, ENC_NA);
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return len;
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}
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@ -9851,6 +9921,76 @@ proto_register_nas_5gs(void)
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FT_BOOLEAN, 8, TFS(&tfs_5gs_sm_cpoi), 0x01,
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NULL, HFILL }
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},
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{ &hf_nas_5gs_sm_ip_hdr_comp_config_p0104,
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{ "RoHC profile 0x0104 (IP)", "nas_5gs.sm.ip_hdr_comp_config.p0104",
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FT_BOOLEAN, 8, TFS(&tfs_supported_not_supported), 0x40,
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NULL, HFILL }
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},
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{ &hf_nas_5gs_sm_ip_hdr_comp_config_p0103,
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{ "RoHC profile 0x0103 (ESP/IP)", "nas_5gs.sm.ip_hdr_comp_config.p0103",
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FT_BOOLEAN, 8, TFS(&tfs_supported_not_supported), 0x20,
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NULL, HFILL }
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},
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{ &hf_nas_5gs_sm_ip_hdr_comp_config_p0102,
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{ "RoHC profile 0x0102 (UDP/IP)", "nas_5gs.sm.ip_hdr_comp_config.p0102",
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FT_BOOLEAN, 8, TFS(&tfs_supported_not_supported), 0x10,
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NULL, HFILL }
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},
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{ &hf_nas_5gs_sm_ip_hdr_comp_config_p0006,
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{ "RoHC profile 0x0006 (TCP/IP)", "nas_5gs.sm.ip_hdr_comp_config.p0006",
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FT_BOOLEAN, 8, TFS(&tfs_supported_not_supported), 0x08,
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NULL, HFILL }
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},
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{ &hf_nas_5gs_sm_ip_hdr_comp_config_p0004,
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{ "RoHC profile 0x0004 (IP)", "nas_5gs.sm.ip_hdr_comp_config.p0004",
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FT_BOOLEAN, 8, TFS(&tfs_supported_not_supported), 0x04,
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NULL, HFILL }
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},
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{ &hf_nas_5gs_sm_ip_hdr_comp_config_p0003,
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{ "RoHC profile 0x0003 (ESP/IP)", "nas_5gs.sm.ip_hdr_comp_config.p0003",
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FT_BOOLEAN, 8, TFS(&tfs_supported_not_supported), 0x02,
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NULL, HFILL }
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},
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{ &hf_nas_5gs_sm_ip_hdr_comp_config_p0002,
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{ "RoHC profile 0x0002 (UDP/IP)", "nas_5gs.sm.ip_hdr_comp_config.p0002",
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FT_BOOLEAN, 8, TFS(&tfs_supported_not_supported), 0x01,
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NULL, HFILL }
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},
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{ &hf_nas_5gs_sm_ip_hdr_comp_config_max_cid,
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{ "MAX_CID", "nas_5gs.sm.ip_hdr_comp_config.max_cid",
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FT_UINT16, BASE_DEC, NULL, 0x0,
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NULL, HFILL }
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},
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{ &hf_nas_5gs_sm_ip_hdr_comp_config_add_ip_hdr_compr_cxt_setup_params_type,
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{ "Additional header compression context setup parameters type", "nas_5gs.sm.ip_hdr_comp_config.add_hdr_compr_cxt_setup_params_type",
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FT_UINT8, BASE_HEX, VALS(nas_5gs_sm_ip_hdr_comp_config_add_ip_hdr_compr_cxt_setup_params_type_vals), 0x0,
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NULL, HFILL }
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},
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{ &hf_nas_5gs_sm_ip_hdr_comp_config_add_ip_hdr_compr_cxt_setup_params_cont,
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{ "Additional header compression context setup parameters container", "nas_5gs.sm.ip_hdr_comp_config.add_hdr_compr_cxt_setup_params_cont",
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FT_BYTES, BASE_NONE, NULL, 0x0,
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NULL, HFILL }
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},
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{ &hf_nas_5gs_sm_ds_tt_eth_port_mac_addr,
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{ "DS-TT Ethernet port MAC address", "nas_5gs.sm.ds_tt_eth_port_mac_addr",
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FT_ETHER, BASE_NONE, NULL, 0x0,
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NULL, HFILL }
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},
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{ &hf_nas_5gs_sm_ue_ds_tt_residence_time,
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{ "UE-DS-TT residence time", "nas_5gs.sm.ue_ds_tt_residence_time",
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FT_BYTES, BASE_NONE, NULL, 0x0,
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NULL, HFILL }
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},
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{ &hf_nas_5gs_sm_port_mgmt_info_cont,
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{ "Port management information container", "nas_5gs.sm.port_mgmt_info_cont",
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FT_BYTES, BASE_NONE, NULL, 0x0,
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NULL, HFILL }
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},
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{ &hf_nas_5gs_sm_eth_hdr_comp_config_cid_len,
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{ "Port management information container", "nas_5gs.sm.eth_hdr_comp_config.cid_len",
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FT_UINT8, BASE_DEC, VALS(nas_5gs_sm_eth_hdr_comp_config_cid_len_vals), 0x03,
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NULL, HFILL }
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},
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{ &hf_nas_5gs_sm_sel_sc_mode,
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{ "Selected SSC mode", "nas_5gs.sm.sel_sc_mode",
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FT_UINT8, BASE_DEC, VALS(nas_5gs_sc_mode_values), 0x70,
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@ -10227,17 +10367,17 @@ proto_register_nas_5gs(void)
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NULL, HFILL }
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},
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{ &hf_nas_5gs_mm_mauri,
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{ "MAURI", "nas_5gs.mm.mauri",
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{ "MAC address usage restriction indication (MAURI)", "nas_5gs.mm.mauri",
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FT_BOOLEAN, 8, TFS(&nas_5gs_mauri_tfs), 0x08,
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NULL, HFILL }
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},
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{ &hf_nas_5gs_mm_mac_addr,
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{ "MAURI", "nas_5gs.mm.mauri",
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{ "MAC address", "nas_5gs.mm.mac_addr",
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FT_ETHER, BASE_NONE, NULL, 0,
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NULL, HFILL }
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},
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{ &hf_nas_5gs_mm_eui_64,
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{ "MAURI", "nas_5gs.mm.mauri",
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{ "EUI-64", "nas_5gs.mm.eui_64",
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FT_EUI64, BASE_NONE, NULL, 0,
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NULL, HFILL }
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},
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