rlcmac: tests: Account for T3180 existance in test_ul_tbf_t3182_timeout

Test test_ul_tbf_t3182_timeout needs to be modified in order to avoid
triggering T3180 once it is implemented in a follow-up patch.
Both T3180 and T3182 are armed at the same time, so modify the scenario
to really scenify the case where T3182 matters: the MS keeps receiving USF
indications but the PCU doesn't see them and hence never sends a PKT UL
ACK/NACK acking the last block.

Related: OS#6209
Change-Id: I73b648bc04d863b9eb67093e5fa510ba88d712c8
This commit is contained in:
Pau Espin 2023-10-16 17:21:04 +02:00 committed by pespin
parent 8d347143ba
commit 72598d2c7f
2 changed files with 25 additions and 5 deletions

View File

@ -841,6 +841,7 @@ static void test_ul_tbf_t3182_timeout(bool acked_mode)
{
struct osmo_gprs_rlcmac_prim *rlcmac_prim;
int rc;
unsigned int i;
printf("=== %s start ===\n", __func__);
prepare_test();
@ -884,10 +885,26 @@ static void test_ul_tbf_t3182_timeout(bool acked_mode)
rc = osmo_gprs_rlcmac_prim_lower_up(rlcmac_prim);
OSMO_ASSERT(rc == 0);
/* Now T3182 is armed and will trigger in 5 seconds. */
if (acked_mode) {
/* Make sure we don't apply the max-4-cv0-tx limit as with unacked mode: */
unsigned int i;
/* Keep sending some USF-polling from PCU to avoid T3180 triggering.
* while at it, make sure we don't apply the max-4-cv0-tx limit as with unacked mode: */
for (i = 0; i < 5; i++) {
/* increase time 1 seconds, timeout should trigger */
clock_override_add(1, 0);
rts_fn = fn_next_block(rts_fn);
printf("RTS %u: FN=%u\n", i, rts_fn);
/* Trigger transmission of LLC data (GMM Attach) (second part) */
rlcmac_prim = osmo_gprs_rlcmac_prim_alloc_l1ctl_pdch_rts_ind(ts_nr, rts_fn, usf);
rc = osmo_gprs_rlcmac_prim_lower_up(rlcmac_prim);
OSMO_ASSERT(rc == 0);
}
} else {
for (i = 0; i < 2; i++) {
/* Keep sending some USF-polling from PCU to avoid T3180 triggering:
* increase time 2.500 seconds 2 times = 5s, */
clock_override_add(2, 500000);
rts_fn = fn_next_block(rts_fn);
printf("RTS %u: FN=%u\n", i, rts_fn);
/* Trigger transmission of LLC data (GMM Attach) (second part) */
@ -897,8 +914,7 @@ static void test_ul_tbf_t3182_timeout(bool acked_mode)
}
}
/* increase time 5 seconds, timeout should trigger */
clock_override_add(5, 0);
/* Timeout should trigger now: */
clock_debug("Expect T3182 timeout");
osmo_select_main(0);

View File

@ -129,17 +129,21 @@ test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=
test_rlcmac_prim_up_cb(): Rx GMMRR-LLC_TRANSMITTED.indication TLLI=0x00002342
test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_DATA.request fn=4 ts=7 data_len=34 data=[3c 01 01 00 00 23 42 01 c0 00 08 01 01 d5 71 00 00 08 29 26 24 00 00 00 00 71 62 f2 24 6c 84 44 04 00 ]
test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_DATA.request fn=8 ts=7 data_len=34 data=[00 00 02 1d 11 e5 10 00 e2 18 f2 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 00 ]
sys={1.000000}, mono={1.000000}: clock_override_add
RTS 0: FN=13
test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_DATA.request fn=13 ts=7 data_len=34 data=[00 00 02 1d 11 e5 10 00 e2 18 f2 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 00 ]
sys={2.000000}, mono={2.000000}: clock_override_add
RTS 1: FN=17
test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_DATA.request fn=17 ts=7 data_len=34 data=[00 00 02 1d 11 e5 10 00 e2 18 f2 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 00 ]
sys={3.000000}, mono={3.000000}: clock_override_add
RTS 2: FN=21
test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_DATA.request fn=21 ts=7 data_len=34 data=[00 00 02 1d 11 e5 10 00 e2 18 f2 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 00 ]
sys={4.000000}, mono={4.000000}: clock_override_add
RTS 3: FN=26
test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_DATA.request fn=26 ts=7 data_len=34 data=[00 00 02 1d 11 e5 10 00 e2 18 f2 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 00 ]
sys={5.000000}, mono={5.000000}: clock_override_add
RTS 4: FN=30
test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_DATA.request fn=30 ts=7 data_len=34 data=[00 00 02 1d 11 e5 10 00 e2 18 f2 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 00 ]
sys={5.000000}, mono={5.000000}: clock_override_add
sys={5.000000}, mono={5.000000}: Expect T3182 timeout
test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x00
=== test_ul_tbf_t3182_timeout end ===