If the master clock rate fails to set - this basically only happens
when the wrong transceiver is choosen for the particular device -
the error is fatal and the transceiver should exit. The clock rate
setting was previously never verified.
Signed-off-by: Thomas Tsou <ttsou@vt.edu>
Receive buffer flush should continue to read until
either the desired number of packets has been read or
timeout, which means that the buffer has been emptied.
These are expected behaviours and should return true.
Ignore errors at this stage as the data and associated
metadata can be considered garbage and not worth
reporting. Actual error conditions will be caught
further downstream when useful data comes in.
Signed-off-by: Thomas Tsou <ttsou@vt.edu>
Bump abnormal asynchronous events - basically send errors -
up to ERROR level. These errors are dominated almost
entirely by underflow events, which should not be regularly
occuring.
Signed-off-by: Thomas Tsou <ttsou@vt.edu>
UHD will internally accept floats with a range of +/-1.0,
which corresponds to a 16-bit signed integer range of
apporximately +/- 32000. Set the default amplitude to .3,
which is a safe value agaist saturation elsewhere in the
transmit chain.
The non-UHD maximum amplitude is unchanged at 13500.
Remove digital gain control because it's unnecessary and
causes extra load on enbedded systems.
Signed-off-by: Thomas Tsou <ttsou@vt.edu>
This is primarily a minor refactor with the exception
of non-recoverable errors - notably if the receive times
out - which almost always requires a reload of the FPGA.
In these cases, quit without trying as resistance is
futile.
ERROR_TIMING: Soft restart of streaming
ERROR_UNHANDLED: Benign errors
ERROR_UNRECOVERABLE: Abandon ship
Non-recoverable behaviour has not been observed in recent
builds, but may exist in older (or future) configurations.
Signed-off-by: Thomas Tsou <ttsou@vt.edu>
Overnight testing shows that this shouldn't be required
in the majority of cases, but shit happens. Enabling
this forces transmit timing realignment at one minute
intervals. As a fallback method, timing slips not
caught by normal checks will be reset at the update.
Signed-off-by: Thomas Tsou <ttsou@vt.edu>
At startup, instead of flushing initial packets blindly,
send a stop streaming command, flush, and start. The same
procedure is used in the event of a runtime timestamp
validity error.
Signed-off-by: Thomas Tsou <ttsou@vt.edu>
On a lapses of time monotonicity (and possibly other errors),
stop and restart the receive streaming with a buffer flush
in between. This is a cleaner replacement to the previous
clock reset with that didn't attempt to stop steaming.
Signed-off-by: Thomas Tsou <ttsou@vt.edu>
Type size_t was used in the UHD time_spec_t to integer
conversion, which would overflow at roughly 4 and a half
hours causing the sample buffer to error on timestamp
validity. Builds where size_t takes on 64-bits were not
affected by this bug.
Signed-off-by: Thomas Tsou <ttsou@vt.edu>
With UHD b4fc0d61bb6cbd1a5614745bab9aeb0abc22cb6f
Sample clock will reset to zero after an overrun. Earlier
versions may hang the FPGA, which is non-recoverable,
requiring a manual image reload or reboot.
If reset to zero, attempt to kick the sample clock to the
last properly received timestamp value. At this point,
there will be a timing continuity jump, which will drop
connections, but transmit and receive chains should be
aligned allowing for re-establishment.
Signed-off-by: Thomas Tsou <ttsou@vt.edu>
Use the same header files for the device and start moving
toward a commmon transceiver without so much redundant code.
Signed-off-by: Thomas Tsou <ttsou@vt.edu>
Shadow all gains and frequencies, which minimizes device access.
This allows the transceiver to variably control the device
settings.
Signed-off-by: Thomas Tsou <ttsou@vt.edu>
This shouldn't matter much, but the gain settings through the
interface are short circuited right now, which makes this a
problem.
Signed-off-by: Thomas Tsou <ttsou@vt.edu>
The value is used to align transmit and receive time slots within
a sample. This oscilloscope measured value is close, but may
need minor tweaking.
Signed-off-by: Thomas Tsou <ttsou@vt.edu>
Occasionally, the E100 will have errant timestamps at start
related to previous sessions. Early packets will be thrown
out anyways, so do this explicitly so the timestamps don't
royally fuck up the sample timing.
Signed-off-by: Thomas Tsou <ttsou@vt.edu>
Because I can't take it anymore...
Actually, I've been manually converting names to camel
case before checking in, which was an error prone process
in and of itself.
The interface is unchanged, so nobody should complain.
Signed-off-by: Thomas Tsou <ttsou@vt.edu>
Utilize start and stop burst flags more effectively to
manage interaction with the FPGA. This makes communication
slightly more explicit, though it is not expected to
have a major effect. Also, lower the alignment messages
to DEBUG, and raise the asynchronous messages to INFO.
In other words, report the underrun, but not the handling
of it.
Signed-off-by: Thomas Tsou <ttsou@vt.edu>
Though the receive loop ultimately drives the GSM clock,
it does not have any priority because it runs as a
separate thread from the trasmit loop. The transmit
has priority because it starts the UHD device, where
priority scheduling is enabled. The result is frequent
underruns, which occur regardless of buffer size tuning.
To address this, break out and expose the priority
setting so that it can be called from the radioInterface
at the start of a new thread.
Tested on a modest Intel Core 2 Duo tablet running
Linux 2.6.33.7.2-rt30, this reduced underruns down to
near zero.
Signed-off-by: Thomas Tsou <ttsou@vt.edu>
Currently, upon receiving an unexpected timestamp, the sample
buffer will error and log its internal state. The errant
timestamp is not logged though. This patch fixes that.
Signed-off-by: Thomas Tsou <ttsou@vt.edu>
Certain chipsets (e.g. RTL8168) have issues with the
initial packet of samples at that start of a UHD
receive stream resulting in timestamp errors shortly
after start. This temporary patch forces a receive
during init to clear any lingering errant packets.
Signed-off-by: Thomas Tsou <ttsou@vt.edu>
Recent UHD firmware for the USRP2/N210 replaces the MicroBlaze
with a slower ZPU in addition to changes to the control
transactions. The effect is less predictable reading of the
current time and Tx/Rx sample mis-alignment following
underruns.
After an underrun, this patch drops potentially stale packets
with a fixed interval instead of relying on reading the
current time from the device.
Signed-off-by: Thomas Tsou <ttsou@vt.edu>
The non-UHD implementation tunes the DDC to output an inverted
spectrum that requires swapping on the host. Push I/Q and byte
swapping into the device implementation and strip the related
bits out of the remaining transceiver code.
This also moves the Transceiver closer to the Transcever52M
version.
Signed-off-by: Thomas Tsou <ttsou@vt.edu>
Fixes the following build error.
UHDDevice.cpp:462: error: ‘EVENT_CODE_SUCCESS’ is not a member of ‘uhd::async_metadata_t’
UHDDevice.cpp:507: error: ‘EVENT_CODE_SUCCESS’ is not a member of ‘uhd::async_metadata_t’
Reported-by: Dirk Kirsten <Dirk.Kirsten@uni-konstanz.de>
Signed-off-by: Thomas Tsou <ttsou@vt.edu>
Fixes the following that occurs with recent uhd changes.
UHDDevice.cpp:260: error: ‘struct uhd::gain_range_t’ has no member named ‘max’
UHDDevice.cpp:260: error: ‘struct uhd::gain_range_t’ has no member named ‘min’
Signed-off-by: Thomas Tsou <ttsou@vt.edu>
This patch adds USRP2 device support and future support for
other UHD based devices. On receive, a sample buffer class,
which is indexable by timestamps, is used to temporarily
hold data until the requested samples are available.
On transmit, samples are sent immediately unless sample
alignment is known to be off - during startup or after the
occurrence of underruns or other errors. To regain
synchronization at these moments, timestamps are compared
against the current device time and dropped unless there
exists significant delay margin to physically arrive at the
device before deadline.
Signed-off-by: Thomas Tsou <ttsou@vt.edu>
Thomas Tsou