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uhd: verify setting of master clock rate

If the master clock rate fails to set - this basically only happens
when the wrong transceiver is choosen for the particular device -
the error is fatal and the transceiver should exit. The clock rate
setting was previously never verified.

Signed-off-by: Thomas Tsou <ttsou@vt.edu>
master
Thomas Tsou 11 years ago
parent f8838172ad
commit fda11abe6c
  1. 23
      public-trunk/Transceiver/UHDDevice.cpp
  2. 23
      public-trunk/Transceiver52M/UHDDevice.cpp

@ -292,22 +292,32 @@ void uhd_device::set_ref_clk(bool ext_clk)
double uhd_device::set_rates(double rate)
{
double actual_rate;
double actual_rt, actual_clk_rt;
// Set master clock rate
usrp_dev->set_master_clock_rate(master_clk_rt);
actual_clk_rt = usrp_dev->get_master_clock_rate();
if (actual_clk_rt != master_clk_rt) {
LOG(ERROR) << "Failed to set master clock rate";
return -1.0;
}
// Set sample rates
usrp_dev->set_tx_rate(rate);
usrp_dev->set_rx_rate(rate);
actual_rate = usrp_dev->get_tx_rate();
actual_rt = usrp_dev->get_tx_rate();
if (actual_rate != rate) {
if (actual_rt != rate) {
LOG(ERROR) << "Actual sample rate differs from desired rate";
return -1.0;
}
if (usrp_dev->get_rx_rate() != actual_rate) {
if (usrp_dev->get_rx_rate() != actual_rt) {
LOG(ERROR) << "Transmit and receive sample rates do not match";
return -1.0;
}
return actual_rate;
return actual_rt;
}
double uhd_device::setTxGain(double db)
@ -345,9 +355,6 @@ bool uhd_device::open()
return false;
}
// Set master clock rate
usrp_dev->set_master_clock_rate(master_clk_rt);
// Number of samples per over-the-wire packet
tx_spp = usrp_dev->get_device()->get_max_send_samps_per_packet();
rx_spp = usrp_dev->get_device()->get_max_recv_samps_per_packet();

@ -292,22 +292,32 @@ void uhd_device::set_ref_clk(bool ext_clk)
double uhd_device::set_rates(double rate)
{
double actual_rate;
double actual_rt, actual_clk_rt;
// Set master clock rate
usrp_dev->set_master_clock_rate(master_clk_rt);
actual_clk_rt = usrp_dev->get_master_clock_rate();
if (actual_clk_rt != master_clk_rt) {
LOG(ERROR) << "Failed to set master clock rate";
return -1.0;
}
// Set sample rates
usrp_dev->set_tx_rate(rate);
usrp_dev->set_rx_rate(rate);
actual_rate = usrp_dev->get_tx_rate();
actual_rt = usrp_dev->get_tx_rate();
if (actual_rate != rate) {
if (actual_rt != rate) {
LOG(ERROR) << "Actual sample rate differs from desired rate";
return -1.0;
}
if (usrp_dev->get_rx_rate() != actual_rate) {
if (usrp_dev->get_rx_rate() != actual_rt) {
LOG(ERROR) << "Transmit and receive sample rates do not match";
return -1.0;
}
return actual_rate;
return actual_rt;
}
double uhd_device::setTxGain(double db)
@ -345,9 +355,6 @@ bool uhd_device::open()
return false;
}
// Set master clock rate
usrp_dev->set_master_clock_rate(master_clk_rt);
// Number of samples per over-the-wire packet
tx_spp = usrp_dev->get_device()->get_max_send_samps_per_packet();
rx_spp = usrp_dev->get_device()->get_max_recv_samps_per_packet();