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170 Commits

Author SHA1 Message Date
Martin Schramm 86a2c70a67 gtm900-bo: add header for power source selection (DC in / USB) 2020-05-22 23:33:49 +02:00
Martin Schramm 7f920a3085 gtm900-bo: ease some part's distances, increase OSHW logo 2020-05-22 21:34:15 +02:00
Martin Schramm db7c7a1194 gtm900-bo: re-introduce serial 0R on UART_RI 
...not, that it was needed, but just in case...
 2020-05-19 14:31:44 +02:00
Martin Schramm b9df775569 gtm900-bo: ERC + DRC done + corrections 2020-05-18 20:57:23 +02:00
Martin Schramm 6e2422c979 gtm900-bo: routing done, no airwires left, mirrored FPC removed 2020-05-18 20:39:01 +02:00
Martin Schramm aba83c5ecc gtm900-bo: hopefully incorporating all we discussed last weeks 
see OS#4030
 2020-05-17 14:03:37 +02:00
Martin Schramm 9f860f796e gtm900: added CP2105 and 3.5mm TRRS audio jack, remv'd aux conn 
adds to OS#4030
 2020-04-27 19:16:49 +02:00
Martin Schramm 0730af45e2 initial commit for a GTM900 breakout PCBA 
An additional mirrored FPC header will still be maintained
as long as this PCBA is discussed/revised.

This is going to be a OSHW CC-BY-SA.
 2020-04-20 23:39:46 +02:00
Harald Welte 617288296f clock-generator: Fix VDD connection of TC2050 SWD connector 
Closes: OS#4431
 2020-03-01 19:42:20 +01:00
Martin Schramm 7d09b416a2 clock-gen: increase I2C PU's to 4k7 
Although the SI5153 datasheet mentions the I2C PUs as ">=1k", this
appears to be unusually strong for no obvious reason, and we don't
have high data rates there... changed them to more reasonable 4k7.
 2020-02-07 20:00:44 +01:00
Martin Schramm 44e584624a clock-gen: update ATSAMD21's BOM attributes (solves OS#4387) 2020-01-31 18:19:20 +01:00
Martin Schramm 895c6d3dde clock-generator: exchange mini-USB foorprint (solves OS#4386) 
... and purge unneeded layers
 2020-01-30 18:03:26 +01:00
Martin Schramm 76c5448d75 clock-generator: exchange silk screen position of R14 vs. C19 
fortunately, they have a different size (0603 vs 0402), so while placing
this be#came obvious.
 2020-01-28 18:22:25 +01:00
Martin Schramm f85755ceda Merge branch 'master' of ssh://git.osmocom.org/osmo-small-hardware 2020-01-09 16:55:39 +01:00
Martin Schramm 14c2642a1d ngff: add product links to all one- and two-row 2,54mm pin header 2020-01-09 16:54:12 +01:00
Harald Welte f2e12808de add PDF renderings of ngff-breakout 2019-12-14 14:41:24 +01:00
Martin Schramm 1fed947ff7 ngff-breakout: update BOM 2019-11-22 20:45:09 +01:00
Harald Welte beffe5c0c2 ngff-breakout: Add M.2 nut/stand-off data sheet 2019-11-15 11:03:20 +01:00
Harald Welte 9706e99ba0 clock-generator: Replace SAM D11 data sheet with D21 data sheet 2019-11-05 13:51:20 +01:00
Martin Schramm 4fdc3b8522 ngff: revert increased clearance for supply net class 
...and instead change class membership of an affected wire.
 2019-10-18 21:08:28 +02:00
Martin Schramm ef87dab295 ngff: PCB cosmetics and subsequent DRC; rearrange SMA + MHF4 conn 2019-10-18 20:54:07 +02:00
Martin Schramm bc7e4cec92 ngff: swap Rx and Tx (solves OS#4230) 2019-10-18 17:27:11 +02:00
Martin Schramm 1de1cd0da1 ngff: connect pin 4 @X2 to GND (solves OS#4216) 2019-10-17 18:33:06 +02:00
Martin Schramm 63389c1b99 ngff: add eBOM 2019-09-25 20:49:12 +02:00
Martin Schramm 593ab6798b ngff: add / refresh most ext'd attribs for eBOM 2019-09-25 20:46:22 +02:00
Martin Schramm 26425b8623 ngff: silk screen cosmetics 2019-09-24 18:43:49 +02:00
Martin Schramm 94d293bdb0 ngff: re-introduce and re-position OSHW logo and bott silk screen 2019-09-24 18:25:08 +02:00
Martin Schramm a2e0970835 ngff: repair one critical via for ERC passing 2019-09-24 16:51:50 +02:00
Martin Schramm 861afe9e60 ngff: 2/2 make room for 2x5 header and route SIM2 signals there 
...and run ERC/DRC

adresses OS#4211
 2019-09-24 16:42:42 +02:00
Martin Schramm b9a0f747cb ngff: make room for 2x5 header and route SIM2 signals there 
adresses OS#4211
 2019-09-20 22:04:52 +02:00
Martin Schramm dd62b6547e ngff: remove bogus packages names with '@1' by re-importing std lib 2019-09-19 19:20:35 +02:00
Martin Schramm 8dcf136de6 ngff: move PCIe header 3mm inwards (solves OS#4210) 
... and started OS#4211.
 2019-09-19 19:15:48 +02:00
Martin Schramm 3e103422c2 ngff: set R9 to 100k (solves OS#4209) 2019-09-17 17:44:02 +02:00
Martin Schramm aaaf260b1f ngff: route all four ANTCTLn signals on bottom layer (fixes OS#4187) 2019-09-17 15:01:11 +02:00
Martin Schramm deccb4f960 ngff: repair M.2/NGFF footprint (see SYS#4661) 2019-09-17 13:35:36 +02:00
Harald Welte 102d73a760 Merge branch 'laforge/ngff-breakout' 2019-08-29 15:35:06 +02:00
Martin Schramm 300180dd97 ngff: finishing work 2019-08-29 15:33:28 +02:00
Martin Schramm d4ed3daf17 ngff-breakout: almost ready 
missing: more vias, more ext. attributes (for BOM)
 2019-08-29 15:33:21 +02:00
Martin Schramm 4be5f434e9 ngff-breakout: intermediate state 2019-08-29 15:33:17 +02:00
Martin Schramm 6830553c74 ngff-breakout: make 4layer PCB 2019-08-29 15:33:13 +02:00
Harald Welte 3ad642f19b ngff-breakout: Update con-ngff.lbr to get PCIe lanes 2019-08-29 15:33:09 +02:00
Harald Welte 7501689b2a ngff-breakout: Partial migration over to NGFF 
The mPCIe slot has been removed and the NGFF slot added. Basic
connections have been made in the schematics, but it's far from being
complete.  No effort on the PCB routing has been made so far.
 2019-08-29 15:33:04 +02:00
Harald Welte 63e90df39f ngff-breakout: Rename "mPCIe" -> "NGFF WWAN" and re-start version at v1 2019-08-29 15:33:00 +02:00
Harald Welte b824f0509c Add ngff-breakout as copy of mpcie-breakout 
... ngff specific modifications will follow
 2019-08-29 15:32:55 +02:00
Harald Welte 31ae1be9c6 sc14cvm-evb: Add attributes 2019-08-16 17:58:49 +02:00
Harald Welte c5c776b7ce add SC14CVMDECT module breakout board 2019-08-07 20:22:28 +02:00
Harald Welte 8908096c70 v3 final with gerber output 2019-06-22 11:59:27 +02:00
Harald Welte d9df109853 final v3 as it goes in pcb production 
* smash components and move labels to where they can be read
* add indication of + / GND to X3/X4
* re-route some traces to ensure sufficient distance between them
* make all traces 0.508 mm wide, even signal traces.
 2019-06-22 11:59:27 +02:00
Harald Welte 69f4bae1a9 update OHM4 OCXO, preliminary v3 
* use new LDO (single LDO with range up to 12V input)
 * add U.FL clock input (instead of OCXO as source)
 * no parallel, but series resistors to trimmer
 * allow output of PLL to be fed through resistive divider
 2019-06-22 11:59:27 +02:00
Harald Welte ad725445da remove .pro file, not needed 2019-06-22 11:59:27 +02:00