339 lines
7.3 KiB
C
339 lines
7.3 KiB
C
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/*
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* Part of librfm3 (a utility library built on librfn and libopencm3)
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*
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* Copyright (C) 2014 Daniel Thompson <daniel@redfelineninja.org.uk>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <librfm3/i2c_ctx.h>
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#include <errno.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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#include <libopencm3/stm32/i2c.h>
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#include <libopencm3/stm32/rcc.h>
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#include <librfn/regdump.h>
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#include <librfn/time.h>
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#include <librfn/util.h>
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#define D(x) { #x, x }
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static const regdump_desc_t i2c_sr1_desc[] = { { "I2C_SR1", 0 },
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D(I2C_SR1_SMBALERT),
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D(I2C_SR1_TIMEOUT),
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D(I2C_SR1_PECERR),
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D(I2C_SR1_OVR),
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D(I2C_SR1_AF),
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D(I2C_SR1_ARLO),
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D(I2C_SR1_BERR),
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D(I2C_SR1_TxE),
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D(I2C_SR1_RxNE),
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D(I2C_SR1_STOPF),
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D(I2C_SR1_ADD10),
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D(I2C_SR1_BTF),
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D(I2C_SR1_ADDR),
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D(I2C_SR1_SB),
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{ NULL, 0 } };
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#undef D
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static bool i2c_ctx_is_timed_out(i2c_ctx_t *c)
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{
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if (cyclecmp32(time_now(), c->timeout) > 0) {
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if (c->verbose) {
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printf("I2C TRANSACTION TIMED OUT\n");
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regdump(I2C_SR1(c->i2c), i2c_sr1_desc);
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}
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return true;
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}
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return false;
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}
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void i2c_ctx_init(i2c_ctx_t *c, uint32_t pi2c)
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{
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memset(c, 0, sizeof(*c));
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c->i2c = pi2c;
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c->timeout = time_now() + 100000;
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}
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void i2c_ctx_reset(i2c_ctx_t *c)
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{
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/* TODO: Latest opencm3 has this code built in */
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switch (c->i2c) {
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case I2C1:
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rcc_periph_reset_pulse(RST_I2C1);
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rcc_periph_reset_pulse(RST_I2C1);
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break;
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case I2C2:
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rcc_periph_reset_pulse(RST_I2C2);
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rcc_periph_reset_pulse(RST_I2C2);
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break;
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#ifdef STM32F4
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case I2C3:
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rcc_periph_reset_pulse(RST_I2C3);
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rcc_periph_reset_pulse(RST_I2C3);
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break;
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#endif
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}
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/* freq's numeric value ends up in MHz (i.e. in this case, 30) */
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#ifdef STM32F4
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uint16_t freq = I2C_CR2_FREQ_30MHZ;
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#else
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uint16_t freq = 36;
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#endif
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/* CCR is the number of APB bus cycles in *half* an I2C bus
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* cycle. For Sm (100Khz) this ends up as:
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* freq * 1MHz / 2 * 100KHz
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* freq * 1000000 / 200000
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* freq * 5
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*
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* Similar trise is the number of APB bus cycles in the rise
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* time (plus 1). For Sm (1us) this ends up as:
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* freq * 1Mhz / (1/1us) + 1
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* freq * 1MHz / 1MHz + 1
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* freq + 1
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*/
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/* peripheral configuration */
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i2c_peripheral_disable(c->i2c);
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i2c_set_clock_frequency(c->i2c, freq);
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i2c_set_ccr(c->i2c, freq * 5);
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i2c_set_trise(c->i2c, freq + 1);
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i2c_set_own_7bit_slave_address(c->i2c, 0x32);
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i2c_peripheral_enable(c->i2c);
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}
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pt_state_t i2c_ctx_start(i2c_ctx_t *c)
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{
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PT_BEGIN(&c->leaf);
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i2c_send_start(c->i2c);
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while (!i2c_ctx_is_timed_out(c) &&
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!((I2C_SR1(c->i2c) & I2C_SR1_SB) &
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(I2C_SR2(c->i2c) & (I2C_SR2_MSL | I2C_SR2_BUSY))))
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PT_YIELD();
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if (!I2C_SR1(c->i2c) & I2C_SR1_SB) {
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i2c_ctx_reset(c);
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c->err = EIO;
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}
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PT_END();
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}
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pt_state_t i2c_ctx_sendaddr(i2c_ctx_t *c, uint16_t addr,
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uint8_t bytes_to_read)
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{
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PT_BEGIN(&c->leaf);
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c->bytes_remaining = bytes_to_read;
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i2c_send_7bit_address(c->i2c, addr, !!bytes_to_read);
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while (!i2c_ctx_is_timed_out(c) && // bad
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!(I2C_SR1(c->i2c) & I2C_SR1_AF) && // bad
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!(I2C_SR1(c->i2c) & I2C_SR1_ADDR)) // good
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PT_YIELD();
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if (!(I2C_SR1(c->i2c) & I2C_SR1_ADDR)) {
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i2c_ctx_reset(c);
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c->err = EIO;
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}
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/* If we are only reading one byte we must get ready to NACK the
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* final byte.
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*/
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if (c->bytes_remaining == 1)
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I2C_CR1(c->i2c) &= ~I2C_CR1_ACK;
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else if (c->bytes_remaining >= 2)
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I2C_CR1(c->i2c) |= I2C_CR1_ACK;
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/* Read sequence has side effect or clearing I2C_SR1_ADDR */
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uint32_t reg32 __attribute__((unused));
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reg32 = I2C_SR2(c->i2c);
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if (c->bytes_remaining == 1)
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i2c_send_stop(c->i2c);
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PT_END();
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}
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pt_state_t i2c_ctx_senddata(i2c_ctx_t *c, uint8_t data)
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{
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PT_BEGIN(&c->leaf);
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i2c_send_data(c->i2c, data);
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while (!i2c_ctx_is_timed_out(c) && !(I2C_SR1(c->i2c) & I2C_SR1_BTF))
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PT_YIELD();
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if (!(I2C_SR1(c->i2c) & I2C_SR1_BTF)) {
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i2c_ctx_reset(c);
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c->err = EIO;
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}
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PT_END();
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}
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pt_state_t i2c_ctx_getdata(i2c_ctx_t *c, uint8_t *data)
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{
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PT_BEGIN(&c->leaf);
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while (!i2c_ctx_is_timed_out(c) && !(I2C_SR1(c->i2c) & I2C_SR1_RxNE))
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PT_YIELD();
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if (!(I2C_SR1(c->i2c) & I2C_SR1_RxNE)) {
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i2c_ctx_reset(c);
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c->err = EIO;
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PT_EXIT();
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}
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/* Need to NACK the final byte and STOP the transaction */
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if (--c->bytes_remaining == 1) {
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I2C_CR1(c->i2c) &= ~I2C_CR1_ACK;
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i2c_send_stop(c->i2c);
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}
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*data = i2c_get_data(c->i2c);
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PT_END();
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}
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pt_state_t i2c_ctx_stop(i2c_ctx_t *c)
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{
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PT_BEGIN(&c->leaf);
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while (!i2c_ctx_is_timed_out(c) &&
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!(I2C_SR1(c->i2c) & (I2C_SR1_BTF | I2C_SR1_TxE)))
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PT_YIELD();
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if (!(I2C_SR1(c->i2c) & (I2C_SR1_BTF | I2C_SR1_TxE))) {
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i2c_ctx_reset(c);
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c->err = EIO;
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PT_EXIT();
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}
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i2c_send_stop(c->i2c);
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/* TODO: is it safe to just drop out of this */
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PT_END();
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}
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pt_state_t i2c_ctx_detect(i2c_ctx_t *c, i2c_device_map_t *map)
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{
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PT_BEGIN(&c->pt);
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memset(map, 0, sizeof(*map));
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for (c->i = 0; c->i < 0x80; c->i++) {
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c->timeout = time_now() + 10000;
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c->err = 0;
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PT_SPAWN(&c->leaf, i2c_ctx_start(c));
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if (c->err)
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continue;
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PT_SPAWN(&c->leaf, i2c_ctx_sendaddr(c, c->i, I2C_WRITE));
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if (c->err)
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continue;
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PT_SPAWN(&c->leaf, i2c_ctx_stop(c));
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if (c->err)
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continue;
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map->devices[c->i / 16] |= 1 << (c->i % 16);
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}
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PT_END();
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}
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pt_state_t i2c_ctx_setreg(i2c_ctx_t *c, uint16_t addr, uint16_t reg,
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uint8_t val)
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{
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PT_BEGIN(&c->pt);
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PT_SPAWN(&c->leaf, i2c_ctx_start(c));
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PT_EXIT_ON(c->err);
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PT_SPAWN(&c->leaf, i2c_ctx_sendaddr(c, addr, I2C_WRITE));
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PT_EXIT_ON(c->err);
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PT_SPAWN(&c->leaf, i2c_ctx_senddata(c, reg));
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PT_EXIT_ON(c->err);
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PT_SPAWN(&c->leaf, i2c_ctx_senddata(c, val));
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PT_EXIT_ON(c->err);
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PT_SPAWN(&c->leaf, i2c_ctx_stop(c));
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PT_END();
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}
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pt_state_t i2c_ctx_getreg(i2c_ctx_t *c, uint16_t addr, uint16_t reg,
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uint8_t *val)
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{
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PT_BEGIN(&c->pt);
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PT_SPAWN(&c->leaf, i2c_ctx_start(c));
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PT_EXIT_ON(c->err);
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PT_SPAWN(&c->leaf, i2c_ctx_sendaddr(c, addr, I2C_WRITE));
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PT_EXIT_ON(c->err);
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PT_SPAWN(&c->leaf, i2c_ctx_senddata(c, reg));
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PT_EXIT_ON(c->err);
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PT_SPAWN(&c->leaf, i2c_ctx_start(c));
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PT_EXIT_ON(c->err);
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PT_SPAWN(&c->leaf, i2c_ctx_sendaddr(c, addr, I2C_READ));
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PT_EXIT_ON(c->err);
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PT_SPAWN(&c->leaf, i2c_ctx_getdata(c, val));
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/* For reads STOP is generated automatically by sendaddr and/or
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* getdata
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*/
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PT_END();
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}
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pt_state_t i2c_ctx_write(i2c_ctx_t *c, uint16_t addr, uint8_t *data,
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uint8_t len)
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{
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PT_BEGIN(&c->pt);
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PT_SPAWN(&c->leaf, i2c_ctx_start(c));
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PT_EXIT_ON(c->err);
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PT_SPAWN(&c->leaf, i2c_ctx_sendaddr(c, addr, I2C_WRITE));
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PT_EXIT_ON(c->err);
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for (c->i = 0; c->i < len; c->i++) {
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PT_SPAWN(&c->leaf, i2c_ctx_senddata(c, data[c->i]));
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PT_EXIT_ON(c->err);
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}
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PT_SPAWN(&c->leaf, i2c_ctx_stop(c));
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PT_END();
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}
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