libopencm3/scripts/data/lpc43xx/gpdma.csv

1	GPDMA_INTSTAT	0	8	INTSTAT	Status of DMA channel interrupts after masking	0x00	r
2	GPDMA_INTTCSTAT	0	8	INTTCSTAT	Terminal count interrupt request status for DMA channels	0x00	r
3	GPDMA_INTTCCLEAR	0	8	INTTCCLEAR	Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels	0x00	w
4	GPDMA_INTERRSTAT	0	8	INTERRSTAT	Interrupt error status for DMA channels	0x00	r
5	GPDMA_INTERRCLR	0	8	INTERRCLR	Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels	0x00	w
6	GPDMA_RAWINTTCSTAT	0	8	RAWINTTCSTAT	Status of the terminal count interrupt for DMA channels prior to masking	0x00	r
7	GPDMA_RAWINTERRSTAT	0	8	RAWINTERRSTAT	Status of the error interrupt for DMA channels prior to masking	0x00	r
8	GPDMA_ENBLDCHNS	0	8	ENABLEDCHANNELS	Enable status for DMA channels	0x00	r
9	GPDMA_SOFTBREQ	0	16	SOFTBREQ	Software burst request flags for each of 16 possible sources	0x00	rw
10	GPDMA_SOFTSREQ	0	16	SOFTSREQ	Software single transfer request flags for each of 16 possible sources	0x00	rw
11	GPDMA_SOFTLBREQ	0	16	SOFTLBREQ	Software last burst request flags for each of 16 possible sources	0x00	rw
12	GPDMA_SOFTLSREQ	0	16	SOFTLSREQ	Software last single transfer request flags for each of 16 possible sources	0x00	rw
13	GPDMA_CONFIG	0	1	E	DMA Controller enable	0	rw
14	GPDMA_CONFIG	1	1	M0	AHB Master 0 endianness configuration	0	rw
15	GPDMA_CONFIG	2	1	M1	AHB Master 1 endianness configuration	0	rw
16	GPDMA_SYNC	0	16	DMACSYNC	Controls the synchronization logic for DMA request signals	0x00	rw
17	GPDMA_C0SRCADDR	0	32	SRCADDR	DMA source address	0x00000000	rw
18	GPDMA_C1SRCADDR	0	32	SRCADDR	DMA source address	0x00000000	rw
19	GPDMA_C2SRCADDR	0	32	SRCADDR	DMA source address	0x00000000	rw
20	GPDMA_C3SRCADDR	0	32	SRCADDR	DMA source address	0x00000000	rw
21	GPDMA_C4SRCADDR	0	32	SRCADDR	DMA source address	0x00000000	rw
22	GPDMA_C5SRCADDR	0	32	SRCADDR	DMA source address	0x00000000	rw
23	GPDMA_C6SRCADDR	0	32	SRCADDR	DMA source address	0x00000000	rw
24	GPDMA_C7SRCADDR	0	32	SRCADDR	DMA source address	0x00000000	rw
25	GPDMA_C0DESTADDR	0	32	DESTADDR	DMA source address	0x00000000	rw
26	GPDMA_C1DESTADDR	0	32	DESTADDR	DMA source address	0x00000000	rw
27	GPDMA_C2DESTADDR	0	32	DESTADDR	DMA source address	0x00000000	rw
28	GPDMA_C3DESTADDR	0	32	DESTADDR	DMA source address	0x00000000	rw
29	GPDMA_C4DESTADDR	0	32	DESTADDR	DMA source address	0x00000000	rw
30	GPDMA_C5DESTADDR	0	32	DESTADDR	DMA source address	0x00000000	rw
31	GPDMA_C6DESTADDR	0	32	DESTADDR	DMA source address	0x00000000	rw
32	GPDMA_C7DESTADDR	0	32	DESTADDR	DMA source address	0x00000000	rw
33	GPDMA_C0LLI	0	1	LM	AHB master select for loading the next LLI	0	rw
34	GPDMA_C0LLI	2	30	LLI	Linked list item	0x00000000	rw
35	GPDMA_C1LLI	0	1	LM	AHB master select for loading the next LLI	0	rw
36	GPDMA_C1LLI	2	30	LLI	Linked list item	0x00000000	rw
37	GPDMA_C2LLI	0	1	LM	AHB master select for loading the next LLI	0	rw
38	GPDMA_C2LLI	2	30	LLI	Linked list item	0x00000000	rw
39	GPDMA_C3LLI	0	1	LM	AHB master select for loading the next LLI	0	rw
40	GPDMA_C3LLI	2	30	LLI	Linked list item	0x00000000	rw
41	GPDMA_C4LLI	0	1	LM	AHB master select for loading the next LLI	0	rw
42	GPDMA_C4LLI	2	30	LLI	Linked list item	0x00000000	rw
43	GPDMA_C5LLI	0	1	LM	AHB master select for loading the next LLI	0	rw
44	GPDMA_C5LLI	2	30	LLI	Linked list item	0x00000000	rw
45	GPDMA_C6LLI	0	1	LM	AHB master select for loading the next LLI	0	rw
46	GPDMA_C6LLI	2	30	LLI	Linked list item	0x00000000	rw
47	GPDMA_C7LLI	0	1	LM	AHB master select for loading the next LLI	0	rw
48	GPDMA_C7LLI	2	30	LLI	Linked list item	0x00000000	rw
49	GPDMA_C0CONTROL	0	12	TRANSFERSIZE	Transfer size in number of transfers	0x00	rw
50	GPDMA_C0CONTROL	12	3	SBSIZE	Source burst size	0x0	rw
51	GPDMA_C0CONTROL	15	3	DBSIZE	Destination burst size	0x0	rw
52	GPDMA_C0CONTROL	18	3	SWIDTH	Source transfer width	0x0	rw
53	GPDMA_C0CONTROL	21	3	DWIDTH	Destination transfer width	0x0	rw
54	GPDMA_C0CONTROL	24	1	S	Source AHB master select	0	rw
55	GPDMA_C0CONTROL	25	1	D	Destination AHB master select	0	rw
56	GPDMA_C0CONTROL	26	1	SI	Source increment	0	rw
57	GPDMA_C0CONTROL	27	1	DI	Destination increment	0	rw
58	GPDMA_C0CONTROL	28	1	PROT1	This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode	0	rw
59	GPDMA_C0CONTROL	29	1	PROT2	This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable	0	rw
60	GPDMA_C0CONTROL	30	1	PROT3	This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable	0	rw
61	GPDMA_C0CONTROL	31	1	I	Terminal count interrupt enable bit	0	rw
62	GPDMA_C1CONTROL	0	12	TRANSFERSIZE	Transfer size in number of transfers	0x00	rw
63	GPDMA_C1CONTROL	12	3	SBSIZE	Source burst size	0x0	rw
64	GPDMA_C1CONTROL	15	3	DBSIZE	Destination burst size	0x0	rw
65	GPDMA_C1CONTROL	18	3	SWIDTH	Source transfer width	0x0	rw
66	GPDMA_C1CONTROL	21	3	DWIDTH	Destination transfer width	0x0	rw
67	GPDMA_C1CONTROL	24	1	S	Source AHB master select	0	rw
68	GPDMA_C1CONTROL	25	1	D	Destination AHB master select	0	rw
69	GPDMA_C1CONTROL	26	1	SI	Source increment	0	rw
70	GPDMA_C1CONTROL	27	1	DI	Destination increment	0	rw
71	GPDMA_C1CONTROL	28	1	PROT1	This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode	0	rw
72	GPDMA_C1CONTROL	29	1	PROT2	This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable	0	rw
73	GPDMA_C1CONTROL	30	1	PROT3	This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable	0	rw
74	GPDMA_C1CONTROL	31	1	I	Terminal count interrupt enable bit	0	rw
75	GPDMA_C2CONTROL	0	12	TRANSFERSIZE	Transfer size in number of transfers	0x00	rw
76	GPDMA_C2CONTROL	12	3	SBSIZE	Source burst size	0x0	rw
77	GPDMA_C2CONTROL	15	3	DBSIZE	Destination burst size	0x0	rw
78	GPDMA_C2CONTROL	18	3	SWIDTH	Source transfer width	0x0	rw
79	GPDMA_C2CONTROL	21	3	DWIDTH	Destination transfer width	0x0	rw
80	GPDMA_C2CONTROL	24	1	S	Source AHB master select	0	rw
81	GPDMA_C2CONTROL	25	1	D	Destination AHB master select	0	rw
82	GPDMA_C2CONTROL	26	1	SI	Source increment	0	rw
83	GPDMA_C2CONTROL	27	1	DI	Destination increment	0	rw
84	GPDMA_C2CONTROL	28	1	PROT1	This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode	0	rw
85	GPDMA_C2CONTROL	29	1	PROT2	This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable	0	rw
86	GPDMA_C2CONTROL	30	1	PROT3	This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable	0	rw
87	GPDMA_C2CONTROL	31	1	I	Terminal count interrupt enable bit	0	rw
88	GPDMA_C3CONTROL	0	12	TRANSFERSIZE	Transfer size in number of transfers	0x00	rw
89	GPDMA_C3CONTROL	12	3	SBSIZE	Source burst size	0x0	rw
90	GPDMA_C3CONTROL	15	3	DBSIZE	Destination burst size	0x0	rw
91	GPDMA_C3CONTROL	18	3	SWIDTH	Source transfer width	0x0	rw
92	GPDMA_C3CONTROL	21	3	DWIDTH	Destination transfer width	0x0	rw
93	GPDMA_C3CONTROL	24	1	S	Source AHB master select	0	rw
94	GPDMA_C3CONTROL	25	1	D	Destination AHB master select	0	rw
95	GPDMA_C3CONTROL	26	1	SI	Source increment	0	rw
96	GPDMA_C3CONTROL	27	1	DI	Destination increment	0	rw
97	GPDMA_C3CONTROL	28	1	PROT1	This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode	0	rw
98	GPDMA_C3CONTROL	29	1	PROT2	This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable	0	rw
99	GPDMA_C3CONTROL	30	1	PROT3	This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable	0	rw
100	GPDMA_C3CONTROL	31	1	I	Terminal count interrupt enable bit	0	rw
101	GPDMA_C4CONTROL	0	12	TRANSFERSIZE	Transfer size in number of transfers	0x00	rw
102	GPDMA_C4CONTROL	12	3	SBSIZE	Source burst size	0x0	rw
103	GPDMA_C4CONTROL	15	3	DBSIZE	Destination burst size	0x0	rw
104	GPDMA_C4CONTROL	18	3	SWIDTH	Source transfer width	0x0	rw
105	GPDMA_C4CONTROL	21	3	DWIDTH	Destination transfer width	0x0	rw
106	GPDMA_C4CONTROL	24	1	S	Source AHB master select	0	rw
107	GPDMA_C4CONTROL	25	1	D	Destination AHB master select	0	rw
108	GPDMA_C4CONTROL	26	1	SI	Source increment	0	rw
109	GPDMA_C4CONTROL	27	1	DI	Destination increment	0	rw
110	GPDMA_C4CONTROL	28	1	PROT1	This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode	0	rw
111	GPDMA_C4CONTROL	29	1	PROT2	This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable	0	rw
112	GPDMA_C4CONTROL	30	1	PROT3	This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable	0	rw
113	GPDMA_C4CONTROL	31	1	I	Terminal count interrupt enable bit	0	rw
114	GPDMA_C5CONTROL	0	12	TRANSFERSIZE	Transfer size in number of transfers	0x00	rw
115	GPDMA_C5CONTROL	12	3	SBSIZE	Source burst size	0x0	rw
116	GPDMA_C5CONTROL	15	3	DBSIZE	Destination burst size	0x0	rw
117	GPDMA_C5CONTROL	18	3	SWIDTH	Source transfer width	0x0	rw
118	GPDMA_C5CONTROL	21	3	DWIDTH	Destination transfer width	0x0	rw
119	GPDMA_C5CONTROL	24	1	S	Source AHB master select	0	rw
120	GPDMA_C5CONTROL	25	1	D	Destination AHB master select	0	rw
121	GPDMA_C5CONTROL	26	1	SI	Source increment	0	rw
122	GPDMA_C5CONTROL	27	1	DI	Destination increment	0	rw
123	GPDMA_C5CONTROL	28	1	PROT1	This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode	0	rw
124	GPDMA_C5CONTROL	29	1	PROT2	This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable	0	rw
125	GPDMA_C5CONTROL	30	1	PROT3	This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable	0	rw
126	GPDMA_C5CONTROL	31	1	I	Terminal count interrupt enable bit	0	rw
127	GPDMA_C6CONTROL	0	12	TRANSFERSIZE	Transfer size in number of transfers	0x00	rw
128	GPDMA_C6CONTROL	12	3	SBSIZE	Source burst size	0x0	rw
129	GPDMA_C6CONTROL	15	3	DBSIZE	Destination burst size	0x0	rw
130	GPDMA_C6CONTROL	18	3	SWIDTH	Source transfer width	0x0	rw
131	GPDMA_C6CONTROL	21	3	DWIDTH	Destination transfer width	0x0	rw
132	GPDMA_C6CONTROL	24	1	S	Source AHB master select	0	rw
133	GPDMA_C6CONTROL	25	1	D	Destination AHB master select	0	rw
134	GPDMA_C6CONTROL	26	1	SI	Source increment	0	rw
135	GPDMA_C6CONTROL	27	1	DI	Destination increment	0	rw
136	GPDMA_C6CONTROL	28	1	PROT1	This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode	0	rw
137	GPDMA_C6CONTROL	29	1	PROT2	This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable	0	rw
138	GPDMA_C6CONTROL	30	1	PROT3	This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable	0	rw
139	GPDMA_C6CONTROL	31	1	I	Terminal count interrupt enable bit	0	rw
140	GPDMA_C7CONTROL	0	12	TRANSFERSIZE	Transfer size in number of transfers	0x00	rw
141	GPDMA_C7CONTROL	12	3	SBSIZE	Source burst size	0x0	rw
142	GPDMA_C7CONTROL	15	3	DBSIZE	Destination burst size	0x0	rw
143	GPDMA_C7CONTROL	18	3	SWIDTH	Source transfer width	0x0	rw
144	GPDMA_C7CONTROL	21	3	DWIDTH	Destination transfer width	0x0	rw
145	GPDMA_C7CONTROL	24	1	S	Source AHB master select	0	rw
146	GPDMA_C7CONTROL	25	1	D	Destination AHB master select	0	rw
147	GPDMA_C7CONTROL	26	1	SI	Source increment	0	rw
148	GPDMA_C7CONTROL	27	1	DI	Destination increment	0	rw
149	GPDMA_C7CONTROL	28	1	PROT1	This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode	0	rw
150	GPDMA_C7CONTROL	29	1	PROT2	This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable	0	rw
151	GPDMA_C7CONTROL	30	1	PROT3	This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable	0	rw
152	GPDMA_C7CONTROL	31	1	I	Terminal count interrupt enable bit	0	rw
153	GPDMA_C0CONFIG	0	1	E	Channel enable	0	rw
154	GPDMA_C0CONFIG	1	5	SRCPERIPHERAL	Source peripheral		rw
155	GPDMA_C0CONFIG	6	5	DESTPERIPHERAL	Destination peripheral		rw
156	GPDMA_C0CONFIG	11	3	FLOWCNTRL	Flow control and transfer type		rw
157	GPDMA_C0CONFIG	14	1	IE	Interrupt error mask		rw
158	GPDMA_C0CONFIG	15	1	ITC	Terminal count interrupt mask		rw
159	GPDMA_C0CONFIG	16	1	L	Lock		rw
160	GPDMA_C0CONFIG	17	1	A	Active		r
161	GPDMA_C0CONFIG	18	1	H	Halt		rw
162	GPDMA_C1CONFIG	0	1	E	Channel enable	0	rw
163	GPDMA_C1CONFIG	1	5	SRCPERIPHERAL	Source peripheral		rw
164	GPDMA_C1CONFIG	6	5	DESTPERIPHERAL	Destination peripheral		rw
165	GPDMA_C1CONFIG	11	3	FLOWCNTRL	Flow control and transfer type		rw
166	GPDMA_C1CONFIG	14	1	IE	Interrupt error mask		rw
167	GPDMA_C1CONFIG	15	1	ITC	Terminal count interrupt mask		rw
168	GPDMA_C1CONFIG	16	1	L	Lock		rw
169	GPDMA_C1CONFIG	17	1	A	Active		r
170	GPDMA_C1CONFIG	18	1	H	Halt		rw
171	GPDMA_C2CONFIG	0	1	E	Channel enable	0	rw
172	GPDMA_C2CONFIG	1	5	SRCPERIPHERAL	Source peripheral		rw
173	GPDMA_C2CONFIG	6	5	DESTPERIPHERAL	Destination peripheral		rw
174	GPDMA_C2CONFIG	11	3	FLOWCNTRL	Flow control and transfer type		rw
175	GPDMA_C2CONFIG	14	1	IE	Interrupt error mask		rw
176	GPDMA_C2CONFIG	15	1	ITC	Terminal count interrupt mask		rw
177	GPDMA_C2CONFIG	16	1	L	Lock		rw
178	GPDMA_C2CONFIG	17	1	A	Active		r
179	GPDMA_C2CONFIG	18	1	H	Halt		rw
180	GPDMA_C3CONFIG	0	1	E	Channel enable	0	rw
181	GPDMA_C3CONFIG	1	5	SRCPERIPHERAL	Source peripheral		rw
182	GPDMA_C3CONFIG	6	5	DESTPERIPHERAL	Destination peripheral		rw
183	GPDMA_C3CONFIG	11	3	FLOWCNTRL	Flow control and transfer type		rw
184	GPDMA_C3CONFIG	14	1	IE	Interrupt error mask		rw
185	GPDMA_C3CONFIG	15	1	ITC	Terminal count interrupt mask		rw
186	GPDMA_C3CONFIG	16	1	L	Lock		rw
187	GPDMA_C3CONFIG	17	1	A	Active		r
188	GPDMA_C3CONFIG	18	1	H	Halt		rw
189	GPDMA_C4CONFIG	0	1	E	Channel enable	0	rw
190	GPDMA_C4CONFIG	1	5	SRCPERIPHERAL	Source peripheral		rw
191	GPDMA_C4CONFIG	6	5	DESTPERIPHERAL	Destination peripheral		rw
192	GPDMA_C4CONFIG	11	3	FLOWCNTRL	Flow control and transfer type		rw
193	GPDMA_C4CONFIG	14	1	IE	Interrupt error mask		rw
194	GPDMA_C4CONFIG	15	1	ITC	Terminal count interrupt mask		rw
195	GPDMA_C4CONFIG	16	1	L	Lock		rw
196	GPDMA_C4CONFIG	17	1	A	Active		r
197	GPDMA_C4CONFIG	18	1	H	Halt		rw
198	GPDMA_C5CONFIG	0	1	E	Channel enable	0	rw
199	GPDMA_C5CONFIG	1	5	SRCPERIPHERAL	Source peripheral		rw
200	GPDMA_C5CONFIG	6	5	DESTPERIPHERAL	Destination peripheral		rw
201	GPDMA_C5CONFIG	11	3	FLOWCNTRL	Flow control and transfer type		rw
202	GPDMA_C5CONFIG	14	1	IE	Interrupt error mask		rw
203	GPDMA_C5CONFIG	15	1	ITC	Terminal count interrupt mask		rw
204	GPDMA_C5CONFIG	16	1	L	Lock		rw
205	GPDMA_C5CONFIG	17	1	A	Active		r
206	GPDMA_C5CONFIG	18	1	H	Halt		rw
207	GPDMA_C6CONFIG	0	1	E	Channel enable	0	rw
208	GPDMA_C6CONFIG	1	5	SRCPERIPHERAL	Source peripheral		rw
209	GPDMA_C6CONFIG	6	5	DESTPERIPHERAL	Destination peripheral		rw
210	GPDMA_C6CONFIG	11	3	FLOWCNTRL	Flow control and transfer type		rw
211	GPDMA_C6CONFIG	14	1	IE	Interrupt error mask		rw
212	GPDMA_C6CONFIG	15	1	ITC	Terminal count interrupt mask		rw
213	GPDMA_C6CONFIG	16	1	L	Lock		rw
214	GPDMA_C6CONFIG	17	1	A	Active		r
215	GPDMA_C6CONFIG	18	1	H	Halt		rw
216	GPDMA_C7CONFIG	0	1	E	Channel enable	0	rw
217	GPDMA_C7CONFIG	1	5	SRCPERIPHERAL	Source peripheral		rw
218	GPDMA_C7CONFIG	6	5	DESTPERIPHERAL	Destination peripheral		rw
219	GPDMA_C7CONFIG	11	3	FLOWCNTRL	Flow control and transfer type		rw
220	GPDMA_C7CONFIG	14	1	IE	Interrupt error mask		rw
221	GPDMA_C7CONFIG	15	1	ITC	Terminal count interrupt mask		rw
222	GPDMA_C7CONFIG	16	1	L	Lock		rw
223	GPDMA_C7CONFIG	17	1	A	Active		r
224	GPDMA_C7CONFIG	18	1	H	Halt		rw