Commit Graph

4 Commits

Author SHA1 Message Date
Karl Palsson 76c0a8c289 stm32: rcc: convert to use new standard defines 2020-11-28 22:13:25 +00:00
Karl Palsson 06ee2009e8 doc: gd32f1x0: merge flash and rcc into periperhal apis
Instead of having some in peripheral_apis and some under the target
itself
2019-06-27 14:53:09 +00:00
Karl Palsson 0cd06bcc97 doc: gd32/f1x0: fix missing tags, drop wrong tags
Drop incorrect/redundant type information from doxygen parameters
Adds groupings that are referred to.
2019-06-25 21:15:35 +00:00
Icenowy Zheng 330d5fd5be gd32: add new chip series f1x0
GD32F1X0 (X can be 3, 5, 7 and 9) is a series of Cortex-M3 MCUs by
GigaDevice, which features pin-to-pin package compatibility with
STM32F030 MCU line. F150 adds USB support to F130, and F170/F190 adds
CAN support.

Currently the code mainly targets GD32F130 and F150 chips. Some register
are different between F130/150 and F170/190, just like the difference
between STM32F1 Performance line and Connectivity line.

From the perspective of registers and memory map, GD32F1X0 seems like a
mixture between STM32F1 and STM32F0 (because it is designed to be
pin-to-pin compatible with F0, but with Cortex-M3 like F1). A bunch of
code are shared between STM32 and GD32, and these code are specially
processed to include the GD32 headers instead of STM32 headers when meet
GD32F1X0.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

Reviewed-by: Karl Palsson <karlp@tweak.net.au>
gd32/rcc.[ch] are forks of stm32f1/rcc
gd32/flash.[ch] are forks of stm32f0/flash
No attempts at deduplicating this have been done at this stage.  We can
see where they move in the future.
2019-04-03 12:53:33 +00:00