stm32: rcc: convert to use new standard defines
This commit is contained in:
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c7d7a18dd7
commit
76c0a8c289
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@ -62,10 +62,10 @@ uint32_t rcc_ahb_frequency = 8000000;
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const struct rcc_clock_scale rcc_hsi_configs[] = {
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{ /* 48MHz */
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.pllmul = RCC_CFGR_PLLMUL_PLL_CLK_MUL12,
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.hpre = RCC_CFGR_HPRE_SYSCLK_NODIV,
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.ppre1 = RCC_CFGR_PPRE1_HCLK_DIV2,
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.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
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.adcpre = RCC_CFGR_ADCPRE_PCLK2_DIV8,
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.hpre = RCC_CFGR_HPRE_NODIV,
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.ppre1 = RCC_CFGR_PPRE_DIV2,
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.ppre2 = RCC_CFGR_PPRE_NODIV,
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.adcpre = RCC_CFGR_ADCPRE_DIV8,
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.use_hse = false,
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.ahb_frequency = 48000000,
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.apb1_frequency = 24000000,
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@ -73,10 +73,10 @@ const struct rcc_clock_scale rcc_hsi_configs[] = {
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},
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{ /* 64MHz */
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.pllmul = RCC_CFGR_PLLMUL_PLL_CLK_MUL16,
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.hpre = RCC_CFGR_HPRE_SYSCLK_NODIV,
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.ppre1 = RCC_CFGR_PPRE1_HCLK_DIV2,
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.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
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.adcpre = RCC_CFGR_ADCPRE_PCLK2_DIV8,
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.hpre = RCC_CFGR_HPRE_NODIV,
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.ppre1 = RCC_CFGR_PPRE_DIV2,
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.ppre2 = RCC_CFGR_PPRE_NODIV,
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.adcpre = RCC_CFGR_ADCPRE_DIV8,
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.use_hse = false,
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.ahb_frequency = 64000000,
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.apb1_frequency = 32000000,
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@ -87,10 +87,10 @@ const struct rcc_clock_scale rcc_hsi_configs[] = {
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const struct rcc_clock_scale rcc_hse8_configs[] = {
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{ /* 72MHz */
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.pllmul = RCC_CFGR_PLLMUL_PLL_CLK_MUL9,
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.hpre = RCC_CFGR_HPRE_SYSCLK_NODIV,
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.ppre1 = RCC_CFGR_PPRE1_HCLK_DIV2,
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.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
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.adcpre = RCC_CFGR_ADCPRE_PCLK2_DIV8,
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.hpre = RCC_CFGR_HPRE_NODIV,
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.ppre1 = RCC_CFGR_PPRE_DIV2,
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.ppre2 = RCC_CFGR_PPRE_NODIV,
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.adcpre = RCC_CFGR_ADCPRE_DIV8,
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.usbpre = RCC_CFGR_USBPRE_PLL_CLK_DIV1_5,
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.use_hse = true,
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.pll_hse_prediv = RCC_CFGR2_PREDIV_NODIV,
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@ -631,10 +631,10 @@ void rcc_clock_setup_in_hsi_out_64mhz(void)
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* Set prescalers for AHB, ADC, APB1, APB2.
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* Do this before touching the PLL (TODO: why?).
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*/
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rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 64MHz Max. 72MHz */
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rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Set. 8MHz Max. 14MHz */
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rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 32MHz Max. 36MHz */
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rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 64MHz Max. 72MHz */
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rcc_set_hpre(RCC_CFGR_HPRE_NODIV); /* Set. 64MHz Max. 72MHz */
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rcc_set_adcpre(RCC_CFGR_ADCPRE_DIV8); /* Set. 8MHz Max. 14MHz */
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rcc_set_ppre1(RCC_CFGR_PPRE_DIV2); /* Set. 32MHz Max. 36MHz */
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rcc_set_ppre2(RCC_CFGR_PPRE_NODIV); /* Set. 64MHz Max. 72MHz */
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/*
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* Sysclk is running with 64MHz -> 2 waitstates.
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@ -684,10 +684,10 @@ void rcc_clock_setup_in_hsi_out_48mhz(void)
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* Set prescalers for AHB, ADC, APB1, APB2.
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* Do this before touching the PLL (TODO: why?).
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*/
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rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /*Set.48MHz Max.72MHz */
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rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /*Set. 6MHz Max.14MHz */
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rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /*Set.24MHz Max.36MHz */
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rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /*Set.48MHz Max.72MHz */
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rcc_set_hpre(RCC_CFGR_HPRE_NODIV); /*Set.48MHz Max.72MHz */
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rcc_set_adcpre(RCC_CFGR_ADCPRE_DIV8); /*Set. 6MHz Max.14MHz */
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rcc_set_ppre1(RCC_CFGR_PPRE_DIV2); /*Set.24MHz Max.36MHz */
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rcc_set_ppre2(RCC_CFGR_PPRE_NODIV); /*Set.48MHz Max.72MHz */
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rcc_set_usbpre(RCC_CFGR_USBPRE_PLL_CLK_NODIV); /*Set.48MHz Max.48MHz */
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/*
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@ -738,10 +738,10 @@ void rcc_clock_setup_in_hsi_out_24mhz(void)
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* Set prescalers for AHB, ADC, APB1, APB2.
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* Do this before touching the PLL (TODO: why?).
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*/
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rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 24MHz Max. 24MHz */
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rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV2); /* Set. 12MHz Max. 12MHz */
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rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_NODIV); /* Set. 24MHz Max. 24MHz */
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rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 24MHz Max. 24MHz */
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rcc_set_hpre(RCC_CFGR_HPRE_NODIV); /* Set. 24MHz Max. 24MHz */
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rcc_set_adcpre(RCC_CFGR_ADCPRE_DIV2); /* Set. 12MHz Max. 12MHz */
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rcc_set_ppre1(RCC_CFGR_PPRE_NODIV); /* Set. 24MHz Max. 24MHz */
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rcc_set_ppre2(RCC_CFGR_PPRE_NODIV); /* Set. 24MHz Max. 24MHz */
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/*
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* Sysclk is (will be) running with 24MHz -> 0 waitstates.
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@ -796,10 +796,10 @@ void rcc_clock_setup_in_hse_8mhz_out_24mhz(void)
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* Set prescalers for AHB, ADC, APB1, APB2.
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* Do this before touching the PLL (TODO: why?).
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*/
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rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 24MHz Max. 72MHz */
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rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV2); /* Set. 12MHz Max. 14MHz */
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rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_NODIV); /* Set. 24MHz Max. 36MHz */
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rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 24MHz Max. 72MHz */
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rcc_set_hpre(RCC_CFGR_HPRE_NODIV); /* Set. 24MHz Max. 72MHz */
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rcc_set_adcpre(RCC_CFGR_ADCPRE_DIV2); /* Set. 12MHz Max. 14MHz */
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rcc_set_ppre1(RCC_CFGR_PPRE_NODIV); /* Set. 24MHz Max. 36MHz */
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rcc_set_ppre2(RCC_CFGR_PPRE_NODIV); /* Set. 24MHz Max. 72MHz */
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/*
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* Sysclk runs with 24MHz -> 0 waitstates.
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@ -860,10 +860,10 @@ void rcc_clock_setup_in_hse_8mhz_out_72mhz(void)
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* Set prescalers for AHB, ADC, APB1, APB2.
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* Do this before touching the PLL (TODO: why?).
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*/
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rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */
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rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Set. 9MHz Max. 14MHz */
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rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */
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rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */
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rcc_set_hpre(RCC_CFGR_HPRE_NODIV); /* Set. 72MHz Max. 72MHz */
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rcc_set_adcpre(RCC_CFGR_ADCPRE_DIV8); /* Set. 9MHz Max. 14MHz */
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rcc_set_ppre1(RCC_CFGR_PPRE_DIV2); /* Set. 36MHz Max. 36MHz */
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rcc_set_ppre2(RCC_CFGR_PPRE_NODIV); /* Set. 72MHz Max. 72MHz */
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/*
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* Sysclk runs with 72MHz -> 2 waitstates.
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@ -924,10 +924,10 @@ void rcc_clock_setup_in_hse_12mhz_out_72mhz(void)
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* Set prescalers for AHB, ADC, APB1, APB2.
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* Do this before touching the PLL (TODO: why?).
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*/
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rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */
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rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Set. 12MHz Max. 14MHz */
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rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */
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rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */
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rcc_set_hpre(RCC_CFGR_HPRE_NODIV); /* Set. 72MHz Max. 72MHz */
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rcc_set_adcpre(RCC_CFGR_ADCPRE_DIV6); /* Set. 12MHz Max. 14MHz */
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rcc_set_ppre1(RCC_CFGR_PPRE_DIV2); /* Set. 36MHz Max. 36MHz */
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rcc_set_ppre2(RCC_CFGR_PPRE_NODIV); /* Set. 72MHz Max. 72MHz */
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/*
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* Sysclk runs with 72MHz -> 2 waitstates.
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@ -988,10 +988,10 @@ void rcc_clock_setup_in_hse_16mhz_out_72mhz(void)
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* Set prescalers for AHB, ADC, APB1, APB2.
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* Do this before touching the PLL (TODO: why?).
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*/
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rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */
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rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Set. 12MHz Max. 14MHz */
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rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */
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rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */
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rcc_set_hpre(RCC_CFGR_HPRE_NODIV); /* Set. 72MHz Max. 72MHz */
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rcc_set_adcpre(RCC_CFGR_ADCPRE_DIV6); /* Set. 12MHz Max. 14MHz */
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rcc_set_ppre1(RCC_CFGR_PPRE_DIV2); /* Set. 36MHz Max. 36MHz */
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rcc_set_ppre2(RCC_CFGR_PPRE_NODIV); /* Set. 72MHz Max. 72MHz */
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/*
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* Sysclk runs with 72MHz -> 2 waitstates.
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@ -1053,10 +1053,10 @@ void rcc_clock_setup_in_hse_25mhz_out_72mhz(void)
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* Set prescalers for AHB, ADC, APB1, APB2.
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* Do this before touching the PLL (TODO: why?).
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*/
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rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */
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rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Set. 12MHz Max. 14MHz */
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rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */
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rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */
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rcc_set_hpre(RCC_CFGR_HPRE_NODIV); /* Set. 72MHz Max. 72MHz */
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rcc_set_adcpre(RCC_CFGR_ADCPRE_DIV6); /* Set. 12MHz Max. 14MHz */
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rcc_set_ppre1(RCC_CFGR_PPRE_DIV2); /* Set. 36MHz Max. 36MHz */
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rcc_set_ppre2(RCC_CFGR_PPRE_NODIV); /* Set. 72MHz Max. 72MHz */
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/* Set pll2 prediv and multiplier */
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rcc_set_prediv2(RCC_CFGR2_PREDIV2_DIV5);
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@ -54,9 +54,9 @@ const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = {
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.plln = 240,
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.pllp = 2,
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.pllq = 5,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.hpre = RCC_CFGR_HPRE_NODIV,
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.ppre1 = RCC_CFGR_PPRE_DIV4,
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.ppre2 = RCC_CFGR_PPRE_DIV2,
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.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
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FLASH_ACR_LATENCY_3WS,
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.apb1_frequency = 30000000,
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@ -48,9 +48,9 @@ const struct rcc_clock_scale rcc_hsi_configs[] = {
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{ /* 48MHz */
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.pllmul = RCC_CFGR_PLLMUL_MUL12,
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.pllsrc = RCC_CFGR_PLLSRC_HSI_DIV2,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE1_DIV_2,
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.ppre2 = RCC_CFGR_PPRE2_DIV_NONE,
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.hpre = RCC_CFGR_HPRE_NODIV,
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.ppre1 = RCC_CFGR_PPRE_DIV2,
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.ppre2 = RCC_CFGR_PPRE_NODIV,
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.flash_waitstates = 1,
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.ahb_frequency = 48000000,
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.apb1_frequency = 24000000,
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@ -59,9 +59,9 @@ const struct rcc_clock_scale rcc_hsi_configs[] = {
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{ /* 64MHz */
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.pllmul = RCC_CFGR_PLLMUL_MUL16,
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.pllsrc = RCC_CFGR_PLLSRC_HSI_DIV2,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE1_DIV_2,
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.ppre2 = RCC_CFGR_PPRE2_DIV_NONE,
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.hpre = RCC_CFGR_HPRE_NODIV,
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.ppre1 = RCC_CFGR_PPRE_DIV2,
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.ppre2 = RCC_CFGR_PPRE_NODIV,
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.flash_waitstates = 2,
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.ahb_frequency = 64000000,
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.apb1_frequency = 32000000,
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@ -76,9 +76,9 @@ const struct rcc_clock_scale rcc_hse8mhz_configs[] = {
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.plldiv = RCC_CFGR2_PREDIV_NODIV,
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.usbdiv1 = false,
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.flash_waitstates = 2,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE1_DIV_2,
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.ppre2 = RCC_CFGR_PPRE2_DIV_NONE,
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.hpre = RCC_CFGR_HPRE_NODIV,
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.ppre1 = RCC_CFGR_PPRE_DIV2,
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.ppre2 = RCC_CFGR_PPRE_NODIV,
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.ahb_frequency = 72e6,
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.apb1_frequency = 36e6,
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.apb2_frequency = 72e6,
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@ -57,9 +57,9 @@ const struct rcc_clock_scale rcc_hsi_configs[RCC_CLOCK_3V3_END] = {
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.pllq = 7,
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.pllr = 0,
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.pll_source = RCC_CFGR_PLLSRC_HSI_CLK,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_2,
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.ppre2 = RCC_CFGR_PPRE_DIV_NONE,
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.hpre = RCC_CFGR_HPRE_NODIV,
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.ppre1 = RCC_CFGR_PPRE_DIV2,
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.ppre2 = RCC_CFGR_PPRE_NODIV,
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.voltage_scale = PWR_SCALE1,
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.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
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FLASH_ACR_LATENCY_2WS,
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@ -74,9 +74,9 @@ const struct rcc_clock_scale rcc_hsi_configs[RCC_CLOCK_3V3_END] = {
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.pllq = 7,
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.pllr = 0,
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.pll_source = RCC_CFGR_PLLSRC_HSI_CLK,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.hpre = RCC_CFGR_HPRE_NODIV,
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.ppre1 = RCC_CFGR_PPRE_DIV4,
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.ppre2 = RCC_CFGR_PPRE_DIV2,
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.voltage_scale = PWR_SCALE1,
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.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
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FLASH_ACR_LATENCY_5WS,
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@ -91,9 +91,9 @@ const struct rcc_clock_scale rcc_hsi_configs[RCC_CLOCK_3V3_END] = {
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.pllq = 8,
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.pllr = 0,
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.pll_source = RCC_CFGR_PLLSRC_HSI_CLK,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.hpre = RCC_CFGR_HPRE_NODIV,
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.ppre1 = RCC_CFGR_PPRE_DIV4,
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.ppre2 = RCC_CFGR_PPRE_DIV2,
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.voltage_scale = PWR_SCALE1,
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.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
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FLASH_ACR_LATENCY_5WS,
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@ -111,9 +111,9 @@ const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = {
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.pllq = 7,
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.pllr = 0,
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.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_2,
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.ppre2 = RCC_CFGR_PPRE_DIV_NONE,
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.hpre = RCC_CFGR_HPRE_NODIV,
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.ppre1 = RCC_CFGR_PPRE_DIV2,
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.ppre2 = RCC_CFGR_PPRE_NODIV,
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.voltage_scale = PWR_SCALE1,
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.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
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FLASH_ACR_LATENCY_2WS,
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@ -128,9 +128,9 @@ const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = {
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.pllq = 7,
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.pllr = 0,
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.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.hpre = RCC_CFGR_HPRE_NODIV,
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.ppre1 = RCC_CFGR_PPRE_DIV4,
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.ppre2 = RCC_CFGR_PPRE_DIV2,
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.voltage_scale = PWR_SCALE1,
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.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
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FLASH_ACR_LATENCY_5WS,
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@ -145,9 +145,9 @@ const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = {
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.pllq = 8,
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.pllr = 0,
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.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
|
||||
.ppre1 = RCC_CFGR_PPRE_DIV_4,
|
||||
.ppre2 = RCC_CFGR_PPRE_DIV_2,
|
||||
.hpre = RCC_CFGR_HPRE_NODIV,
|
||||
.ppre1 = RCC_CFGR_PPRE_DIV4,
|
||||
.ppre2 = RCC_CFGR_PPRE_DIV2,
|
||||
.voltage_scale = PWR_SCALE1,
|
||||
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
|
||||
FLASH_ACR_LATENCY_5WS,
|
||||
|
@ -165,9 +165,9 @@ const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = {
|
|||
.pllq = 7,
|
||||
.pllr = 0,
|
||||
.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
|
||||
.hpre = RCC_CFGR_HPRE_DIV_NONE,
|
||||
.ppre1 = RCC_CFGR_PPRE_DIV_2,
|
||||
.ppre2 = RCC_CFGR_PPRE_DIV_NONE,
|
||||
.hpre = RCC_CFGR_HPRE_NODIV,
|
||||
.ppre1 = RCC_CFGR_PPRE_DIV2,
|
||||
.ppre2 = RCC_CFGR_PPRE_NODIV,
|
||||
.voltage_scale = PWR_SCALE1,
|
||||
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
|
||||
FLASH_ACR_LATENCY_2WS,
|
||||
|
@ -182,9 +182,9 @@ const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = {
|
|||
.pllq = 7,
|
||||
.pllr = 0,
|
||||
.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
|
||||
.hpre = RCC_CFGR_HPRE_DIV_NONE,
|
||||
.ppre1 = RCC_CFGR_PPRE_DIV_4,
|
||||
.ppre2 = RCC_CFGR_PPRE_DIV_2,
|
||||
.hpre = RCC_CFGR_HPRE_NODIV,
|
||||
.ppre1 = RCC_CFGR_PPRE_DIV4,
|
||||
.ppre2 = RCC_CFGR_PPRE_DIV2,
|
||||
.voltage_scale = PWR_SCALE1,
|
||||
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
|
||||
FLASH_ACR_LATENCY_5WS,
|
||||
|
@ -199,9 +199,9 @@ const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = {
|
|||
.pllq = 8,
|
||||
.pllr = 0,
|
||||
.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
|
||||
.hpre = RCC_CFGR_HPRE_DIV_NONE,
|
||||
.ppre1 = RCC_CFGR_PPRE_DIV_4,
|
||||
.ppre2 = RCC_CFGR_PPRE_DIV_2,
|
||||
.hpre = RCC_CFGR_HPRE_NODIV,
|
||||
.ppre1 = RCC_CFGR_PPRE_DIV4,
|
||||
.ppre2 = RCC_CFGR_PPRE_DIV2,
|
||||
.voltage_scale = PWR_SCALE1,
|
||||
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
|
||||
FLASH_ACR_LATENCY_5WS,
|
||||
|
@ -219,9 +219,9 @@ const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = {
|
|||
.pllq = 7,
|
||||
.pllr = 0,
|
||||
.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
|
||||
.hpre = RCC_CFGR_HPRE_DIV_NONE,
|
||||
.ppre1 = RCC_CFGR_PPRE_DIV_2,
|
||||
.ppre2 = RCC_CFGR_PPRE_DIV_NONE,
|
||||
.hpre = RCC_CFGR_HPRE_NODIV,
|
||||
.ppre1 = RCC_CFGR_PPRE_DIV2,
|
||||
.ppre2 = RCC_CFGR_PPRE_NODIV,
|
||||
.voltage_scale = PWR_SCALE1,
|
||||
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
|
||||
FLASH_ACR_LATENCY_2WS,
|
||||
|
@ -236,9 +236,9 @@ const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = {
|
|||
.pllq = 7,
|
||||
.pllr = 0,
|
||||
.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
|
||||
.hpre = RCC_CFGR_HPRE_DIV_NONE,
|
||||
.ppre1 = RCC_CFGR_PPRE_DIV_4,
|
||||
.ppre2 = RCC_CFGR_PPRE_DIV_2,
|
||||
.hpre = RCC_CFGR_HPRE_NODIV,
|
||||
.ppre1 = RCC_CFGR_PPRE_DIV4,
|
||||
.ppre2 = RCC_CFGR_PPRE_DIV2,
|
||||
.voltage_scale = PWR_SCALE1,
|
||||
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
|
||||
FLASH_ACR_LATENCY_5WS,
|
||||
|
@ -253,9 +253,9 @@ const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = {
|
|||
.pllq = 8,
|
||||
.pllr = 0,
|
||||
.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
|
||||
.hpre = RCC_CFGR_HPRE_DIV_NONE,
|
||||
.ppre1 = RCC_CFGR_PPRE_DIV_4,
|
||||
.ppre2 = RCC_CFGR_PPRE_DIV_2,
|
||||
.hpre = RCC_CFGR_HPRE_NODIV,
|
||||
.ppre1 = RCC_CFGR_PPRE_DIV4,
|
||||
.ppre2 = RCC_CFGR_PPRE_DIV2,
|
||||
.voltage_scale = PWR_SCALE1,
|
||||
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
|
||||
FLASH_ACR_LATENCY_5WS,
|
||||
|
@ -273,9 +273,9 @@ const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = {
|
|||
.pllq = 7,
|
||||
.pllr = 0,
|
||||
.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
|
||||
.hpre = RCC_CFGR_HPRE_DIV_NONE,
|
||||
.ppre1 = RCC_CFGR_PPRE_DIV_2,
|
||||
.ppre2 = RCC_CFGR_PPRE_DIV_NONE,
|
||||
.hpre = RCC_CFGR_HPRE_NODIV,
|
||||
.ppre1 = RCC_CFGR_PPRE_DIV2,
|
||||
.ppre2 = RCC_CFGR_PPRE_NODIV,
|
||||
.voltage_scale = PWR_SCALE1,
|
||||
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
|
||||
FLASH_ACR_LATENCY_2WS,
|
||||
|
@ -290,9 +290,9 @@ const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = {
|
|||
.pllq = 7,
|
||||
.pllr = 0,
|
||||
.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
|
||||
.hpre = RCC_CFGR_HPRE_DIV_NONE,
|
||||
.ppre1 = RCC_CFGR_PPRE_DIV_4,
|
||||
.ppre2 = RCC_CFGR_PPRE_DIV_2,
|
||||
.hpre = RCC_CFGR_HPRE_NODIV,
|
||||
.ppre1 = RCC_CFGR_PPRE_DIV4,
|
||||
.ppre2 = RCC_CFGR_PPRE_DIV2,
|
||||
.voltage_scale = PWR_SCALE1,
|
||||
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
|
||||
FLASH_ACR_LATENCY_5WS,
|
||||
|
@ -307,9 +307,9 @@ const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = {
|
|||
.pllq = 8,
|
||||
.pllr = 0,
|
||||
.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
|
||||
.hpre = RCC_CFGR_HPRE_DIV_NONE,
|
||||
.ppre1 = RCC_CFGR_PPRE_DIV_4,
|
||||
.ppre2 = RCC_CFGR_PPRE_DIV_2,
|
||||
.hpre = RCC_CFGR_HPRE_NODIV,
|
||||
.ppre1 = RCC_CFGR_PPRE_DIV4,
|
||||
.ppre2 = RCC_CFGR_PPRE_DIV2,
|
||||
.voltage_scale = PWR_SCALE1,
|
||||
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
|
||||
FLASH_ACR_LATENCY_5WS,
|
||||
|
|
|
@ -25,9 +25,9 @@ const struct rcc_clock_scale rcc_3v3[RCC_CLOCK_3V3_END] = {
|
|||
.plln = 432,
|
||||
.pllp = 2,
|
||||
.pllq = 9,
|
||||
.hpre = RCC_CFGR_HPRE_DIV_NONE,
|
||||
.ppre1 = RCC_CFGR_PPRE_DIV_4,
|
||||
.ppre2 = RCC_CFGR_PPRE_DIV_2,
|
||||
.hpre = RCC_CFGR_HPRE_NODIV,
|
||||
.ppre1 = RCC_CFGR_PPRE_DIV4,
|
||||
.ppre2 = RCC_CFGR_PPRE_DIV2,
|
||||
.vos_scale = PWR_SCALE1,
|
||||
.overdrive = 1,
|
||||
.flash_waitstates = 7,
|
||||
|
@ -39,9 +39,9 @@ const struct rcc_clock_scale rcc_3v3[RCC_CLOCK_3V3_END] = {
|
|||
.plln = 336,
|
||||
.pllp = 2,
|
||||
.pllq = 7,
|
||||
.hpre = RCC_CFGR_HPRE_DIV_NONE,
|
||||
.ppre1 = RCC_CFGR_PPRE_DIV_4,
|
||||
.ppre2 = RCC_CFGR_PPRE_DIV_2,
|
||||
.hpre = RCC_CFGR_HPRE_NODIV,
|
||||
.ppre1 = RCC_CFGR_PPRE_DIV4,
|
||||
.ppre2 = RCC_CFGR_PPRE_DIV2,
|
||||
.vos_scale = PWR_SCALE2,
|
||||
.overdrive = 1,
|
||||
.flash_waitstates = 5,
|
||||
|
@ -53,9 +53,9 @@ const struct rcc_clock_scale rcc_3v3[RCC_CLOCK_3V3_END] = {
|
|||
.plln = 240,
|
||||
.pllp = 2,
|
||||
.pllq = 5,
|
||||
.hpre = RCC_CFGR_HPRE_DIV_NONE,
|
||||
.ppre1 = RCC_CFGR_PPRE_DIV_4,
|
||||
.ppre2 = RCC_CFGR_PPRE_DIV_2,
|
||||
.hpre = RCC_CFGR_HPRE_NODIV,
|
||||
.ppre1 = RCC_CFGR_PPRE_DIV4,
|
||||
.ppre2 = RCC_CFGR_PPRE_DIV2,
|
||||
.vos_scale = PWR_SCALE3,
|
||||
.overdrive = 0,
|
||||
.flash_waitstates = 3,
|
||||
|
@ -67,9 +67,9 @@ const struct rcc_clock_scale rcc_3v3[RCC_CLOCK_3V3_END] = {
|
|||
.plln = 144,
|
||||
.pllp = 2,
|
||||
.pllq = 3,
|
||||
.hpre = RCC_CFGR_HPRE_DIV_NONE,
|
||||
.ppre1 = RCC_CFGR_PPRE_DIV_4,
|
||||
.ppre2 = RCC_CFGR_PPRE_DIV_2,
|
||||
.hpre = RCC_CFGR_HPRE_NODIV,
|
||||
.ppre1 = RCC_CFGR_PPRE_DIV4,
|
||||
.ppre2 = RCC_CFGR_PPRE_DIV2,
|
||||
.vos_scale = PWR_SCALE3,
|
||||
.overdrive = 0,
|
||||
.flash_waitstates = 2,
|
||||
|
@ -81,9 +81,9 @@ const struct rcc_clock_scale rcc_3v3[RCC_CLOCK_3V3_END] = {
|
|||
.plln = 192,
|
||||
.pllp = 4,
|
||||
.pllq = 4,
|
||||
.hpre = RCC_CFGR_HPRE_DIV_NONE,
|
||||
.ppre1 = RCC_CFGR_PPRE_DIV_2,
|
||||
.ppre2 = RCC_CFGR_PPRE_DIV_2,
|
||||
.hpre = RCC_CFGR_HPRE_NODIV,
|
||||
.ppre1 = RCC_CFGR_PPRE_DIV2,
|
||||
.ppre2 = RCC_CFGR_PPRE_DIV2,
|
||||
.vos_scale = PWR_SCALE3,
|
||||
.overdrive = 0,
|
||||
.flash_waitstates = 1,
|
||||
|
@ -95,9 +95,9 @@ const struct rcc_clock_scale rcc_3v3[RCC_CLOCK_3V3_END] = {
|
|||
.plln = 192,
|
||||
.pllp = 8,
|
||||
.pllq = 4,
|
||||
.hpre = RCC_CFGR_HPRE_DIV_NONE,
|
||||
.ppre1 = RCC_CFGR_PPRE_DIV_NONE,
|
||||
.ppre2 = RCC_CFGR_PPRE_DIV_NONE,
|
||||
.hpre = RCC_CFGR_HPRE_NODIV,
|
||||
.ppre1 = RCC_CFGR_PPRE_NODIV,
|
||||
.ppre2 = RCC_CFGR_PPRE_NODIV,
|
||||
.vos_scale = PWR_SCALE3,
|
||||
.overdrive = 0,
|
||||
.flash_waitstates = 0,
|
||||
|
|
|
@ -53,9 +53,9 @@ const struct rcc_clock_scale rcc_clock_config[RCC_CLOCK_CONFIG_END] = {
|
|||
.pll_source = RCC_CFGR_PLLSRC_HSI_CLK,
|
||||
.pll_mul = RCC_CFGR_PLLMUL_MUL3,
|
||||
.pll_div = RCC_CFGR_PLLDIV_DIV2,
|
||||
.hpre = RCC_CFGR_HPRE_SYSCLK_NODIV,
|
||||
.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
|
||||
.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
|
||||
.hpre = RCC_CFGR_HPRE_NODIV,
|
||||
.ppre1 = RCC_CFGR_PPRE_NODIV,
|
||||
.ppre2 = RCC_CFGR_PPRE_NODIV,
|
||||
.voltage_scale = PWR_SCALE1,
|
||||
.flash_waitstates = 1,
|
||||
.ahb_frequency = 24000000,
|
||||
|
@ -66,9 +66,9 @@ const struct rcc_clock_scale rcc_clock_config[RCC_CLOCK_CONFIG_END] = {
|
|||
.pll_source = RCC_CFGR_PLLSRC_HSI_CLK,
|
||||
.pll_mul = RCC_CFGR_PLLMUL_MUL6,
|
||||
.pll_div = RCC_CFGR_PLLDIV_DIV3,
|
||||
.hpre = RCC_CFGR_HPRE_SYSCLK_NODIV,
|
||||
.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
|
||||
.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
|
||||
.hpre = RCC_CFGR_HPRE_NODIV,
|
||||
.ppre1 = RCC_CFGR_PPRE_NODIV,
|
||||
.ppre2 = RCC_CFGR_PPRE_NODIV,
|
||||
.voltage_scale = PWR_SCALE1,
|
||||
.flash_waitstates = 1,
|
||||
.ahb_frequency = 32000000,
|
||||
|
@ -76,9 +76,9 @@ const struct rcc_clock_scale rcc_clock_config[RCC_CLOCK_CONFIG_END] = {
|
|||
.apb2_frequency = 32000000,
|
||||
},
|
||||
{ /* 16MHz HSI raw */
|
||||
.hpre = RCC_CFGR_HPRE_SYSCLK_NODIV,
|
||||
.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
|
||||
.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
|
||||
.hpre = RCC_CFGR_HPRE_NODIV,
|
||||
.ppre1 = RCC_CFGR_PPRE_NODIV,
|
||||
.ppre2 = RCC_CFGR_PPRE_NODIV,
|
||||
.voltage_scale = PWR_SCALE1,
|
||||
.flash_waitstates = 0,
|
||||
.ahb_frequency = 16000000,
|
||||
|
@ -86,9 +86,9 @@ const struct rcc_clock_scale rcc_clock_config[RCC_CLOCK_CONFIG_END] = {
|
|||
.apb2_frequency = 16000000,
|
||||
},
|
||||
{ /* 4MHz HSI raw */
|
||||
.hpre = RCC_CFGR_HPRE_SYSCLK_DIV4,
|
||||
.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
|
||||
.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
|
||||
.hpre = RCC_CFGR_HPRE_DIV4,
|
||||
.ppre1 = RCC_CFGR_PPRE_NODIV,
|
||||
.ppre2 = RCC_CFGR_PPRE_NODIV,
|
||||
.voltage_scale = PWR_SCALE1,
|
||||
.flash_waitstates = 0,
|
||||
.ahb_frequency = 4000000,
|
||||
|
@ -96,9 +96,9 @@ const struct rcc_clock_scale rcc_clock_config[RCC_CLOCK_CONFIG_END] = {
|
|||
.apb2_frequency = 4000000,
|
||||
},
|
||||
{ /* 4MHz MSI raw */
|
||||
.hpre = RCC_CFGR_HPRE_SYSCLK_NODIV,
|
||||
.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
|
||||
.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
|
||||
.hpre = RCC_CFGR_HPRE_NODIV,
|
||||
.ppre1 = RCC_CFGR_PPRE_NODIV,
|
||||
.ppre2 = RCC_CFGR_PPRE_NODIV,
|
||||
.voltage_scale = PWR_SCALE1,
|
||||
.flash_waitstates = 0,
|
||||
.ahb_frequency = 4194000,
|
||||
|
@ -107,9 +107,9 @@ const struct rcc_clock_scale rcc_clock_config[RCC_CLOCK_CONFIG_END] = {
|
|||
.msi_range = RCC_ICSCR_MSIRANGE_4MHZ,
|
||||
},
|
||||
{ /* 2MHz MSI raw */
|
||||
.hpre = RCC_CFGR_HPRE_SYSCLK_NODIV,
|
||||
.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
|
||||
.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
|
||||
.hpre = RCC_CFGR_HPRE_NODIV,
|
||||
.ppre1 = RCC_CFGR_PPRE_NODIV,
|
||||
.ppre2 = RCC_CFGR_PPRE_NODIV,
|
||||
.voltage_scale = PWR_SCALE1,
|
||||
.flash_waitstates = 0,
|
||||
.ahb_frequency = 2097000,
|
||||
|
|
Loading…
Reference in New Issue