Updates to a base set of includes to map to the h7 include files which are
mainly based on the f7 versions for simple devices (e.g. SPI, USART, GPIO).
Custom files that have been implemented from the datasheet/ref manual include
the memory map, RCC, PWR definitions, and irq.json file for generation of
nvic files for interrupt mapping.
Additional functionality, especially PLL and tweaks for non-F7 compatible
implementations coming in future commits.
Added documentation tree configuration.
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
Changed dmaX_streamX to dmaX_strX in a few places for consistency
The leading - makes it rather inconsistent with the majority of other
projects around the world. Use the form everyone else uses.
To solve this, properly pass prefix to inner makes as was always
intended.
Fixes: https://github.com/libopencm3/libopencm3/issues/1058
SWM050 is a series of MCU made by Foshan Synwit Tech. It contains a
Cortex-M0 CPU core, 8KiB of Flash and 1KiB of SRAM. The only peripherals
are GPIO, Timer and WDT. There's only two parts in this series, with
either TSSOP-8 or SSOP-16 packages.
This commit introduces the interrupt vector and GPIO support for them.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
GD32F1X0 (X can be 3, 5, 7 and 9) is a series of Cortex-M3 MCUs by
GigaDevice, which features pin-to-pin package compatibility with
STM32F030 MCU line. F150 adds USB support to F130, and F170/F190 adds
CAN support.
Currently the code mainly targets GD32F130 and F150 chips. Some register
are different between F130/150 and F170/190, just like the difference
between STM32F1 Performance line and Connectivity line.
From the perspective of registers and memory map, GD32F1X0 seems like a
mixture between STM32F1 and STM32F0 (because it is designed to be
pin-to-pin compatible with F0, but with Cortex-M3 like F1). A bunch of
code are shared between STM32 and GD32, and these code are specially
processed to include the GD32 headers instead of STM32 headers when meet
GD32F1X0.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
gd32/rcc.[ch] are forks of stm32f1/rcc
gd32/flash.[ch] are forks of stm32f0/flash
No attempts at deduplicating this have been done at this stage. We can
see where they move in the future.
The original submitter of this squished everything into one series, and
has not returned. The code mostly appears good, and review comments were
followed for the most part. The project doesn't really maintain any
testing or board farm for sam3/sam4 parts, so we're going to just trust
our users.
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
sam/4l: IRQ Configuration file (irq.json)
sam/4l: Basic Memory Map.
sam/4l: GPIO Defines.
sam/4l: GPIO Functions
Added everything that needed to compile the library: Makefile, Linker
Script and common includes.
sam/4l: SCIF function to start OSC.
sam/4l: GPIO Enable/Disable and Multiplexing configuration functions.
sam/4l: PLL Clock configuration.
sam/4l: Peripheral clock configuration and basic USART support.
sam: USART Character length configuration.
sam/4l: Generic Clock configuration functions.
sam/4l: Analog to Digital Converter Interface (ADCIFE) basic support.
Instead of expecting a posix-ish "find" in the shell, simply leverage
our knowledge of our source structure to make a single list using make's
builtin wildcard() functionality.
Fixes https://github.com/libopencm3/libopencm3/issues/828
Sometimes you're working on a subset of targets, and want to do full
clean/builds, but don't need to clean and rebuild families you're not
working with. This is a pure syntactic change that makes it easier to
simply comment out lines for targets, instead of having to mangle line
continuations.
Thoughts: should this be a "sam0" family rather than samd? (Much like Atmel's
own software package lumps all the cortex-m0+ devices in one family)
This was enough to get a basic blinky working at least.
This has hurt many many many people over it's lifetime, by confusing their
multilib toolchains. Simply drop it outright. People who _really_ know what
they're doing are still perfectly entitled to "install" portions of this
project in suitable locations for their own use.
Values from RM0351rev1, with the correction of the duplicate TIM1_CC entry.
Only stub support so far, but this opens up the beginning of build testing.
Most changes are noise from doxygen.
Readme udpated to explain newer FP_FLAGS for m7
stm32f7 library is skipped if the toolchain doesn't support it yet.
Freescale Vybrid is a familiy of ARM SoC, wheras the VF6xx models
have two cores in one SoC, a Cortex-A5 and a Cortex-M4. This adds
initial support for the Cortex-M4 in the libopencm3 library.
By using two different ram areas (pc_ram and ps_ram) the user can
put the code in a RAM area bounded to the code bus. The data can
be stored in the data area. However, currently the initial values
of for the variables in the data section are stored in the code
section and copied to the ram section by the initialization code
(like it's copied from ROM to RAM on microcontrollers).
When full path of a source directory has spaces in it, that makes
shell and Make split the path, so special treatment is
necessary. Additionally, @F doesn't honour the escaping, so has to be
avoided.
Reported-by: Roman Faizullin <roman@faizullin.info>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
So that the navigation pane works correctly in browsers.
Some additional doc fixes put in where found (but many more still to go).
Added some dummy .c and .h files to bring the associated docs into line.
makefile changed to allow 'make html' as well as 'make doc' (the latter only does html anyway).
This converts all the YAML files to JSON files, as json parsing is built
into python instead of being a separate library requiring installation.
YAML is a superset of JSON, but putting comments in is not quite as obvious
as it is in yaml.
The following glue was used to convert yaml to json:
python -c 'import sys, yaml, json; json.dump(yaml.load(sys.stdin), sys.stdout, indent=4)' < $1 > $2
Clearly I haven't tested this on every single platform, and this
doesn't address the large blobs of yaml in the lpc4300 scripts directory,
only the cortex NVIC generation process.
I've tested a few IRQ driven example apps, and I've checked the generated
output of some known cases like the LM3s that has explicit gaps, and they are
all generated correctly.
Each thread runs its own stylecheck script, outputing to {FILENAME}.stylecheck file. If that file is empty, it is deleted. Otherwise it is printed to the output and stays in the sources directory to indicate something in that file is not correct.
The file mangling and cat-ing is needed because of multithreaded nature of paralell make. (We like single file to be an block of text on the output).
New PHONY added that make styleclean clears all .stylecheck files.
New functionality added to check only single file (specifyilng the file with stylecheck extension) ie
make lib/usb/usb.c.stylecheck
BUG: if someone edit that file, .stylecheck file is not regenerated - missing dependency on the %.stylecheck rule. FIX: make styleclean stylecheck rebuild all style errors
Performance:
make stylecheck 1:43 -> 1:54 (slightly slower due to file creation)
make stylecheck -j8 1:43 -> 0:34 (Rapidly faster)
note the -j option must be specified with number, OS Windows cannot handle one thread per file.
make clean 34.64s -> 35.35s
make clean -j 14.00s -> 14.16s
(measured on Core2 quad, 2.84GHz, 4GB ram, windows x86)
Added overhead is logging the operation with every yamlfile to output.
- Makefiles now include building f3 src directory.
- Gpio support added. gpio_common_f24 changed to support also f3.
- f3 still not compiling, but f2 compile not broken (probably also f4).
We now have a subdirectory containing register definitions in scripts,
this confuses the install command so we have to be more specific about
which scripts to install. We actually only want to install the black
magic scripts from there as they are useful for locm3 users.
Fabio Pugliese Ornellas