msp432/e4: new target
Basic memory map and system control. Originally tracked via: https://github.com/libopencm3/libopencm3/pull/946
This commit is contained in:
Dmitry Rezvanov
Karl Palsson
parent
0c91dbf57e
commit
2adefd95fe
2
Makefile
2
Makefile
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@ -30,7 +30,7 @@ SRCLIBDIR:= $(subst $(space),\$(space),$(realpath lib))
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TARGETS ?= stm32/f0 stm32/f1 stm32/f2 stm32/f3 stm32/f4 stm32/f7 \
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stm32/l0 stm32/l1 stm32/l4 \
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lpc13xx lpc17xx lpc43xx/m4 lpc43xx/m0 \
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lm3s lm4f \
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lm3s lm4f msp432/e4 \
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efm32/tg efm32/g efm32/lg efm32/gg efm32/hg efm32/wg \
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efm32/ezr32wg \
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sam/3a sam/3n sam/3s sam/3u sam/3x sam/4l \
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@ -64,6 +64,9 @@
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/* Yes, we use the same interrupt table for both LM3S and LM4F */
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# include <libopencm3/lm3s/nvic.h>
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#elif defined(MSP432E4)
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# include <libopencm3/msp432/e4/nvic.h>
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#elif defined(VF6XX)
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# include <libopencm3/vf6xx/nvic.h>
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@ -0,0 +1,35 @@
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/** @mainpage libopencm3 MSP432E4
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@version 1.0.0
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@date 29 July 2018
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API documentation for Texas Instruments MSP432E4xx Cortex M4F series.
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LGPL License Terms @ref lgpl_license
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*/
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/** @defgroup peripheral_apis Peripheral APIs
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* APIs for device peripherals
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*/
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/** @defgroup MSP432E4xx MSP432E4xx
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Libraries for Texas Instruments MSP432E4xx series.
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@version 1.0.0
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@date 29 July 2018
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LGPL License Terms @ref lgpl_license
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*/
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/** @defgroup MSP432E4xx_defines MSP432E4xx Defines
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*
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@brief Defined Constants and Types for the MSP432E4xx series.
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@version 1.0.0
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@date 29 July 2018
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LGPL License Terms @ref lgpl_license
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*/
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@ -0,0 +1,102 @@
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{
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"irqs": [
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"gpioa",
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"gpiob",
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"gpioc",
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"gpiod",
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"gpioe",
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"uart0",
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"uart1",
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"ssi0",
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"i2c0",
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"pwm0_fault",
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"pwm0_0",
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"pwm0_1",
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"pwm0_2",
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"qei0",
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"adc0ss0",
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"adc0ss1",
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"adc0ss2",
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"adc0ss3",
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"watchdog0",
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"timer0a",
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"timer0b",
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"timer1a",
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"timer1b",
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"timer2a",
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"timer2b",
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"comp0",
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"comp1",
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"comp2",
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"sysctl",
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"flash_ctrl",
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"gpiof",
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"gpiog",
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"gpioh",
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"uart2",
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"ssi1",
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"timer3a",
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"timer3b",
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"i2c1",
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"can0",
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"can1",
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"emac0",
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"hib",
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"usb0",
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"pwm0_3",
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"udma",
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"udmaerr",
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"adc1ss0",
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"adc1ss1",
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"adc1ss2",
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"adc1ss3",
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"epi0",
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"gpioj",
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"gpiok",
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"gpiol",
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"ssi2",
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"ssi3",
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"uart3",
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"uart4",
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"uart5",
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"uart6",
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"uart7",
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"i2c2",
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"i2c3",
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"timer4a",
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"timer4b",
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"timer5a",
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"timer5b",
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"sysexc",
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"i2c4",
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"i2c5",
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"gpiom",
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"gpion",
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"gpiop0",
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"gpiop1",
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"gpiop3",
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"gpiop4",
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"gpiop5",
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"gpiop6",
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"gpiop7",
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"gpioq0",
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"gpioq1",
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"gpioq2",
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"gpioq3",
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"gpioq4",
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"gpioq5",
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"gpioq6",
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"gpioq7",
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"timer6a",
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"timer6b",
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"timer7a",
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"timer7b",
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"i2c6",
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"i2c7",
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"i2c8",
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"i2c9"
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],
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"partname_humanreadable": "MSP432 E4 series",
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"partname_doxygen": "MSP432E4",
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"includeguard": "LIBOPENCM3_MSP432_E4_NVIC_H"
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}
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@ -0,0 +1,174 @@
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/** @defgroup msp432e4_memorymap MSP432E4xx Memory Map
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*
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* @ingroup MSP432E4xx_defines
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*
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* @brief Memory map for the MSP432E4xx devices
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*
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* @version 1.0.0
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*
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* @date 22 July 2018
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
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* Copyright (C) 2018 Dmitry Rezvanov <dmitry.rezvanov@yandex.ru>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#ifndef MSP432E4_MEMORYMAP_H
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#define MSP432E4_MEMORYMAP_H
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#include <libopencm3/cm3/common.h>
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/* --- MSP432E4xx specific peripheral definitions --------------------------- */
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/** System Control Base Address */
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#define SYSCTL_BASE (0x400FE000U)
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/** Hibernation Module Base Address */
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#define HIB_BASE (0x400FC000U)
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/** Flash Controller Base Address */
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#define FLASH_CTRL_BASE (0x400FD000U)
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/** EEPROM Controller Base Address */
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#define EEPROM_BASE (0x400AF000U)
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/** Micro Direct Memory Access Base Address */
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#define DMA_BASE (0x400FF000U)
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/** Advance Encryption Standard Accelerator Base Address */
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#define AES_BASE (0x44036000U)
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/** Analog-to-Digital Converter Base Address */
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#define ADC0_BASE (0x40038000U)
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#define ADC1_BASE (0x40039000U)
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/** Controller Area Network Base Address */
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#define CAN0_BASE (0x40040000U)
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#define CAN1_BASE (0x40041000U)
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/** Analog Comparator Base Address */
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#define ACMP_BASE (0x4003C000U)
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/** Cyclical Redundancy Check Base Address */
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#define CRC_BASE (0x44030000U)
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/** Data Encryption Standard Accelerator Base Address */
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#define DES_BASE (0x44038000U)
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/** Ethernet Controller Base Address */
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#define EMAC_BASE (0x400EC000U)
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/** External Peripheral Interface Base Address */
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#define EPI0_BASE (0x400D0000U)
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/** General-Purpose Input/Outputs Base Address */
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#define GPIOA_APB_BASE (0x40004000U)
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#define GPIOB_APB_BASE (0x40005000U)
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#define GPIOC_APB_BASE (0x40006000U)
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#define GPIOD_APB_BASE (0x40007000U)
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#define GPIOE_APB_BASE (0x40024000U)
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#define GPIOF_APB_BASE (0x40025000U)
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#define GPIOG_APB_BASE (0x40026000U)
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#define GPIOH_APB_BASE (0x40027000U)
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#define GPIOJ_APB_BASE (0x4003D000U)
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/** General-Purpose Input/Outputs (AHB) Base Address */
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#define GPIOA_BASE (0x40058000U)
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#define GPIOB_BASE (0x40059000U)
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#define GPIOC_BASE (0x4005A000U)
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#define GPIOD_BASE (0x4005B000U)
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#define GPIOE_BASE (0x4005C000U)
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#define GPIOF_BASE (0x4005D000U)
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#define GPIOG_BASE (0x4005E000U)
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#define GPIOH_BASE (0x4005F000U)
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#define GPIOJ_BASE (0x40060000U)
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#define GPIOK_BASE (0x40061000U)
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#define GPIOL_BASE (0x40062000U)
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#define GPIOM_BASE (0x40063000U)
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#define GPION_BASE (0x40064000U)
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#define GPIOP_BASE (0x40065000U)
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#define GPIOQ_BASE (0x40066000U)
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/** General-Purpose Timers Base Address */
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#define TIM0_BASE (0x40030000U)
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#define TIM1_BASE (0x40031000U)
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#define TIM2_BASE (0x40032000U)
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#define TIM3_BASE (0x40033000U)
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#define TIM4_BASE (0x40034000U)
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#define TIM5_BASE (0x40035000U)
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#define TIM6_BASE (0x400E0000U)
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#define TIM7_BASE (0x400E1000U)
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/** Inter-Integrated Circuit Base Address */
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#define I2C0_BASE (0x40020000U)
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#define I2C1_BASE (0x40021000U)
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#define I2C2_BASE (0x40022000U)
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#define I2C3_BASE (0x40023000U)
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#define I2C4_BASE (0x400C0000U)
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#define I2C5_BASE (0x400C1000U)
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#define I2C6_BASE (0x400C2000U)
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#define I2C7_BASE (0x400C3000U)
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#define I2C8_BASE (0x400B8000U)
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#define I2C9_BASE (0x400B9000U)
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/** LCD Controller Base Address */
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#define LCD_BASE (0x44050000U)
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/** Pulse Width Modulator Base Address */
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#define PWM0_BASE (0x40028000U)
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/** 1-Wire Master Module Base Address */
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#define ONEWIRE_BASE (0x400B6000U)
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/** Quad Synchronous Serial Interface Base Address */
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#define SSI0_BASE (0x40008000U)
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#define SSI1_BASE (0x40009000U)
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#define SSI2_BASE (0x4000A000U)
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#define SSI3_BASE (0x4000B000U)
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/** Quadrature Encoder Interface Base Address */
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#define QEI0_BASE (0x4002C000U)
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/** SHA/MD5 Accelerator Base Address */
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#define SHA_BASE (0x44034000U)
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/** Universal Asynchronous Receiver/Transmitter Base Address */
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#define UART0_BASE (0x4000C000U)
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#define UART1_BASE (0x4000D000U)
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#define UART2_BASE (0x4000E000U)
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#define UART3_BASE (0x4000F000U)
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#define UART4_BASE (0x40010000U)
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#define UART5_BASE (0x40011000U)
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#define UART6_BASE (0x40012000U)
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#define UART7_BASE (0x40013000U)
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/** Universal Serial Bus Controller Base Address */
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#define USB_BASE (0x40050000U)
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/** Watchdog Timers Base Address */
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#define WDT0_BASE (0x40000000U)
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#define WDT1_BASE (0x40001000U)
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#endif /* MSP432E4_MEMORYMAP_H */
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/**@}*/
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File diff suppressed because it is too large
Load Diff
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@ -63,6 +63,9 @@
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/* Yes, we use the same interrupt table for both LM3S and LM4F */
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# include "../lm3s/vector_nvic.c"
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#elif defined(MSP432E4)
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# include "../msp432/e4/vector_nvic.c"
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#else
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# warning "no interrupts defined for chipset;"\
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"not allocating space in the vector table"
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@ -0,0 +1,47 @@
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##
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## This file is part of the libopencm3 project.
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##
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## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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## Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me@gmail.com>
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## Copyright (C) 2018 Dmitry Rezvanov <dmitry.rezvanov@yandex.ru>
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##
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## This library is free software: you can redistribute it and/or modify
|
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## it under the terms of the GNU Lesser General Public License as published by
|
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## the Free Software Foundation, either version 3 of the License, or
|
||||
## (at your option) any later version.
|
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##
|
||||
## This library is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU Lesser General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU Lesser General Public License
|
||||
## along with this library. If not, see <http://www.gnu.org/licenses/>.
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##
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LIBNAME = libopencm3_msp432e4
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SRCLIBDIR ?= ../..
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FP_FLAGS ?= -mfloat-abi=hard -mfpu=fpv4-sp-d16
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PREFIX ?= arm-none-eabi
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CC = $(PREFIX)-gcc
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AR = $(PREFIX)-ar
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TGT_CFLAGS = -Os \
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-Wall -Wextra -Wimplicit-function-declaration \
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-Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \
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-Wundef -Wshadow \
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-I../../../include -fno-common \
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-mcpu=cortex-m4 -mthumb $(FP_FLAGS) \
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-Wstrict-prototypes \
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-ffunction-sections -fdata-sections -MD -DMSP432E4
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TGT_CFLAGS += $(DEBUG_FLAGS)
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TGT_CFLAGS += $(STANDARD_FLAGS)
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# ARFLAGS = rcsv
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ARFLAGS = rcs
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OBJS = systemcontrol.o
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VPATH += ../:../../cm3:../common
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include ../../Makefile.include
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@ -0,0 +1,130 @@
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/** @defgroup systemcontrol_file System Control
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*
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* @ingroup MSP432E4xx
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*
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* @brief libopencm3 MSP432E4xx System Control
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*
|
||||
* @version 1.0.0
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*
|
||||
* @date 22 July 2018
|
||||
*
|
||||
* LGPL License Terms @ref lgpl_license
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
|
||||
* Copyright (C) 2018 Dmitry Rezvanov <dmitry.rezvanov@yandex.ru>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <libopencm3/msp432/e4/systemcontrol.h>
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#include <stdbool.h>
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|
||||
#define _SYSCTL_REG(base, i) MMIO32((base) + ((i) >> 5))
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#define _SYSCTL_BIT(i) (1 << ((i) & 0x1f))
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|
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/*----------------------------------------------------------------------------*/
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||||
/** @brief System Control Enable Peripheral Clock
|
||||
*
|
||||
* @param[in] clock_mode ::msp432_clock_mode Clock mode
|
||||
* @param[in] periph ::msp432_periph Peripheral block
|
||||
*/
|
||||
void sysctl_periph_clock_enable(enum msp432_clock_mode clock_mode,
|
||||
enum msp432_periph periph)
|
||||
{
|
||||
_SYSCTL_REG(SYSCTL_BASE + clock_mode, periph) |= _SYSCTL_BIT(periph);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/** @brief System Control Disable Peripheral Clock
|
||||
*
|
||||
* @param[in] clock_mode ::msp432_clock_mode Clock mode
|
||||
* @param[in] periph ::msp432_periph Peripheral block
|
||||
*/
|
||||
void sysctl_periph_clock_disable(enum msp432_clock_mode clock_mode,
|
||||
enum msp432_periph periph)
|
||||
{
|
||||
_SYSCTL_REG(SYSCTL_BASE + clock_mode, periph) &= ~_SYSCTL_BIT(periph);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/** @brief System Control Peripheral Software Reset
|
||||
*
|
||||
* @param[in] periph ::msp432_periph Peripheral block
|
||||
*/
|
||||
void sysctl_periph_reset(enum msp432_periph periph)
|
||||
{
|
||||
_SYSCTL_REG((uint32_t)&SYSCTL_SRWD, periph) |= _SYSCTL_BIT(periph);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/** @brief System Control Peripheral Clear Software Reset
|
||||
*
|
||||
* @param[in] periph ::msp432_periph Peripheral block
|
||||
*/
|
||||
void sysctl_periph_clear_reset(enum msp432_periph periph)
|
||||
{
|
||||
_SYSCTL_REG((uint32_t)&SYSCTL_SRWD, periph) &= ~_SYSCTL_BIT(periph);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/** @brief System Control Peripheral Is Present
|
||||
*
|
||||
* @param[in] periph ::msp432_periph Peripheral block
|
||||
*/
|
||||
bool sysctl_periph_is_present(enum msp432_periph periph)
|
||||
{
|
||||
uint32_t reg32 = _SYSCTL_REG((uint32_t)&SYSCTL_PPWD, periph);
|
||||
uint32_t mask = _SYSCTL_BIT(periph);
|
||||
|
||||
return ((reg32 & mask) != 0);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/** @brief System Control Peripheral Is Ready
|
||||
*
|
||||
* @param[in] periph ::msp432_periph Peripheral block
|
||||
*/
|
||||
bool sysctl_periph_is_ready(enum msp432_periph periph)
|
||||
{
|
||||
uint32_t reg32 = _SYSCTL_REG((uint32_t)&SYSCTL_PRWD, periph);
|
||||
uint32_t mask = _SYSCTL_BIT(periph);
|
||||
|
||||
return ((reg32 & mask) != 0);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/** @brief System Control Peripheral Set Power State
|
||||
*
|
||||
* @param[in] power_mode ::msp432_power_mode Power mode
|
||||
* @param[in] periph ::msp432_periph Peripheral block
|
||||
*
|
||||
* @note If the module is in run, sleep or deep-sleep mode - the module
|
||||
* is powered and receives a clock regardless of the value of power mode.
|
||||
*/
|
||||
void sysctl_periph_set_power_state(enum msp432_power_mode power_mode,
|
||||
enum msp432_periph periph)
|
||||
{
|
||||
if(power_mode == POWER_ENABLE) {
|
||||
_SYSCTL_REG((uint32_t)&SYSCTL_PCWD, periph) |= _SYSCTL_BIT(periph);
|
||||
} else {
|
||||
_SYSCTL_REG((uint32_t)&SYSCTL_PCWD, periph) &= ~_SYSCTL_BIT(periph);
|
||||
}
|
||||
}
|
||||
|
||||
#undef _SYSCTL_REG
|
||||
#undef _SYSCTL_BIT
|
||||
Loading…
Reference in New Issue