doc: stm32l0: rcc: add groupings for periph resets
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@ -262,17 +262,18 @@
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#define RCC_IOPPRSTR_IOPBRST (1<<1)
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#define RCC_IOPPRSTR_IOPARST (1<<0)
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/* --- RCC_AHBRSTR values ------------------------------------------------- */
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/** @defgroup rcc_ahbrstr_rst RCC_AHBRSTR reset values
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@{*/
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#define RCC_AHBRSTR_CRYPRST (1 << 24)
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#define RCC_AHBRSTR_RNGRST (1 << 20)
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#define RCC_AHBRSTR_TSCRST (1 << 16)
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#define RCC_AHBRSTR_CRCRST (1 << 12)
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#define RCC_AHBRSTR_MIFRST (1 << 8)
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#define RCC_AHBRSTR_DMARST (1 << 0)
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/**@}*/
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/* --- RCC_APB2RSTR values ------------------------------------------------- */
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/** @defgroup rcc_apb2rstr_rst RCC_APB2RSTR reset values
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@{*/
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#define RCC_APB2RSTR_DBGRST (1 << 22)
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#define RCC_APB2RSTR_USART1RST (1 << 14)
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#define RCC_APB2RSTR_SPI1RST (1 << 12)
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@ -280,9 +281,10 @@
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#define RCC_APB2RSTR_TIM22RST (1 << 5)
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#define RCC_APB2RSTR_TIM21RST (1 << 2)
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#define RCC_APB2RSTR_SYSCFGRST (1 << 0)
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/**@}*/
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/* --- RCC_APB1RSTR values ------------------------------------------------- */
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/** @defgroup rcc_apb1rstr_rst RCC_APB1RSTR reset values
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@{*/
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#define RCC_APB1RSTR_LPTIM1RST (1 << 31)
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#define RCC_APB1RSTR_I2C3RST (1 << 30)
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#define RCC_APB1RSTR_DACRST (1 << 29)
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@ -302,6 +304,7 @@
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#define RCC_APB1RSTR_TIM6RST (1 << 4)
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#define RCC_APB1RSTR_TIM3RST (1 << 1)
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#define RCC_APB1RSTR_TIM2RST (1 << 0)
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/**@}*/
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/* --- RCC_IOPENR - GPIO clock enable register */
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@ -312,11 +315,7 @@
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#define RCC_IOPENR_IOPBEN (1<<1)
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#define RCC_IOPENR_IOPAEN (1<<0)
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/* --- RCC_AHBENR values --------------------------------------------------- */
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/** @defgroup rcc_ahbenr_en RCC_AHBENR enable values
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@ingroup STM32L0xx_rcc_defines
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/** @defgroup rcc_ahbenr_en RCC_APHBENR enable values
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@{*/
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#define RCC_AHBENR_CRYPEN (1 << 24)
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#define RCC_AHBENR_RNGEN (1 << 20)
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@ -324,13 +323,9 @@
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#define RCC_AHBENR_CRCEN (1 << 12)
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#define RCC_AHBENR_MIFEN (1 << 8)
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#define RCC_AHBENR_DMAEN (1 << 0)
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/*@}*/
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/* --- RCC_APB2ENR values -------------------------------------------------- */
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/** @defgroup rcc_apb2enr_en RCC_APB2ENR enable values
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@ingroup STM32L0xx_rcc_defines
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/**@}*/
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/** @defgroup rcc_apb2enr_en RCC_APPB2ENR enable values
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@{*/
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#define RCC_APB2ENR_DBGEN (1 << 22)
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#define RCC_APB2ENR_USART1EN (1 << 14)
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@ -340,13 +335,9 @@
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#define RCC_APB2ENR_TIM22EN (1 << 5)
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#define RCC_APB2ENR_TIM21EN (1 << 2)
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#define RCC_APB2ENR_SYSCFGEN (1 << 0)
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/*@}*/
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/* --- RCC_APB1ENR values -------------------------------------------------- */
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/**@}*/
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/** @defgroup rcc_apb1enr_en RCC_APB1ENR enable values
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@ingroup STM32L0xx_rcc_defines
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@{*/
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#define RCC_APB1ENR_LPTIM1EN (1 << 31)
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#define RCC_APB1ENR_DACEN (1 << 29)
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@ -366,7 +357,7 @@
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#define RCC_APB1ENR_TIM6EN (1 << 4)
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#define RCC_APB1ENR_TIM3EN (1 << 1)
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#define RCC_APB1ENR_TIM2EN (1 << 0)
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/*@}*/
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/**@}*/
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/* --- RCC_IOPSMENR - GPIO Clock enable in sleep mode */
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