doc: stm32f2: rcc: add groupings for periph resets

We use a parent grouping to make the generic "AHB" groups work, even
though F2 and many later families have AHB1, AHB2 and AHB3
This commit is contained in:
Karl Palsson 2019-06-11 21:49:44 +00:00 committed by Karl Palsson
parent 21a0c1178c
commit da3466057b
1 changed files with 36 additions and 20 deletions

View File

@ -208,8 +208,10 @@
#define RCC_CIR_LSERDYF (1 << 1)
#define RCC_CIR_LSIRDYF (1 << 0)
/* --- RCC_AHB1RSTR values ------------------------------------------------- */
/** @defgroup rcc_ahbrstr_rst RCC_AHBxRSTR reset values (full set)
@{*/
/** @defgroup rcc_ahb1rstr_rst RCC_AHB1RSTR reset values
@{*/
#define RCC_AHB1RSTR_OTGHSRST (1 << 29)
#define RCC_AHB1RSTR_ETHMACRST (1 << 25)
#define RCC_AHB1RSTR_DMA2RST (1 << 22)
@ -224,6 +226,7 @@
#define RCC_AHB1RSTR_GPIOCRST (1 << 2)
#define RCC_AHB1RSTR_GPIOBRST (1 << 1)
#define RCC_AHB1RSTR_GPIOARST (1 << 0)
/**@}*/
/** @addtogroup deprecated_201802_rcc Deprecated 2018
* @deprecated replace zzz_IOPxRST with zzz_GPIOxRST
@ -240,20 +243,23 @@
#define RCC_AHB1RSTR_IOPARST RCC_AHB1RSTR_GPIOARST
/**@}*/
/* --- RCC_AHB2RSTR values ------------------------------------------------- */
/** @defgroup rcc_ahb2rstr_rst RCC_AHB2RSTR reset values
@{*/
#define RCC_AHB2RSTR_OTGFSRST (1 << 7)
#define RCC_AHB2RSTR_RNGRST (1 << 6)
#define RCC_AHB2RSTR_HASHRST (1 << 5)
#define RCC_AHB2RSTR_CRYPRST (1 << 4)
#define RCC_AHB2RSTR_DCMIRST (1 << 0)
/**@}*/
/* --- RCC_AHB3RSTR values ------------------------------------------------- */
/** @defgroup rcc_ahb3rstr_rst RCC_AHB3RSTR reset values
@{*/
#define RCC_AHB3RSTR_FSMCRST (1 << 0)
/**@}*/
/**@}*/
/* --- RCC_APB1RSTR values ------------------------------------------------- */
/** @defgroup rcc_apb1rstr_rst RCC_APB1RSTR reset values
@{*/
#define RCC_APB1RSTR_DACRST (1 << 29)
#define RCC_APB1RSTR_PWRRST (1 << 28)
#define RCC_APB1RSTR_CAN2RST (1 << 26)
@ -277,9 +283,10 @@
#define RCC_APB1RSTR_TIM4RST (1 << 2)
#define RCC_APB1RSTR_TIM3RST (1 << 1)
#define RCC_APB1RSTR_TIM2RST (1 << 0)
/**@}*/
/* --- RCC_APB2RSTR values ------------------------------------------------- */
/** @defgroup rcc_apb2rstr_rst RCC_APB2RSTR reset values
@{*/
#define RCC_APB2RSTR_TIM11RST (1 << 18)
#define RCC_APB2RSTR_TIM10RST (1 << 17)
#define RCC_APB2RSTR_TIM9RST (1 << 16)
@ -291,9 +298,12 @@
#define RCC_APB2RSTR_USART1RST (1 << 4)
#define RCC_APB2RSTR_TIM8RST (1 << 1)
#define RCC_APB2RSTR_TIM1RST (1 << 0)
/**@}*/
/* --- RCC_AHB1ENR values ------------------------------------------------- */
/** @defgroup rcc_ahbenr_en RCC_AHBxENR enable values (full set)
@{*/
/** @defgroup rcc_ahb1enr_en RCC_AHB1ENR enable values
@{*/
#define RCC_AHB1ENR_OTGHSULPIEN (1 << 30)
#define RCC_AHB1ENR_OTGHSEN (1 << 29)
#define RCC_AHB1ENR_ETHMACPTPEN (1 << 28)
@ -313,6 +323,7 @@
#define RCC_AHB1ENR_GPIOCEN (1 << 2)
#define RCC_AHB1ENR_GPIOBEN (1 << 1)
#define RCC_AHB1ENR_GPIOAEN (1 << 0)
/**@}*/
/** @addtogroup deprecated_201802_rcc Deprecated 2018
* @deprecated replace zzz_IOPxEN with zzz_GPIOxEN
@ -329,20 +340,23 @@
#define RCC_AHB1ENR_IOPAEN RCC_AHB1ENR_GPIOAEN
/**@}*/
/* --- RCC_AHB2ENR values ------------------------------------------------- */
/** @defgroup rcc_ahb2enr_en RCC_AHB2ENR enable values
@{*/
#define RCC_AHB2ENR_OTGFSEN (1 << 7)
#define RCC_AHB2ENR_RNGEN (1 << 6)
#define RCC_AHB2ENR_HASHEN (1 << 5)
#define RCC_AHB2ENR_CRYPEN (1 << 4)
#define RCC_AHB2ENR_DCMIEN (1 << 0)
/**@}*/
/* --- RCC_AHB3ENR values ------------------------------------------------- */
/** @defgroup rcc_ahb3enr_en RCC_AHB3ENR enable values
@{*/
#define RCC_AHB3ENR_FSMCEN (1 << 0)
/**@}*/
/**@}*/
/* --- RCC_APB1ENR values ------------------------------------------------- */
/** @defgroup rcc_apb1enr_en RCC_APB1ENR enable values
@{*/
#define RCC_APB1ENR_DACEN (1 << 29)
#define RCC_APB1ENR_PWREN (1 << 28)
#define RCC_APB1ENR_CAN2EN (1 << 26)
@ -366,9 +380,10 @@
#define RCC_APB1ENR_TIM4EN (1 << 2)
#define RCC_APB1ENR_TIM3EN (1 << 1)
#define RCC_APB1ENR_TIM2EN (1 << 0)
/**@}*/
/* --- RCC_APB2ENR values ------------------------------------------------- */
/** @defgroup rcc_apb2enr_en RCC_APB2ENR enable values
@{*/
#define RCC_APB2ENR_TIM11EN (1 << 18)
#define RCC_APB2ENR_TIM10EN (1 << 17)
#define RCC_APB2ENR_TIM9EN (1 << 16)
@ -382,6 +397,7 @@
#define RCC_APB2ENR_USART1EN (1 << 4)
#define RCC_APB2ENR_TIM8EN (1 << 1)
#define RCC_APB2ENR_TIM1EN (1 << 0)
/**@}*/
/* --- RCC_AHB1LPENR values ------------------------------------------------- */