[Style] Global style fix run.
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67efedec54
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@ -156,14 +156,17 @@ static inline bool cm_mask_faults(bool mask)
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#if !defined(__DOXYGEN__)
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/* Do not populate this definition outside */
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static inline bool __cm_atomic_set(bool* val)
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static inline bool __cm_atomic_set(bool *val)
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{
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return cm_mask_interrupts(*val);
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}
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#define __CM_SAVER(state) __val = state, \
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#define __CM_SAVER(state) \
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do { \
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__val = state, \
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__save __attribute__((__cleanup__(__cm_atomic_set))) = \
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__cm_atomic_set(&__val)
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__cm_atomic_set(&__val); \
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} while (0)
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#endif /* !defined(__DOXYGEN) */
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@ -213,8 +216,10 @@ static inline bool __cm_atomic_set(bool* val)
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#if defined(__DOXYGEN__)
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#define CM_ATOMIC_BLOCK()
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#else /* defined(__DOXYGEN__) */
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#define CM_ATOMIC_BLOCK() \
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for (bool ___CM_SAVER(true), __my = true; __my; __my = false)
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#define CM_ATOMIC_BLOCK() \
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do { \
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for (bool ___CM_SAVER(true), __my = true; __my; __my = false); \
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} while (0)
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#endif /* defined(__DOXYGEN__) */
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/*---------------------------------------------------------------------------*/
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@ -32,7 +32,7 @@ void __dmb(void);
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/* --- Exclusive load and store instructions ------------------------------- */
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/* Those are defined only on CM3 or CM4 */
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#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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uint32_t __ldrex(volatile uint32_t *addr);
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uint32_t __strex(uint32_t val, volatile uint32_t *addr);
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@ -749,5 +749,4 @@ END_DECLS
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/**@}*/
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#endif
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@ -684,7 +684,7 @@ typedef struct {
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} sgpio_t;
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/* Global access to SGPIO structure */
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#define SGPIO ((sgpio_t*)SGPIO_PORT_BASE)
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#define SGPIO ((sgpio_t *)SGPIO_PORT_BASE)
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/**@}*/
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@ -622,7 +622,7 @@ injected channels.
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#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQR_JSQ2_LSB)
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#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQR_JSQ1_LSB)
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#define ADC_JSQR_JSQ_VAL(n,val) ((val) << (((n) - 1) * 5))
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#define ADC_JSQR_JSQ_VAL(n, val) ((val) << (((n) - 1) * 5))
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#define ADC_JSQR_JL_VAL(val) (((val) - 1) << ADC_JSQR_JL_SHIFT)
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/* --- ADC_JDRx, ADC_DR values --------------------------------------------- */
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@ -628,7 +628,7 @@
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#define ADC_JSQR_JSQ2_LSB 14
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#define ADC_JSQR_JSQ1_LSB 8
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#define ADC_JSQR_JSQ_VAL(n,val) ((val) << (((n) - 1) * 6 + 8))
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#define ADC_JSQR_JSQ_VAL(n, val) ((val) << (((n) - 1) * 6 + 8))
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#define ADC_JSQR_JL_VAL(val) (((val) - 1) << ADC_JSQR_JL_SHIFT)
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/* Bits 30:26 JSQ4[4:0]: 4th conversion in the injected sequence */
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@ -587,7 +587,7 @@ injected channels.
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#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQR_JSQ2_LSB)
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#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQR_JSQ1_LSB)
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#define ADC_JSQR_JSQ_VAL(n,val) ((val) << (((n) - 1) * 5))
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#define ADC_JSQR_JSQ_VAL(n, val) ((val) << (((n) - 1) * 5))
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#define ADC_JSQR_JL_VAL(val) (((val) - 1) << ADC_JSQR_JL_SHIFT)
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/* --- ADC_JDRx, ADC_DR values --------------------------------------------- */
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@ -530,7 +530,7 @@ enum rcc_periph_clken {
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RCC_TIM12 = _REG_BIT(0x40, 6),
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RCC_TIM13 = _REG_BIT(0x40, 7),
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RCC_TIM14 = _REG_BIT(0x40, 8),
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RCC_WWDG = _REG_BIT(0x40, 11),
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RCC_WWDG = _REG_BIT(0x40, 11),
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RCC_SPI2 = _REG_BIT(0x40, 14),
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RCC_SPI3 = _REG_BIT(0x40, 15),
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RCC_USART2 = _REG_BIT(0x40, 17),
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@ -613,7 +613,7 @@ enum rcc_periph_clken {
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SCC_TIM12 = _REG_BIT(0x60, 6),
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SCC_TIM13 = _REG_BIT(0x60, 7),
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SCC_TIM14 = _REG_BIT(0x60, 8),
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SCC_WWDG = _REG_BIT(0x60, 11),
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SCC_WWDG = _REG_BIT(0x60, 11),
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SCC_SPI2 = _REG_BIT(0x60, 14),
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SCC_SPI3 = _REG_BIT(0x60, 15),
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SCC_USART2 = _REG_BIT(0x60, 17),
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@ -686,7 +686,7 @@ enum rcc_periph_rst {
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RST_TIM12 = _REG_BIT(0x20, 6),
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RST_TIM13 = _REG_BIT(0x20, 7),
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RST_TIM14 = _REG_BIT(0x20, 8),
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RST_WWDG = _REG_BIT(0x20, 11),
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RST_WWDG = _REG_BIT(0x20, 11),
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RST_SPI2 = _REG_BIT(0x20, 14),
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RST_SPI3 = _REG_BIT(0x20, 15),
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RST_USART2 = _REG_BIT(0x20, 17),
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@ -164,7 +164,7 @@ void nvic_set_priority(uint8_t irqn, uint8_t priority)
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}
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/* Those are defined only on CM3 or CM4 */
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#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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/*---------------------------------------------------------------------------*/
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/** @brief NVIC Return Active Interrupt
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*
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@ -22,7 +22,7 @@
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#include <libopencm3/cm3/scb.h>
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/* Those are defined only on CM3 or CM4 */
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#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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void scb_reset_core(void)
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{
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SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_VECTRESET;
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@ -39,7 +39,7 @@ void scb_reset_system(void)
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}
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/* Those are defined only on CM3 or CM4 */
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#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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void scb_set_priority_grouping(uint32_t prigroup)
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{
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SCB_AIRCR = SCB_AIRCR_VECTKEY | prigroup;
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@ -44,7 +44,7 @@ vector_table_t vector_table = {
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.hard_fault = hard_fault_handler,
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/* Those are defined only on CM3 or CM4 */
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#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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.memory_manage_fault = mem_manage_handler,
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.bus_fault = bus_fault_handler,
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.usage_fault = usage_fault_handler,
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@ -112,7 +112,7 @@ void null_handler(void)
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#pragma weak sys_tick_handler = null_handler
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/* Those are defined only on CM3 or CM4 */
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#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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#pragma weak mem_manage_handler = blocking_handler
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#pragma weak bus_fault_handler = blocking_handler
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#pragma weak usage_fault_handler = blocking_handler
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@ -93,7 +93,8 @@ void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset)
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*
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* @param[in] *reg Unsigned int32. Pointer to a Reset Register
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* (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
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* @param[in] clear_reset Unsigned int32. Logical OR of all resets to be removed:
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* @param[in] clear_reset Unsigned int32. Logical OR of all resets to be
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* removed:
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* @li If register is RCC_AHBRSTR, from @ref rcc_ahbrstr_rst
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* @li If register is RCC_APB1RSTR, from @ref rcc_apb1rstr_rst
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* @li If register is RCC_APB2RSTR, from @ref rcc_apb2rstr_rst
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@ -788,7 +788,7 @@ void adc_enable_analog_watchdog_on_all_channels(uint32_t adc)
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void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, uint8_t chan)
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{
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ADC_CFGR1(adc) = (ADC_CFGR1(adc) & ~ADC_CFGR1_AWDCH) | \
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ADC_CFGR1(adc) = (ADC_CFGR1(adc) & ~ADC_CFGR1_AWDCH) |
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ADC_CFGR1_AWDCH_VAL(chan);
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ADC_CFGR1(adc) |= ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL;
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@ -250,7 +250,7 @@ void rcc_osc_on(enum rcc_osc osc)
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RCC_CSR |= RCC_CSR_LSION;
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break;
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case PLL:
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RCC_CR|=RCC_CR_PLLON;
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RCC_CR |= RCC_CR_PLLON;
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break;
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}
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}
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