diff --git a/include/libopencm3/cm3/cortex.h b/include/libopencm3/cm3/cortex.h index c0bdb189..2d6377e7 100644 --- a/include/libopencm3/cm3/cortex.h +++ b/include/libopencm3/cm3/cortex.h @@ -1,277 +1,282 @@ -/** @defgroup CM3_cortex_defines Cortex Core Defines - * - * @brief libopencm3 Defined Constants and Types for the Cortex Core - * - * @ingroup CM3_defines - * - * @version 1.0.0 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Ben Gamari - * Copyright (C) 2013 Frantisek Burian - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#ifndef LIBOPENCM3_CORTEX_H -#define LIBOPENCM3_CORTEX_H - -/**@{*/ - -/*---------------------------------------------------------------------------*/ -/** @brief Cortex M Enable interrupts - * - * Disable the interrupt mask and enable interrupts globally - */ -static inline void cm_enable_interrupts(void) -{ - __asm__("CPSIE I\n"); -} - -/*---------------------------------------------------------------------------*/ -/** @brief Cortex M Disable interrupts - * - * Mask all interrupts globally - */ -static inline void cm_disable_interrupts(void) -{ - __asm__("CPSID I\n"); -} - -/*---------------------------------------------------------------------------*/ -/** @brief Cortex M Enable faults - * - * Disable the HardFault mask and enable fault interrupt globally - */ -static inline void cm_enable_faults(void) -{ - __asm__("CPSIE F\n"); -} - -/*---------------------------------------------------------------------------*/ -/** @brief Cortex M Disable faults - * - * Mask the HardFault interrupt globally - */ -static inline void cm_disable_faults(void) -{ - __asm__("CPSID F\n"); -} - -/*---------------------------------------------------------------------------*/ -/** @brief Cortex M Check if interrupts are masked - * - * Checks, if interrupts are masked (disabled). - * - * @returns true, if interrupts are disabled. - */ -__attribute__((always_inline)) -static inline bool cm_is_masked_interrupts(void) -{ - register uint32_t result; - __asm__ ("MRS %0, PRIMASK" : "=r" (result)); - return result; -} - -/*---------------------------------------------------------------------------*/ -/** @brief Cortex M Check if Fault interrupt is masked - * - * Checks, if HardFault interrupt is masked (disabled). - * - * @returns bool true, if HardFault interrupt is disabled. - */ -__attribute__((always_inline)) -static inline bool cm_is_masked_faults(void) -{ - register uint32_t result; - __asm__ ("MRS %0, FAULTMASK" : "=r" (result)); - return result; -} - -/*---------------------------------------------------------------------------*/ -/** @brief Cortex M Mask interrupts - * - * This function switches the mask of the interrupts. If mask is true, the - * interrupts will be disabled. The result of this function can be used for - * restoring previous state of the mask. - * - * @param[in] mask bool New state of the interrupt mask - * @returns bool old state of the interrupt mask - */ -__attribute__((always_inline)) -static inline bool cm_mask_interrupts(bool mask) -{ - register bool old; - __asm__ __volatile__("MRS %0, PRIMASK" : "=r" (old)); - __asm__ __volatile__("" : : : "memory"); - __asm__ __volatile__("MSR PRIMASK, %0" : : "r" (mask)); - return old; -} - -/*---------------------------------------------------------------------------*/ -/** @brief Cortex M Mask HardFault interrupt - * - * This function switches the mask of the HardFault interrupt. If mask is true, - * the HardFault interrupt will be disabled. The result of this function can be - * used for restoring previous state of the mask. - * - * @param[in] mask bool New state of the HardFault interrupt mask - * @returns bool old state of the HardFault interrupt mask - */ -__attribute__((always_inline)) -static inline bool cm_mask_faults(bool mask) -{ - register bool old; - __asm__ __volatile__ ("MRS %0, FAULTMASK" : "=r" (old)); - __asm__ __volatile__ ("" : : : "memory"); - __asm__ __volatile__ ("MSR FAULTMASK, %0" : : "r" (mask)); - return old; -} - -/**@}*/ - -/*===========================================================================*/ -/** @defgroup CM3_cortex_atomic_defines Cortex Core Atomic support Defines - * - * @brief Atomic operation support - * - * @ingroup CM3_cortex_defines - */ -/**@{*/ - -#if !defined(__DOXYGEN__) -/* Do not populate this definition outside */ -static inline bool __cm_atomic_set(bool* val) -{ - return cm_mask_interrupts(*val); -} - -#define __CM_SAVER(state) __val = state, \ - __save __attribute__((__cleanup__(__cm_atomic_set))) = \ - __cm_atomic_set(&__val) - -#endif /* !defined(__DOXYGEN) */ - - -/*---------------------------------------------------------------------------*/ -/** @brief Cortex M Atomic Declare block - * - * This macro disables interrupts for the next command or block of code. The - * interrupt mask is automatically restored after exit of the boundary of the - * code block. Therefore restore of interrupt is done automatically after call - * of return or goto control sentence jumping outside of the block. - * - * @warning The usage of sentences break or continue is prohibited in the block - * due to implementation of this macro! - * - * @note It is safe to use this block inside normal code and in interrupt - * routine. - * - * @example 1: Basic usage of atomic block - * - * @code - * uint64_t value; // This value is used somewhere in interrupt - * - * ... - * - * CM_ATOMIC_BLOCK() { // interrupts are masked in this block - * value = value * 1024 + 651; // access value as atomic - * } // interrupts is restored automatically - * @endcode - * - * @example 2: Use of return inside block: - * - * @code - * uint64_t value; // This value is used somewhere in interrupt - * - * ... - * - * uint64_t allocval(void) - * { - * CM_ATOMIC_BLOCK() { // interrupts are masked in this block - * value = value * 1024 + 651; // do long atomic operation - * return value; // interrupts is restored automatically - * } - * } - * @endcode - */ -#if defined(__DOXYGEN__) -#define CM_ATOMIC_BLOCK() -#else /* defined(__DOXYGEN__) */ -#define CM_ATOMIC_BLOCK() \ - for (bool ___CM_SAVER(true), __my = true; __my; __my = false) -#endif /* defined(__DOXYGEN__) */ - -/*---------------------------------------------------------------------------*/ -/** @brief Cortex M Atomic Declare context - * - * This macro disables interrupts in the current block of code from the place - * where it is defined to the end of the block. The interrupt mask is - * automatically restored after exit of the boundary of the code block. - * Therefore restore of interrupt is done automatically after call of return, - * continue, break, or goto control sentence jumping outside of the block. - * - * @note This function is intended for use in for- cycles to enable the use of - * break and contine sentences inside the block, and for securing the atomic - * reader-like functions. - * - * @note It is safe to use this block inside normal code and in interrupt - * routine. - * - * @example 1: Basic usage of atomic context - * - * @code - * uint64_t value; // This value is used somewhere in interrupt - * - * ... - * - * for (int i=0;i < 100; i++) { - * CM_ATOMIC_CONTEXT(); // interrupts are masked in this block - * value += 100; // access value as atomic - * if ((value % 16) == 0) { - * break; // restore interrupts and break cycle - * } - * } // interrupts is restored automatically - * @endcode - * - * @example 2: Usage of atomic context inside atomic reader fcn. - * - * @code - * uint64_t value; // This value is used somewhere in interrupt - * - * ... - * - * uint64_t getnextval(void) - * { - * CM_ATOMIC_CONTEXT(); // interrupts are masked in this block - * value = value + 3; // do long atomic operation - * return value; // interrupts is restored automatically - * } - * @endcode - */ -#if defined(__DOXYGEN__) -#define CM_ATOMIC_CONTEXT() -#else /* defined(__DOXYGEN__) */ -#define CM_ATOMIC_CONTEXT() bool __CM_SAVER(true) -#endif /* defined(__DOXYGEN__) */ - -/**@}*/ - - - -#endif +/** @defgroup CM3_cortex_defines Cortex Core Defines + * + * @brief libopencm3 Defined Constants and Types for the Cortex Core + * + * @ingroup CM3_defines + * + * @version 1.0.0 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Ben Gamari + * Copyright (C) 2013 Frantisek Burian + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_CORTEX_H +#define LIBOPENCM3_CORTEX_H + +/**@{*/ + +/*---------------------------------------------------------------------------*/ +/** @brief Cortex M Enable interrupts + * + * Disable the interrupt mask and enable interrupts globally + */ +static inline void cm_enable_interrupts(void) +{ + __asm__("CPSIE I\n"); +} + +/*---------------------------------------------------------------------------*/ +/** @brief Cortex M Disable interrupts + * + * Mask all interrupts globally + */ +static inline void cm_disable_interrupts(void) +{ + __asm__("CPSID I\n"); +} + +/*---------------------------------------------------------------------------*/ +/** @brief Cortex M Enable faults + * + * Disable the HardFault mask and enable fault interrupt globally + */ +static inline void cm_enable_faults(void) +{ + __asm__("CPSIE F\n"); +} + +/*---------------------------------------------------------------------------*/ +/** @brief Cortex M Disable faults + * + * Mask the HardFault interrupt globally + */ +static inline void cm_disable_faults(void) +{ + __asm__("CPSID F\n"); +} + +/*---------------------------------------------------------------------------*/ +/** @brief Cortex M Check if interrupts are masked + * + * Checks, if interrupts are masked (disabled). + * + * @returns true, if interrupts are disabled. + */ +__attribute__((always_inline)) +static inline bool cm_is_masked_interrupts(void) +{ + register uint32_t result; + __asm__ ("MRS %0, PRIMASK" : "=r" (result)); + return result; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Cortex M Check if Fault interrupt is masked + * + * Checks, if HardFault interrupt is masked (disabled). + * + * @returns bool true, if HardFault interrupt is disabled. + */ +__attribute__((always_inline)) +static inline bool cm_is_masked_faults(void) +{ + register uint32_t result; + __asm__ ("MRS %0, FAULTMASK" : "=r" (result)); + return result; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Cortex M Mask interrupts + * + * This function switches the mask of the interrupts. If mask is true, the + * interrupts will be disabled. The result of this function can be used for + * restoring previous state of the mask. + * + * @param[in] mask bool New state of the interrupt mask + * @returns bool old state of the interrupt mask + */ +__attribute__((always_inline)) +static inline bool cm_mask_interrupts(bool mask) +{ + register bool old; + __asm__ __volatile__("MRS %0, PRIMASK" : "=r" (old)); + __asm__ __volatile__("" : : : "memory"); + __asm__ __volatile__("MSR PRIMASK, %0" : : "r" (mask)); + return old; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Cortex M Mask HardFault interrupt + * + * This function switches the mask of the HardFault interrupt. If mask is true, + * the HardFault interrupt will be disabled. The result of this function can be + * used for restoring previous state of the mask. + * + * @param[in] mask bool New state of the HardFault interrupt mask + * @returns bool old state of the HardFault interrupt mask + */ +__attribute__((always_inline)) +static inline bool cm_mask_faults(bool mask) +{ + register bool old; + __asm__ __volatile__ ("MRS %0, FAULTMASK" : "=r" (old)); + __asm__ __volatile__ ("" : : : "memory"); + __asm__ __volatile__ ("MSR FAULTMASK, %0" : : "r" (mask)); + return old; +} + +/**@}*/ + +/*===========================================================================*/ +/** @defgroup CM3_cortex_atomic_defines Cortex Core Atomic support Defines + * + * @brief Atomic operation support + * + * @ingroup CM3_cortex_defines + */ +/**@{*/ + +#if !defined(__DOXYGEN__) +/* Do not populate this definition outside */ +static inline bool __cm_atomic_set(bool *val) +{ + return cm_mask_interrupts(*val); +} + +#define __CM_SAVER(state) \ +do { \ + __val = state, \ + __save __attribute__((__cleanup__(__cm_atomic_set))) = \ + __cm_atomic_set(&__val); \ +} while (0) + +#endif /* !defined(__DOXYGEN) */ + + +/*---------------------------------------------------------------------------*/ +/** @brief Cortex M Atomic Declare block + * + * This macro disables interrupts for the next command or block of code. The + * interrupt mask is automatically restored after exit of the boundary of the + * code block. Therefore restore of interrupt is done automatically after call + * of return or goto control sentence jumping outside of the block. + * + * @warning The usage of sentences break or continue is prohibited in the block + * due to implementation of this macro! + * + * @note It is safe to use this block inside normal code and in interrupt + * routine. + * + * @example 1: Basic usage of atomic block + * + * @code + * uint64_t value; // This value is used somewhere in interrupt + * + * ... + * + * CM_ATOMIC_BLOCK() { // interrupts are masked in this block + * value = value * 1024 + 651; // access value as atomic + * } // interrupts is restored automatically + * @endcode + * + * @example 2: Use of return inside block: + * + * @code + * uint64_t value; // This value is used somewhere in interrupt + * + * ... + * + * uint64_t allocval(void) + * { + * CM_ATOMIC_BLOCK() { // interrupts are masked in this block + * value = value * 1024 + 651; // do long atomic operation + * return value; // interrupts is restored automatically + * } + * } + * @endcode + */ +#if defined(__DOXYGEN__) +#define CM_ATOMIC_BLOCK() +#else /* defined(__DOXYGEN__) */ +#define CM_ATOMIC_BLOCK() \ +do { \ + for (bool ___CM_SAVER(true), __my = true; __my; __my = false); \ +} while (0) +#endif /* defined(__DOXYGEN__) */ + +/*---------------------------------------------------------------------------*/ +/** @brief Cortex M Atomic Declare context + * + * This macro disables interrupts in the current block of code from the place + * where it is defined to the end of the block. The interrupt mask is + * automatically restored after exit of the boundary of the code block. + * Therefore restore of interrupt is done automatically after call of return, + * continue, break, or goto control sentence jumping outside of the block. + * + * @note This function is intended for use in for- cycles to enable the use of + * break and contine sentences inside the block, and for securing the atomic + * reader-like functions. + * + * @note It is safe to use this block inside normal code and in interrupt + * routine. + * + * @example 1: Basic usage of atomic context + * + * @code + * uint64_t value; // This value is used somewhere in interrupt + * + * ... + * + * for (int i=0;i < 100; i++) { + * CM_ATOMIC_CONTEXT(); // interrupts are masked in this block + * value += 100; // access value as atomic + * if ((value % 16) == 0) { + * break; // restore interrupts and break cycle + * } + * } // interrupts is restored automatically + * @endcode + * + * @example 2: Usage of atomic context inside atomic reader fcn. + * + * @code + * uint64_t value; // This value is used somewhere in interrupt + * + * ... + * + * uint64_t getnextval(void) + * { + * CM_ATOMIC_CONTEXT(); // interrupts are masked in this block + * value = value + 3; // do long atomic operation + * return value; // interrupts is restored automatically + * } + * @endcode + */ +#if defined(__DOXYGEN__) +#define CM_ATOMIC_CONTEXT() +#else /* defined(__DOXYGEN__) */ +#define CM_ATOMIC_CONTEXT() bool __CM_SAVER(true) +#endif /* defined(__DOXYGEN__) */ + +/**@}*/ + + + +#endif diff --git a/include/libopencm3/cm3/sync.h b/include/libopencm3/cm3/sync.h index 3ee96f97..e80e3485 100644 --- a/include/libopencm3/cm3/sync.h +++ b/include/libopencm3/cm3/sync.h @@ -32,7 +32,7 @@ void __dmb(void); /* --- Exclusive load and store instructions ------------------------------- */ /* Those are defined only on CM3 or CM4 */ -#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) uint32_t __ldrex(volatile uint32_t *addr); uint32_t __strex(uint32_t val, volatile uint32_t *addr); diff --git a/include/libopencm3/ethernet/mac.h b/include/libopencm3/ethernet/mac.h index 26580577..b047e4db 100644 --- a/include/libopencm3/ethernet/mac.h +++ b/include/libopencm3/ethernet/mac.h @@ -1,46 +1,46 @@ -/** @defgroup ethernet_mac_defines MAC Generic Defines - * - * @brief Defined Constants and Types for the Ethernet MAC - * - * @ingroup ETH - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2013 Frantisek Burian - * - * @date 1 September 2013 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Frantisek Burian - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -/**@{*/ - -#if defined(STM32F1) -# include -#elif defined(STM32F4) -# include -#else -# error "stm32 family not defined." -#endif - -/**@}*/ - - +/** @defgroup ethernet_mac_defines MAC Generic Defines + * + * @brief Defined Constants and Types for the Ethernet MAC + * + * @ingroup ETH + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2013 Frantisek Burian + * + * @date 1 September 2013 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Frantisek Burian + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +#if defined(STM32F1) +# include +#elif defined(STM32F4) +# include +#else +# error "stm32 family not defined." +#endif + +/**@}*/ + + diff --git a/include/libopencm3/ethernet/mac_stm32fxx7.h b/include/libopencm3/ethernet/mac_stm32fxx7.h index b70a49a4..a14a9111 100644 --- a/include/libopencm3/ethernet/mac_stm32fxx7.h +++ b/include/libopencm3/ethernet/mac_stm32fxx7.h @@ -1,6 +1,6 @@ /** @defgroup ethernet_mac_stm32fxx7_defines MAC STM32Fxx7 Defines * - * @brief Defined Constants and Types for the Ethernet MAC for STM32Fxx7 + * @brief Defined Constants and Types for the Ethernet MAC for STM32Fxx7 * chips * * @ingroup ETH @@ -12,10 +12,10 @@ * @date 1 September 2013 * * LGPL License Terms @ref lgpl_license - */ + */ /* - * This file is part of the libopencm3 project. - * + * This file is part of the libopencm3 project. + * * Copyright (C) 2013 Frantisek Burian * * This library is free software: you can redistribute it and/or modify @@ -36,8 +36,8 @@ #define LIBOPENCM3_ETHERNET_H #include -#include - +#include + /**@{*/ /* Ethernet MAC registers */ @@ -746,8 +746,7 @@ END_DECLS * for (;;) * eth_tx(frame,sizeof(frame)); */ - + /**@}*/ - #endif diff --git a/include/libopencm3/ethernet/phy.h b/include/libopencm3/ethernet/phy.h index d08696c7..325695cb 100644 --- a/include/libopencm3/ethernet/phy.h +++ b/include/libopencm3/ethernet/phy.h @@ -11,10 +11,10 @@ * @date 1 September 2013 * * LGPL License Terms @ref lgpl_license - */ + */ /* - * This file is part of the libopencm3 project. - * + * This file is part of the libopencm3 project. + * * Copyright (C) 2013 Frantisek Burian * * This library is free software: you can redistribute it and/or modify @@ -29,12 +29,12 @@ * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . - */ + */ #ifndef LIBOPENCM3_PHY_H #define LIBOPENCM3_PHY_H -#include - +#include + /**@{*/ /* Registers */ @@ -83,8 +83,8 @@ bool phy_link_isup(void); enum phy_status phy_link_status(void); void phy_autoneg_force(enum phy_status mode); -void phy_autoneg_enable(void); - +void phy_autoneg_enable(void); + /**@}*/ diff --git a/include/libopencm3/ethernet/phy_ksz8051mll.h b/include/libopencm3/ethernet/phy_ksz8051mll.h index ad37da1c..a7f9865e 100644 --- a/include/libopencm3/ethernet/phy_ksz8051mll.h +++ b/include/libopencm3/ethernet/phy_ksz8051mll.h @@ -1,6 +1,6 @@ /** @defgroup ethernet_phy_ksz8051mll_defines PHY KSZ8051mll Defines * - * @brief Defined Constants and Types for the Ethernet PHY KSZ8051mll + * @brief Defined Constants and Types for the Ethernet PHY KSZ8051mll * chips * * @ingroup ETH @@ -12,10 +12,10 @@ * @date 1 September 2013 * * LGPL License Terms @ref lgpl_license - */ + */ /* - * This file is part of the libopencm3 project. - * + * This file is part of the libopencm3 project. + * * Copyright (C) 2013 Frantisek Burian * * This library is free software: you can redistribute it and/or modify @@ -30,13 +30,13 @@ * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . - */ - + */ + #ifndef LIBOPENCM3_PHY_KSZ8051MLL_H #define LIBOPENCM3_PHY_KSZ8051MLL_H #include - + /**@{*/ /* Registers */ @@ -52,8 +52,8 @@ #define PHY_REG_LINKMD 0x1D #define PHY_REG_CR1 0x1E -#define PHY_REG_CR2 0x1E - +#define PHY_REG_CR2 0x1E + /**@}*/ diff --git a/include/libopencm3/lpc43xx/sgpio.h b/include/libopencm3/lpc43xx/sgpio.h index 3bff7e3b..e8be60c9 100644 --- a/include/libopencm3/lpc43xx/sgpio.h +++ b/include/libopencm3/lpc43xx/sgpio.h @@ -483,7 +483,7 @@ LGPL License Terms @ref lgpl_license #define SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE_SHIFT (3) #define SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE_MASK \ (0x3 << SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE(x) +#define SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE(x) ((x) << SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE_SHIFT) /* QUALIFIER_MODE: Select qualifier mode */ @@ -684,7 +684,7 @@ typedef struct { } sgpio_t; /* Global access to SGPIO structure */ -#define SGPIO ((sgpio_t*)SGPIO_PORT_BASE) +#define SGPIO ((sgpio_t *)SGPIO_PORT_BASE) /**@}*/ diff --git a/include/libopencm3/stm32/common/rcc_common_all.h b/include/libopencm3/stm32/common/rcc_common_all.h index 43ea2ea2..7892683d 100644 --- a/include/libopencm3/stm32/common/rcc_common_all.h +++ b/include/libopencm3/stm32/common/rcc_common_all.h @@ -29,7 +29,7 @@ #ifndef LIBOPENCM3_RCC_COMMON_ALL_H #define LIBOPENCM3_RCC_COMMON_ALL_H - + BEGIN_DECLS void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en); diff --git a/include/libopencm3/stm32/f1/adc.h b/include/libopencm3/stm32/f1/adc.h index 4858734d..d51839ef 100644 --- a/include/libopencm3/stm32/f1/adc.h +++ b/include/libopencm3/stm32/f1/adc.h @@ -622,7 +622,7 @@ injected channels. #define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQR_JSQ2_LSB) #define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQR_JSQ1_LSB) -#define ADC_JSQR_JSQ_VAL(n,val) ((val) << (((n) - 1) * 5)) +#define ADC_JSQR_JSQ_VAL(n, val) ((val) << (((n) - 1) * 5)) #define ADC_JSQR_JL_VAL(val) (((val) - 1) << ADC_JSQR_JL_SHIFT) /* --- ADC_JDRx, ADC_DR values --------------------------------------------- */ diff --git a/include/libopencm3/stm32/f1/rcc.h b/include/libopencm3/stm32/f1/rcc.h index 514e2fd2..da4f959a 100644 --- a/include/libopencm3/stm32/f1/rcc.h +++ b/include/libopencm3/stm32/f1/rcc.h @@ -519,7 +519,7 @@ enum rcc_periph_clken { RCC_ETHMAC = _REG_BIT(0x14, 14),/*--C*/ RCC_ETHMACTX = _REG_BIT(0x14, 15),/*--C*/ RCC_ETHMACRX = _REG_BIT(0x14, 16),/*--C*/ - + /* APB2 peripherals */ RCC_AFIO = _REG_BIT(0x18, 0),/*VNC*/ RCC_GPIOA = _REG_BIT(0x18, 2),/*VNC*/ @@ -542,7 +542,7 @@ enum rcc_periph_clken { RCC_TIM9 = _REG_BIT(0x18, 19),/*-N-*/ RCC_TIM10 = _REG_BIT(0x18, 20),/*-N-*/ RCC_TIM11 = _REG_BIT(0x18, 21),/*-N-*/ - + /* APB1 peripherals */ RCC_TIM2 = _REG_BIT(0x1C, 0),/*VNC*/ RCC_TIM3 = _REG_BIT(0x1C, 1),/*VNC*/ @@ -600,7 +600,7 @@ enum rcc_periph_rst { RST_TIM9 = _REG_BIT(0x0c, 19),/*-N-*/ RST_TIM10 = _REG_BIT(0x0c, 20),/*-N-*/ RST_TIM11 = _REG_BIT(0x0c, 21),/*-N-*/ - + /* APB1 peripherals */ RST_TIM2 = _REG_BIT(0x10, 0),/*VNC*/ RST_TIM3 = _REG_BIT(0x10, 1),/*VNC*/ diff --git a/include/libopencm3/stm32/f3/adc.h b/include/libopencm3/stm32/f3/adc.h index 6ead9176..88cae818 100644 --- a/include/libopencm3/stm32/f3/adc.h +++ b/include/libopencm3/stm32/f3/adc.h @@ -628,7 +628,7 @@ #define ADC_JSQR_JSQ2_LSB 14 #define ADC_JSQR_JSQ1_LSB 8 -#define ADC_JSQR_JSQ_VAL(n,val) ((val) << (((n) - 1) * 6 + 8)) +#define ADC_JSQR_JSQ_VAL(n, val) ((val) << (((n) - 1) * 6 + 8)) #define ADC_JSQR_JL_VAL(val) (((val) - 1) << ADC_JSQR_JL_SHIFT) /* Bits 30:26 JSQ4[4:0]: 4th conversion in the injected sequence */ diff --git a/include/libopencm3/stm32/f4/adc.h b/include/libopencm3/stm32/f4/adc.h index 23a8d753..aa382637 100644 --- a/include/libopencm3/stm32/f4/adc.h +++ b/include/libopencm3/stm32/f4/adc.h @@ -587,7 +587,7 @@ injected channels. #define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQR_JSQ2_LSB) #define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQR_JSQ1_LSB) -#define ADC_JSQR_JSQ_VAL(n,val) ((val) << (((n) - 1) * 5)) +#define ADC_JSQR_JSQ_VAL(n, val) ((val) << (((n) - 1) * 5)) #define ADC_JSQR_JL_VAL(val) (((val) - 1) << ADC_JSQR_JL_SHIFT) /* --- ADC_JDRx, ADC_DR values --------------------------------------------- */ diff --git a/include/libopencm3/stm32/f4/rcc.h b/include/libopencm3/stm32/f4/rcc.h index 6094f9b7..38d9f12f 100644 --- a/include/libopencm3/stm32/f4/rcc.h +++ b/include/libopencm3/stm32/f4/rcc.h @@ -530,7 +530,7 @@ enum rcc_periph_clken { RCC_TIM12 = _REG_BIT(0x40, 6), RCC_TIM13 = _REG_BIT(0x40, 7), RCC_TIM14 = _REG_BIT(0x40, 8), - RCC_WWDG = _REG_BIT(0x40, 11), + RCC_WWDG = _REG_BIT(0x40, 11), RCC_SPI2 = _REG_BIT(0x40, 14), RCC_SPI3 = _REG_BIT(0x40, 15), RCC_USART2 = _REG_BIT(0x40, 17), @@ -613,7 +613,7 @@ enum rcc_periph_clken { SCC_TIM12 = _REG_BIT(0x60, 6), SCC_TIM13 = _REG_BIT(0x60, 7), SCC_TIM14 = _REG_BIT(0x60, 8), - SCC_WWDG = _REG_BIT(0x60, 11), + SCC_WWDG = _REG_BIT(0x60, 11), SCC_SPI2 = _REG_BIT(0x60, 14), SCC_SPI3 = _REG_BIT(0x60, 15), SCC_USART2 = _REG_BIT(0x60, 17), @@ -686,7 +686,7 @@ enum rcc_periph_rst { RST_TIM12 = _REG_BIT(0x20, 6), RST_TIM13 = _REG_BIT(0x20, 7), RST_TIM14 = _REG_BIT(0x20, 8), - RST_WWDG = _REG_BIT(0x20, 11), + RST_WWDG = _REG_BIT(0x20, 11), RST_SPI2 = _REG_BIT(0x20, 14), RST_SPI3 = _REG_BIT(0x20, 15), RST_USART2 = _REG_BIT(0x20, 17), diff --git a/include/libopencm3/stm32/l1/rcc.h b/include/libopencm3/stm32/l1/rcc.h index 72a245bb..49017d43 100644 --- a/include/libopencm3/stm32/l1/rcc.h +++ b/include/libopencm3/stm32/l1/rcc.h @@ -439,7 +439,7 @@ enum rcc_periph_clken { RCC_DMA2 = _REG_BIT(0x1c, 25), RCC_AES = _REG_BIT(0x1c, 27), RCC_FSMC = _REG_BIT(0x1c, 30), - + /* APB2 peripherals */ RCC_SYSCFG = _REG_BIT(0x20, 0), RCC_TIM9 = _REG_BIT(0x20, 2), @@ -488,7 +488,7 @@ enum rcc_periph_clken { SCC_DMA2 = _REG_BIT(0x28, 25), SCC_AES = _REG_BIT(0x28, 27), SCC_FSMC = _REG_BIT(0x28, 30), - + /* APB2 peripherals */ SCC_SYSCFG = _REG_BIT(0x2c, 0), SCC_TIM9 = _REG_BIT(0x2c, 2), @@ -538,7 +538,7 @@ enum rcc_periph_rst { RST_DMA2 = _REG_BIT(0x10, 25), RST_AES = _REG_BIT(0x10, 27), RST_FSMC = _REG_BIT(0x10, 30), - + /* APB2 peripherals */ RST_SYSCFG = _REG_BIT(0x14, 0), RST_TIM9 = _REG_BIT(0x14, 2), diff --git a/lib/cm3/dwt.c b/lib/cm3/dwt.c index 5f31235b..fe7c2611 100644 --- a/lib/cm3/dwt.c +++ b/lib/cm3/dwt.c @@ -37,7 +37,7 @@ bool dwt_enable_cycle_counter(void) #if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) /* Note TRCENA is for 7M and above*/ - SCS_DEMCR |= SCS_DEMCR_TRCENA; + SCS_DEMCR |= SCS_DEMCR_TRCENA; if (DWT_CTRL & DWT_CTRL_NOCYCCNT) { return false; /* Not supported in implementation */ } diff --git a/lib/cm3/nvic.c b/lib/cm3/nvic.c index e40e7872..6c2188a8 100644 --- a/lib/cm3/nvic.c +++ b/lib/cm3/nvic.c @@ -164,7 +164,7 @@ void nvic_set_priority(uint8_t irqn, uint8_t priority) } /* Those are defined only on CM3 or CM4 */ -#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) /*---------------------------------------------------------------------------*/ /** @brief NVIC Return Active Interrupt * diff --git a/lib/cm3/scb.c b/lib/cm3/scb.c index e51e1450..8c5a2f3a 100644 --- a/lib/cm3/scb.c +++ b/lib/cm3/scb.c @@ -22,7 +22,7 @@ #include /* Those are defined only on CM3 or CM4 */ -#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) void scb_reset_core(void) { SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_VECTRESET; @@ -39,7 +39,7 @@ void scb_reset_system(void) } /* Those are defined only on CM3 or CM4 */ -#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) void scb_set_priority_grouping(uint32_t prigroup) { SCB_AIRCR = SCB_AIRCR_VECTKEY | prigroup; diff --git a/lib/cm3/vector.c b/lib/cm3/vector.c index f73402a9..4523d31d 100644 --- a/lib/cm3/vector.c +++ b/lib/cm3/vector.c @@ -44,7 +44,7 @@ vector_table_t vector_table = { .hard_fault = hard_fault_handler, /* Those are defined only on CM3 or CM4 */ -#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) .memory_manage_fault = mem_manage_handler, .bus_fault = bus_fault_handler, .usage_fault = usage_fault_handler, @@ -112,7 +112,7 @@ void null_handler(void) #pragma weak sys_tick_handler = null_handler /* Those are defined only on CM3 or CM4 */ -#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) #pragma weak mem_manage_handler = blocking_handler #pragma weak bus_fault_handler = blocking_handler #pragma weak usage_fault_handler = blocking_handler diff --git a/lib/ethernet/mac_stm32fxx7.c b/lib/ethernet/mac_stm32fxx7.c index 67623983..16f76a84 100644 --- a/lib/ethernet/mac_stm32fxx7.c +++ b/lib/ethernet/mac_stm32fxx7.c @@ -1,378 +1,378 @@ -/** @defgroup ethernet_mac_stm32fxx7_file MAC STM32Fxx7 - * - * @ingroup ETH - * - * @brief Ethernet MAC STM32Fxx7 Drivers - * - * @version 1.0.0 - * @author @htmlonly © @endhtmlonly 2013 Frantisek Burian - * - * @date 1 September 2013 - * - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Frantisek Burian - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include -#include -#include -#include - -/**@{*/ - -uint32_t TxBD; -uint32_t RxBD; - -/*---------------------------------------------------------------------------*/ -/** @brief Set MAC to the PHY - * - * @param[in] mac uint8_t* Desired MAC - */ -void eth_set_mac(uint8_t *mac) -{ - ETH_MACAHR(0) = ((uint32_t)mac[5] << 8) | (uint32_t)mac[4] | - ETH_MACA0HR_MACA0H; - ETH_MACALR(0) = ((uint32_t)mac[3] << 24) | ((uint32_t)mac[2] << 16) | - ((uint32_t)mac[1] << 8) | mac[0]; -} - -/*---------------------------------------------------------------------------*/ -/** @brief Initialize descriptors - * - * @param[in] buf uint8_t* Buffer for the descriptors - * @param[in] nTx uint32_t Count of Transmit Descriptors - * @param[in] nRx uint32_t Count of Receive Descriptors - * @param[in] cTx uint32_t Bytes in each Transmit Descriptor - * @param[in] cRx uint32_t Bytes in each Receive Descriptor - * @param[in] isext bool true, if extended descriptors should be used - */ -void eth_desc_init(uint8_t *buf, uint32_t nTx, uint32_t nRx, uint32_t cTx, - uint32_t cRx, bool isext) -{ - memset(buf, 0, nTx * cTx + nRx * cRx); - - uint32_t bd = (uint32_t)buf; - uint32_t sz = isext ? ETH_DES_EXT_SIZE : ETH_DES_STD_SIZE; - - /* enable / disable extended frames */ - if (isext) { - ETH_DMABMR |= ETH_DMABMR_EDFE; - } else { - ETH_DMABMR &= ~ETH_DMABMR_EDFE; - } - - TxBD = bd; - while (--nTx > 0) { - ETH_DES0(bd) = ETH_TDES0_TCH; - ETH_DES2(bd) = bd + sz; - ETH_DES3(bd) = bd + sz + cTx; - bd = ETH_DES3(bd); - } - - ETH_DES0(bd) = ETH_TDES0_TCH; - ETH_DES2(bd) = bd + sz; - ETH_DES3(bd) = TxBD; - bd += sz + cTx; - - RxBD = bd; - while (--nRx > 0) { - ETH_DES0(bd) = ETH_RDES0_OWN; - ETH_DES1(bd) = ETH_RDES1_RCH | cRx; - ETH_DES2(bd) = bd + sz; - ETH_DES3(bd) = bd + sz + cRx; - bd = ETH_DES3(bd); - } - - ETH_DES0(bd) = ETH_RDES0_OWN; - ETH_DES1(bd) = ETH_RDES1_RCH | cRx; - ETH_DES2(bd) = bd + sz; - ETH_DES3(bd) = RxBD; - - ETH_DMARDLAR = (uint32_t) RxBD; - ETH_DMATDLAR = (uint32_t) TxBD; -} - -/*---------------------------------------------------------------------------*/ -/** @brief Transmit packet - * - * @param[in] ppkt uint8_t* Pointer to the beginning of the packet - * @param[in] n uint32_t Size of the packet - * @returns bool true, if success - */ -bool eth_tx(uint8_t *ppkt, uint32_t n) -{ - if (ETH_DES0(TxBD) & ETH_TDES0_OWN) { - return false; - } - - memcpy((void *)ETH_DES2(TxBD), ppkt, n); - - ETH_DES1(TxBD) = n & ETH_TDES1_TBS1; - ETH_DES0(TxBD) |= ETH_TDES0_LS | ETH_TDES0_FS | ETH_TDES0_OWN; - TxBD = ETH_DES3(TxBD); - - if (ETH_DMASR & ETH_DMASR_TBUS) { - ETH_DMASR = ETH_DMASR_TBUS; - ETH_DMATPDR = 0; - } - - return true; -} - -/*---------------------------------------------------------------------------*/ -/** @brief Receive packet - * - * @param[inout] ppkt uint8_t* Pointer to the data buffer where to store data - * @param[inout] len uint32_t* Pointer to the variable with the packet length - * @param[in] maxlen uint32_t Maximum length of the packet - * @returns bool true, if the buffer contains readed packet data - */ -bool eth_rx(uint8_t *ppkt, uint32_t *len, uint32_t maxlen) -{ - bool fs = false; - bool ls = false; - bool overrun = false; - uint32_t l = 0; - - while (!(ETH_DES0(RxBD) & ETH_RDES0_OWN) && !ls) { - l = (ETH_DES0(RxBD) & ETH_RDES0_FL) >> ETH_RDES0_FL_SHIFT; - - fs |= ETH_DES0(RxBD) & ETH_RDES0_FS; - ls |= ETH_DES0(RxBD) & ETH_RDES0_LS; - /* frame buffer overrun ?*/ - overrun |= fs && (maxlen < l); - - if (fs && !overrun) { - memcpy(ppkt, (void *)ETH_DES2(RxBD), l); - ppkt += l; - *len += l; - maxlen -= l; - } - - ETH_DES0(RxBD) = ETH_RDES0_OWN; - RxBD = ETH_DES3(RxBD); - } - - if (ETH_DMASR & ETH_DMASR_RBUS) { - ETH_DMASR = ETH_DMASR_RBUS; - ETH_DMARPDR = 0; - } - - return fs && ls && !overrun; -} - -/*---------------------------------------------------------------------------*/ -/** @brief Start the Ethernet DMA processing - */ -void eth_start(void) -{ - ETH_MACCR |= ETH_MACCR_TE; - ETH_DMAOMR |= ETH_DMAOMR_FTF; - ETH_MACCR |= ETH_MACCR_RE; - - ETH_DMAOMR |= ETH_DMAOMR_ST; - ETH_DMAOMR |= ETH_DMAOMR_SR; -} - -/*---------------------------------------------------------------------------*/ -/** @brief Initialize ethernet - * - * This function will initialize ethernet, set up clocks, and initialize DMA. - * - * @param[in] clock enum eth_clk Core clock speed - */ -void eth_init(enum eth_clk clock) -{ - ETH_MACMIIAR = clock; - phy_reset(); - - ETH_MACCR = ETH_MACCR_CSTF | ETH_MACCR_FES | ETH_MACCR_DM | - ETH_MACCR_APCS | ETH_MACCR_RD; - ETH_MACFFR = ETH_MACFFR_RA | ETH_MACFFR_PM; - ETH_MACHTHR = 0; /* pass all frames */ - ETH_MACHTLR = 0; - ETH_MACFCR = (0x100 << ETH_MACFCR_PT_SHIFT); - ETH_MACVLANTR = 0; - ETH_DMAOMR = ETH_DMAOMR_DTCEFD | ETH_DMAOMR_RSF | ETH_DMAOMR_DFRF | - ETH_DMAOMR_TSF | ETH_DMAOMR_FEF | ETH_DMAOMR_OSF; - ETH_DMABMR = ETH_DMABMR_AAB | ETH_DMABMR_FB | - (32 << ETH_DMABMR_RDP_SHIFT) | (32 << ETH_DMABMR_PBL_SHIFT) | - ETH_DMABMR_PM_2_1 | ETH_DMABMR_USP; -} - -/*---------------------------------------------------------------------------*/ -/** @brief Enable the Ethernet IRQ - * - * @param[in] reason uint32_t Which irq will be enabled - */ -void eth_irq_enable(uint32_t reason) -{ - ETH_DMAIER |= reason; -} - -/*---------------------------------------------------------------------------*/ -/** @brief Disable the Ethernet IRQ - * - * @param[in] reason uint32_t Which irq will be disabled - */ -void eth_irq_disable(uint32_t reason) -{ - ETH_DMAIER &= ~reason; -} - -/*---------------------------------------------------------------------------*/ -/** @brief Check if IRQ is pending - * - * @param[in] reason uint32_t Which irq type has to be tested - * @returns bool true, if IRQ is pending - */ -bool eth_irq_is_pending(uint32_t reason) -{ - return (ETH_DMASR & reason) != 0; -} - -/*---------------------------------------------------------------------------*/ -/** @brief Check if IRQ is pending, and acknowledge it - * - * @param[in] reason uint32_t Which irq type has to be tested - * @returns bool true, if IRQ is pending - */ -bool eth_irq_ack_pending(uint32_t reason) -{ - reason &= ETH_DMASR; - ETH_DMASR = reason; - return reason != 0; -} - -/*---------------------------------------------------------------------------*/ -/** @brief Enable checksum offload feature - * - * This function will enable the Checksum offload feature for all of the - * transmit descriptors. Note to use this feature, descriptors must be in - * extended format. - */ -void eth_enable_checksum_offload(void) -{ - uint32_t tab = TxBD; - do { - ETH_DES0(tab) |= ETH_TDES0_CIC_IPPLPH; - tab = ETH_DES3(tab); - } - while (tab != TxBD); - - ETH_MACCR |= ETH_MACCR_IPCO; -} - -/*---------------------------------------------------------------------------*/ -/** @brief Process pending SMI transaction and wait to be done. - */ -static void eth_smi_transact(void) -{ - /* Begin transaction. */ - ETH_MACMIIAR |= ETH_MACMIIAR_MB; - - /* Wait for not busy. */ - while (ETH_MACMIIAR & ETH_MACMIIAR_MB); -} - -/*---------------------------------------------------------------------------*/ -/** @brief Write 16-bit register to the PHY - * - * @param[in] phy uint8_t ID of the PHY (defaults to 1) - * @param[in] reg uint8_t Register address - * @param[in] data uint16_t Data to write - */ -void eth_smi_write(uint8_t phy, uint8_t reg, uint16_t data) -{ - /* Write operation MW=1*/ - ETH_MACMIIAR = (ETH_MACMIIAR & ETH_MACMIIAR_CR) | /* save clocks */ - (phy << ETH_MACMIIAR_PA_SHIFT) | - (reg << ETH_MACMIIAR_MR_SHIFT) | - ETH_MACMIIAR_MW; - - ETH_MACMIIDR = data & ETH_MACMIIDR_MD; - - eth_smi_transact(); -} - -/*---------------------------------------------------------------------------*/ -/** @brief Read the 16-bit register from the PHY - * - * @param[in] phy uint8_t ID of the PHY (defaults to 1) - * @param[in] reg uint8_t Register address - * @returns uint16_t Readed data - */ -uint16_t eth_smi_read(uint8_t phy, uint8_t reg) -{ - /* Read operation MW=0*/ - ETH_MACMIIAR = (ETH_MACMIIAR & ETH_MACMIIAR_CR) | /* save clocks */ - (phy << ETH_MACMIIAR_PA_SHIFT) | - (reg << ETH_MACMIIAR_MR_SHIFT); - - eth_smi_transact(); - - return (uint16_t)(ETH_MACMIIDR & ETH_MACMIIDR_MD); -} - -/*---------------------------------------------------------------------------*/ -/** @brief Process the bit-operation on PHY register - * - * @param[in] phy uint8_t ID of the PHY (defaults to 1) - * @param[in] reg uint8_t Register address - * @param[in] bits uint16_t Bits that have to be set (or'ed) - * @param[in] mask uint16_t Bits that have to be clear (and'ed) - */ -void eth_smi_bit_op(uint8_t phy, uint8_t reg, uint16_t bits, uint16_t mask) -{ - uint16_t val = eth_smi_read(phy, reg); - eth_smi_write(phy, reg, (val & mask) | bits); -} - -/*---------------------------------------------------------------------------*/ -/** @brief Clear bits in the register - * - * @param[in] phy uint8_t ID of the PHY (defaults to 1) - * @param[in] reg uint8_t Register address - * @param[in] clearbits uint16_t Bits that have to be cleared - */ -void eth_smi_bit_clear(uint8_t phy, uint8_t reg, uint16_t clearbits) -{ - uint16_t val = eth_smi_read(phy, reg); - eth_smi_write(phy, reg, val & (uint16_t)~(clearbits)); -} - -/*---------------------------------------------------------------------------*/ -/** @brief Set bits in the register - * - * @param[in] phy uint8_t ID of the PHY (defaults to 1) - * @param[in] reg uint8_t Register address - * @param[in] bits uint16_t Bits that have to be set (or'ed) - */ -void eth_smi_bit_set(uint8_t phy, uint8_t reg, uint16_t setbits) -{ - uint16_t val = eth_smi_read(phy, reg); - eth_smi_write(phy, reg, val | setbits); -} - -/*---------------------------------------------------------------------------*/ - -/**@}*/ +/** @defgroup ethernet_mac_stm32fxx7_file MAC STM32Fxx7 + * + * @ingroup ETH + * + * @brief Ethernet MAC STM32Fxx7 Drivers + * + * @version 1.0.0 + * @author @htmlonly © @endhtmlonly 2013 Frantisek Burian + * + * @date 1 September 2013 + * + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Frantisek Burian + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include +#include +#include +#include + +/**@{*/ + +uint32_t TxBD; +uint32_t RxBD; + +/*---------------------------------------------------------------------------*/ +/** @brief Set MAC to the PHY + * + * @param[in] mac uint8_t* Desired MAC + */ +void eth_set_mac(uint8_t *mac) +{ + ETH_MACAHR(0) = ((uint32_t)mac[5] << 8) | (uint32_t)mac[4] | + ETH_MACA0HR_MACA0H; + ETH_MACALR(0) = ((uint32_t)mac[3] << 24) | ((uint32_t)mac[2] << 16) | + ((uint32_t)mac[1] << 8) | mac[0]; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Initialize descriptors + * + * @param[in] buf uint8_t* Buffer for the descriptors + * @param[in] nTx uint32_t Count of Transmit Descriptors + * @param[in] nRx uint32_t Count of Receive Descriptors + * @param[in] cTx uint32_t Bytes in each Transmit Descriptor + * @param[in] cRx uint32_t Bytes in each Receive Descriptor + * @param[in] isext bool true, if extended descriptors should be used + */ +void eth_desc_init(uint8_t *buf, uint32_t nTx, uint32_t nRx, uint32_t cTx, + uint32_t cRx, bool isext) +{ + memset(buf, 0, nTx * cTx + nRx * cRx); + + uint32_t bd = (uint32_t)buf; + uint32_t sz = isext ? ETH_DES_EXT_SIZE : ETH_DES_STD_SIZE; + + /* enable / disable extended frames */ + if (isext) { + ETH_DMABMR |= ETH_DMABMR_EDFE; + } else { + ETH_DMABMR &= ~ETH_DMABMR_EDFE; + } + + TxBD = bd; + while (--nTx > 0) { + ETH_DES0(bd) = ETH_TDES0_TCH; + ETH_DES2(bd) = bd + sz; + ETH_DES3(bd) = bd + sz + cTx; + bd = ETH_DES3(bd); + } + + ETH_DES0(bd) = ETH_TDES0_TCH; + ETH_DES2(bd) = bd + sz; + ETH_DES3(bd) = TxBD; + bd += sz + cTx; + + RxBD = bd; + while (--nRx > 0) { + ETH_DES0(bd) = ETH_RDES0_OWN; + ETH_DES1(bd) = ETH_RDES1_RCH | cRx; + ETH_DES2(bd) = bd + sz; + ETH_DES3(bd) = bd + sz + cRx; + bd = ETH_DES3(bd); + } + + ETH_DES0(bd) = ETH_RDES0_OWN; + ETH_DES1(bd) = ETH_RDES1_RCH | cRx; + ETH_DES2(bd) = bd + sz; + ETH_DES3(bd) = RxBD; + + ETH_DMARDLAR = (uint32_t) RxBD; + ETH_DMATDLAR = (uint32_t) TxBD; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Transmit packet + * + * @param[in] ppkt uint8_t* Pointer to the beginning of the packet + * @param[in] n uint32_t Size of the packet + * @returns bool true, if success + */ +bool eth_tx(uint8_t *ppkt, uint32_t n) +{ + if (ETH_DES0(TxBD) & ETH_TDES0_OWN) { + return false; + } + + memcpy((void *)ETH_DES2(TxBD), ppkt, n); + + ETH_DES1(TxBD) = n & ETH_TDES1_TBS1; + ETH_DES0(TxBD) |= ETH_TDES0_LS | ETH_TDES0_FS | ETH_TDES0_OWN; + TxBD = ETH_DES3(TxBD); + + if (ETH_DMASR & ETH_DMASR_TBUS) { + ETH_DMASR = ETH_DMASR_TBUS; + ETH_DMATPDR = 0; + } + + return true; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Receive packet + * + * @param[inout] ppkt uint8_t* Pointer to the data buffer where to store data + * @param[inout] len uint32_t* Pointer to the variable with the packet length + * @param[in] maxlen uint32_t Maximum length of the packet + * @returns bool true, if the buffer contains readed packet data + */ +bool eth_rx(uint8_t *ppkt, uint32_t *len, uint32_t maxlen) +{ + bool fs = false; + bool ls = false; + bool overrun = false; + uint32_t l = 0; + + while (!(ETH_DES0(RxBD) & ETH_RDES0_OWN) && !ls) { + l = (ETH_DES0(RxBD) & ETH_RDES0_FL) >> ETH_RDES0_FL_SHIFT; + + fs |= ETH_DES0(RxBD) & ETH_RDES0_FS; + ls |= ETH_DES0(RxBD) & ETH_RDES0_LS; + /* frame buffer overrun ?*/ + overrun |= fs && (maxlen < l); + + if (fs && !overrun) { + memcpy(ppkt, (void *)ETH_DES2(RxBD), l); + ppkt += l; + *len += l; + maxlen -= l; + } + + ETH_DES0(RxBD) = ETH_RDES0_OWN; + RxBD = ETH_DES3(RxBD); + } + + if (ETH_DMASR & ETH_DMASR_RBUS) { + ETH_DMASR = ETH_DMASR_RBUS; + ETH_DMARPDR = 0; + } + + return fs && ls && !overrun; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Start the Ethernet DMA processing + */ +void eth_start(void) +{ + ETH_MACCR |= ETH_MACCR_TE; + ETH_DMAOMR |= ETH_DMAOMR_FTF; + ETH_MACCR |= ETH_MACCR_RE; + + ETH_DMAOMR |= ETH_DMAOMR_ST; + ETH_DMAOMR |= ETH_DMAOMR_SR; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Initialize ethernet + * + * This function will initialize ethernet, set up clocks, and initialize DMA. + * + * @param[in] clock enum eth_clk Core clock speed + */ +void eth_init(enum eth_clk clock) +{ + ETH_MACMIIAR = clock; + phy_reset(); + + ETH_MACCR = ETH_MACCR_CSTF | ETH_MACCR_FES | ETH_MACCR_DM | + ETH_MACCR_APCS | ETH_MACCR_RD; + ETH_MACFFR = ETH_MACFFR_RA | ETH_MACFFR_PM; + ETH_MACHTHR = 0; /* pass all frames */ + ETH_MACHTLR = 0; + ETH_MACFCR = (0x100 << ETH_MACFCR_PT_SHIFT); + ETH_MACVLANTR = 0; + ETH_DMAOMR = ETH_DMAOMR_DTCEFD | ETH_DMAOMR_RSF | ETH_DMAOMR_DFRF | + ETH_DMAOMR_TSF | ETH_DMAOMR_FEF | ETH_DMAOMR_OSF; + ETH_DMABMR = ETH_DMABMR_AAB | ETH_DMABMR_FB | + (32 << ETH_DMABMR_RDP_SHIFT) | (32 << ETH_DMABMR_PBL_SHIFT) | + ETH_DMABMR_PM_2_1 | ETH_DMABMR_USP; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Enable the Ethernet IRQ + * + * @param[in] reason uint32_t Which irq will be enabled + */ +void eth_irq_enable(uint32_t reason) +{ + ETH_DMAIER |= reason; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Disable the Ethernet IRQ + * + * @param[in] reason uint32_t Which irq will be disabled + */ +void eth_irq_disable(uint32_t reason) +{ + ETH_DMAIER &= ~reason; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Check if IRQ is pending + * + * @param[in] reason uint32_t Which irq type has to be tested + * @returns bool true, if IRQ is pending + */ +bool eth_irq_is_pending(uint32_t reason) +{ + return (ETH_DMASR & reason) != 0; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Check if IRQ is pending, and acknowledge it + * + * @param[in] reason uint32_t Which irq type has to be tested + * @returns bool true, if IRQ is pending + */ +bool eth_irq_ack_pending(uint32_t reason) +{ + reason &= ETH_DMASR; + ETH_DMASR = reason; + return reason != 0; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Enable checksum offload feature + * + * This function will enable the Checksum offload feature for all of the + * transmit descriptors. Note to use this feature, descriptors must be in + * extended format. + */ +void eth_enable_checksum_offload(void) +{ + uint32_t tab = TxBD; + do { + ETH_DES0(tab) |= ETH_TDES0_CIC_IPPLPH; + tab = ETH_DES3(tab); + } + while (tab != TxBD); + + ETH_MACCR |= ETH_MACCR_IPCO; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Process pending SMI transaction and wait to be done. + */ +static void eth_smi_transact(void) +{ + /* Begin transaction. */ + ETH_MACMIIAR |= ETH_MACMIIAR_MB; + + /* Wait for not busy. */ + while (ETH_MACMIIAR & ETH_MACMIIAR_MB); +} + +/*---------------------------------------------------------------------------*/ +/** @brief Write 16-bit register to the PHY + * + * @param[in] phy uint8_t ID of the PHY (defaults to 1) + * @param[in] reg uint8_t Register address + * @param[in] data uint16_t Data to write + */ +void eth_smi_write(uint8_t phy, uint8_t reg, uint16_t data) +{ + /* Write operation MW=1*/ + ETH_MACMIIAR = (ETH_MACMIIAR & ETH_MACMIIAR_CR) | /* save clocks */ + (phy << ETH_MACMIIAR_PA_SHIFT) | + (reg << ETH_MACMIIAR_MR_SHIFT) | + ETH_MACMIIAR_MW; + + ETH_MACMIIDR = data & ETH_MACMIIDR_MD; + + eth_smi_transact(); +} + +/*---------------------------------------------------------------------------*/ +/** @brief Read the 16-bit register from the PHY + * + * @param[in] phy uint8_t ID of the PHY (defaults to 1) + * @param[in] reg uint8_t Register address + * @returns uint16_t Readed data + */ +uint16_t eth_smi_read(uint8_t phy, uint8_t reg) +{ + /* Read operation MW=0*/ + ETH_MACMIIAR = (ETH_MACMIIAR & ETH_MACMIIAR_CR) | /* save clocks */ + (phy << ETH_MACMIIAR_PA_SHIFT) | + (reg << ETH_MACMIIAR_MR_SHIFT); + + eth_smi_transact(); + + return (uint16_t)(ETH_MACMIIDR & ETH_MACMIIDR_MD); +} + +/*---------------------------------------------------------------------------*/ +/** @brief Process the bit-operation on PHY register + * + * @param[in] phy uint8_t ID of the PHY (defaults to 1) + * @param[in] reg uint8_t Register address + * @param[in] bits uint16_t Bits that have to be set (or'ed) + * @param[in] mask uint16_t Bits that have to be clear (and'ed) + */ +void eth_smi_bit_op(uint8_t phy, uint8_t reg, uint16_t bits, uint16_t mask) +{ + uint16_t val = eth_smi_read(phy, reg); + eth_smi_write(phy, reg, (val & mask) | bits); +} + +/*---------------------------------------------------------------------------*/ +/** @brief Clear bits in the register + * + * @param[in] phy uint8_t ID of the PHY (defaults to 1) + * @param[in] reg uint8_t Register address + * @param[in] clearbits uint16_t Bits that have to be cleared + */ +void eth_smi_bit_clear(uint8_t phy, uint8_t reg, uint16_t clearbits) +{ + uint16_t val = eth_smi_read(phy, reg); + eth_smi_write(phy, reg, val & (uint16_t)~(clearbits)); +} + +/*---------------------------------------------------------------------------*/ +/** @brief Set bits in the register + * + * @param[in] phy uint8_t ID of the PHY (defaults to 1) + * @param[in] reg uint8_t Register address + * @param[in] bits uint16_t Bits that have to be set (or'ed) + */ +void eth_smi_bit_set(uint8_t phy, uint8_t reg, uint16_t setbits) +{ + uint16_t val = eth_smi_read(phy, reg); + eth_smi_write(phy, reg, val | setbits); +} + +/*---------------------------------------------------------------------------*/ + +/**@}*/ diff --git a/lib/ethernet/phy.c b/lib/ethernet/phy.c index 1f9197e7..4866198a 100644 --- a/lib/ethernet/phy.c +++ b/lib/ethernet/phy.c @@ -1,64 +1,64 @@ -/** @defgroup ethernet_phy_file PHY Generic Drivers - * - * @ingroup ETH - * - * @brief Ethernet PHY Generic Drivers - * - * @version 1.0.0 - * @author @htmlonly © @endhtmlonly 2013 Frantisek Burian - * - * @date 1 September 2013 - * - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Frantisek Burian - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -/**@{*/ - -/*---------------------------------------------------------------------------*/ -/** @brief Is the link up ? - * - * @returns bool true, if link is up - */ -bool phy_link_isup(void) -{ - return eth_smi_read(1, PHY_REG_BSR) & PHY_REG_BSR_UP; -} - -/*---------------------------------------------------------------------------*/ -/** @brief Reset the PHY - * - * Reset the PHY chip and wait for done - */ -void phy_reset(void) -{ - eth_smi_write(1, PHY_REG_BCR, PHY_REG_BCR_RESET); - - while (eth_smi_read(1, PHY_REG_BCR) & PHY_REG_BCR_RESET); -} - -/*---------------------------------------------------------------------------*/ - -/**@}*/ +/** @defgroup ethernet_phy_file PHY Generic Drivers + * + * @ingroup ETH + * + * @brief Ethernet PHY Generic Drivers + * + * @version 1.0.0 + * @author @htmlonly © @endhtmlonly 2013 Frantisek Burian + * + * @date 1 September 2013 + * + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Frantisek Burian + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + +/**@{*/ + +/*---------------------------------------------------------------------------*/ +/** @brief Is the link up ? + * + * @returns bool true, if link is up + */ +bool phy_link_isup(void) +{ + return eth_smi_read(1, PHY_REG_BSR) & PHY_REG_BSR_UP; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Reset the PHY + * + * Reset the PHY chip and wait for done + */ +void phy_reset(void) +{ + eth_smi_write(1, PHY_REG_BCR, PHY_REG_BCR_RESET); + + while (eth_smi_read(1, PHY_REG_BCR) & PHY_REG_BCR_RESET); +} + +/*---------------------------------------------------------------------------*/ + +/**@}*/ diff --git a/lib/ethernet/phy_ksz8051mll.c b/lib/ethernet/phy_ksz8051mll.c index 407c5a4d..1faae4fa 100644 --- a/lib/ethernet/phy_ksz8051mll.c +++ b/lib/ethernet/phy_ksz8051mll.c @@ -1,89 +1,89 @@ -/** @defgroup ethernet_phy_ksz8051mll_file PHY KSZ8051MLL - * - * @ingroup ETH - * - * @brief Ethernet PHY STM32Fxx7 Drivers - * - * @version 1.0.0 - * @author @htmlonly © @endhtmlonly 2013 Frantisek Burian - * - * @date 1 September 2013 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2013 Frantisek Burian - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include -#include - - -/**@{*/ - -/*---------------------------------------------------------------------------*/ -/** @brief Get the current link status - * - * Retrieve the link speed and duplex status of the link. - * - * @returns ::phy_status Link status - */ -enum phy_status phy_link_status(void) -{ - return eth_smi_read(1, PHY_REG_CR1) & 0x07; -} - -/*---------------------------------------------------------------------------*/ -/** @brief Force autonegotiation - * - * Force the autonegotiation and set link speed and duplex mode of the link - * - * @param[in] mode enum phy_status Desired link status - */ -void phy_autoneg_force(enum phy_status mode) -{ - uint16_t bst = 0; - - if ((mode == LINK_FD_10M) || (mode == LINK_FD_100M) || - (mode == LINK_FD_1000M) || (mode == LINK_FD_10000M)) { - bst |= PHY_REG_BCR_FD; - } - - if ((mode == LINK_FD_100M) || (mode == LINK_FD_100M)) { - bst |= PHY_REG_BCR_100M; - } - - eth_smi_bit_op(1, PHY_REG_BCR, bst, - ~(PHY_REG_BCR_AN | PHY_REG_BCR_100M | PHY_REG_BCR_FD)); -} - -/*---------------------------------------------------------------------------*/ -/** @brief Enable the autonegotiation - * - * Enable the autonegotiation of the link speed and duplex mode - */ -void phy_autoneg_enable(void) -{ - eth_smi_bit_set(1, PHY_REG_BCR, PHY_REG_BCR_AN | PHY_REG_BCR_ANRST); -} - -/*---------------------------------------------------------------------------*/ - -/**@}*/ +/** @defgroup ethernet_phy_ksz8051mll_file PHY KSZ8051MLL + * + * @ingroup ETH + * + * @brief Ethernet PHY STM32Fxx7 Drivers + * + * @version 1.0.0 + * @author @htmlonly © @endhtmlonly 2013 Frantisek Burian + * + * @date 1 September 2013 + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Frantisek Burian + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include +#include + + +/**@{*/ + +/*---------------------------------------------------------------------------*/ +/** @brief Get the current link status + * + * Retrieve the link speed and duplex status of the link. + * + * @returns ::phy_status Link status + */ +enum phy_status phy_link_status(void) +{ + return eth_smi_read(1, PHY_REG_CR1) & 0x07; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Force autonegotiation + * + * Force the autonegotiation and set link speed and duplex mode of the link + * + * @param[in] mode enum phy_status Desired link status + */ +void phy_autoneg_force(enum phy_status mode) +{ + uint16_t bst = 0; + + if ((mode == LINK_FD_10M) || (mode == LINK_FD_100M) || + (mode == LINK_FD_1000M) || (mode == LINK_FD_10000M)) { + bst |= PHY_REG_BCR_FD; + } + + if ((mode == LINK_FD_100M) || (mode == LINK_FD_100M)) { + bst |= PHY_REG_BCR_100M; + } + + eth_smi_bit_op(1, PHY_REG_BCR, bst, + ~(PHY_REG_BCR_AN | PHY_REG_BCR_100M | PHY_REG_BCR_FD)); +} + +/*---------------------------------------------------------------------------*/ +/** @brief Enable the autonegotiation + * + * Enable the autonegotiation of the link speed and duplex mode + */ +void phy_autoneg_enable(void) +{ + eth_smi_bit_set(1, PHY_REG_BCR, PHY_REG_BCR_AN | PHY_REG_BCR_ANRST); +} + +/*---------------------------------------------------------------------------*/ + +/**@}*/ diff --git a/lib/stm32/common/exti_common_all.c b/lib/stm32/common/exti_common_all.c index aede62a2..4e06a91a 100644 --- a/lib/stm32/common/exti_common_all.c +++ b/lib/stm32/common/exti_common_all.c @@ -110,7 +110,7 @@ void exti_select_source(uint32_t exti, uint32_t gpioport) case GPIOD: bits = 3; break; -#if defined(GPIOE) && defined(GPIO_PORT_E_BASE) +#if defined(GPIOE) && defined(GPIO_PORT_E_BASE) case GPIOE: bits = 4; break; diff --git a/lib/stm32/common/rcc_common_all.c b/lib/stm32/common/rcc_common_all.c index 5b476dd5..797ee0f7 100644 --- a/lib/stm32/common/rcc_common_all.c +++ b/lib/stm32/common/rcc_common_all.c @@ -17,15 +17,15 @@ * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . */ - + #include /*---------------------------------------------------------------------------*/ /** @brief RCC Enable Peripheral Clocks. * - * Enable the clock on particular peripherals. There are three registers - * involved, each one controlling the enabling of clocks associated with the - * AHB, APB1 and APB2 respectively. Several peripherals could be enabled + * Enable the clock on particular peripherals. There are three registers + * involved, each one controlling the enabling of clocks associated with the + * AHB, APB1 and APB2 respectively. Several peripherals could be enabled * simultaneously only if they are controlled by the same register. * * @param[in] *reg Unsigned int32. Pointer to a Clock Enable Register @@ -45,9 +45,9 @@ void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en) /*---------------------------------------------------------------------------*/ /** @brief RCC Disable Peripheral Clocks. * - * Enable the clock on particular peripherals. There are three registers - * involved, each one controlling the enabling of clocks associated with - * the AHB, APB1 and APB2 respectively. Several peripherals could be disabled + * Enable the clock on particular peripherals. There are three registers + * involved, each one controlling the enabling of clocks associated with + * the AHB, APB1 and APB2 respectively. Several peripherals could be disabled * simultaneously only if they are controlled by the same register. * * @param[in] *reg Unsigned int32. Pointer to a Clock Enable Register @@ -70,7 +70,7 @@ void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en) * controlling reset of peripherals associated with the AHB, APB1 and APB2 * respectively. Several peripherals could be reset simultaneously only if * they are controlled by the same register. - * + * * @param[in] *reg Unsigned int32. Pointer to a Reset Register * (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR) * @param[in] reset Unsigned int32. Logical OR of all resets. @@ -93,7 +93,8 @@ void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset) * * @param[in] *reg Unsigned int32. Pointer to a Reset Register * (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR) - * @param[in] clear_reset Unsigned int32. Logical OR of all resets to be removed: + * @param[in] clear_reset Unsigned int32. Logical OR of all resets to be + * removed: * @li If register is RCC_AHBRSTR, from @ref rcc_ahbrstr_rst * @li If register is RCC_APB1RSTR, from @ref rcc_apb1rstr_rst * @li If register is RCC_APB2RSTR, from @ref rcc_apb2rstr_rst @@ -115,7 +116,7 @@ void rcc_peripheral_clear_reset(volatile uint32_t *reg, uint32_t clear_reset) * * For available constants, see #periph_t (RCC_UART1 for example) */ - + void rcc_periph_clock_enable(enum rcc_periph_clken clken) { _RCC_REG(clken) |= _RCC_BIT(clken); @@ -182,4 +183,4 @@ void rcc_periph_reset_release(enum rcc_periph_rst rst) } #undef _RCC_REG -#undef _RCC_BIT \ No newline at end of file +#undef _RCC_BIT diff --git a/lib/stm32/f0/adc.c b/lib/stm32/f0/adc.c index eaf8580e..7dbf84a9 100644 --- a/lib/stm32/f0/adc.c +++ b/lib/stm32/f0/adc.c @@ -788,7 +788,7 @@ void adc_enable_analog_watchdog_on_all_channels(uint32_t adc) void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, uint8_t chan) { - ADC_CFGR1(adc) = (ADC_CFGR1(adc) & ~ADC_CFGR1_AWDCH) | \ + ADC_CFGR1(adc) = (ADC_CFGR1(adc) & ~ADC_CFGR1_AWDCH) | ADC_CFGR1_AWDCH_VAL(chan); ADC_CFGR1(adc) |= ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL; diff --git a/lib/stm32/f0/rcc.c b/lib/stm32/f0/rcc.c index 09f3bdcd..e5a9a200 100644 --- a/lib/stm32/f0/rcc.c +++ b/lib/stm32/f0/rcc.c @@ -250,7 +250,7 @@ void rcc_osc_on(enum rcc_osc osc) RCC_CSR |= RCC_CSR_LSION; break; case PLL: - RCC_CR|=RCC_CR_PLLON; + RCC_CR |= RCC_CR_PLLON; break; } }