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[Style] Global style fix run.

This commit is contained in:
Piotr Esden-Tempski 2014-01-03 01:07:30 +01:00
parent 67efedec54
commit a909b5ca9e
25 changed files with 920 additions and 915 deletions
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559
include/libopencm3/cm3/cortex.h
View File

@ -1,277 +1,282 @@
/** @defgroup CM3_cortex_defines Cortex Core Defines
*
* @brief <b>libopencm3 Defined Constants and Types for the Cortex Core </b>
*
* @ingroup CM3_defines
*
* @version 1.0.0
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Ben Gamari <bgamari@gmail.com>
* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_CORTEX_H
#define LIBOPENCM3_CORTEX_H
/**@{*/
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Enable interrupts
*
* Disable the interrupt mask and enable interrupts globally
*/
static inline void cm_enable_interrupts(void)
{
__asm__("CPSIE I\n");
}
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Disable interrupts
*
* Mask all interrupts globally
*/
static inline void cm_disable_interrupts(void)
{
__asm__("CPSID I\n");
}
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Enable faults
*
* Disable the HardFault mask and enable fault interrupt globally
*/
static inline void cm_enable_faults(void)
{
__asm__("CPSIE F\n");
}
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Disable faults
*
* Mask the HardFault interrupt globally
*/
static inline void cm_disable_faults(void)
{
__asm__("CPSID F\n");
}
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Check if interrupts are masked
*
* Checks, if interrupts are masked (disabled).
*
* @returns true, if interrupts are disabled.
*/
__attribute__((always_inline))
static inline bool cm_is_masked_interrupts(void)
{
register uint32_t result;
__asm__ ("MRS %0, PRIMASK" : "=r" (result));
return result;
}
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Check if Fault interrupt is masked
*
* Checks, if HardFault interrupt is masked (disabled).
*
* @returns bool true, if HardFault interrupt is disabled.
*/
__attribute__((always_inline))
static inline bool cm_is_masked_faults(void)
{
register uint32_t result;
__asm__ ("MRS %0, FAULTMASK" : "=r" (result));
return result;
}
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Mask interrupts
*
* This function switches the mask of the interrupts. If mask is true, the
* interrupts will be disabled. The result of this function can be used for
* restoring previous state of the mask.
*
* @param[in] mask bool New state of the interrupt mask
* @returns bool old state of the interrupt mask
*/
__attribute__((always_inline))
static inline bool cm_mask_interrupts(bool mask)
{
register bool old;
__asm__ __volatile__("MRS %0, PRIMASK" : "=r" (old));
__asm__ __volatile__("" : : : "memory");
__asm__ __volatile__("MSR PRIMASK, %0" : : "r" (mask));
return old;
}
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Mask HardFault interrupt
*
* This function switches the mask of the HardFault interrupt. If mask is true,
* the HardFault interrupt will be disabled. The result of this function can be
* used for restoring previous state of the mask.
*
* @param[in] mask bool New state of the HardFault interrupt mask
* @returns bool old state of the HardFault interrupt mask
*/
__attribute__((always_inline))
static inline bool cm_mask_faults(bool mask)
{
register bool old;
__asm__ __volatile__ ("MRS %0, FAULTMASK" : "=r" (old));
__asm__ __volatile__ ("" : : : "memory");
__asm__ __volatile__ ("MSR FAULTMASK, %0" : : "r" (mask));
return old;
}
/**@}*/
/*===========================================================================*/
/** @defgroup CM3_cortex_atomic_defines Cortex Core Atomic support Defines
*
* @brief Atomic operation support
*
* @ingroup CM3_cortex_defines
*/
/**@{*/
#if !defined(__DOXYGEN__)
/* Do not populate this definition outside */
static inline bool __cm_atomic_set(bool* val)
{
return cm_mask_interrupts(*val);
}
#define __CM_SAVER(state) __val = state, \
__save __attribute__((__cleanup__(__cm_atomic_set))) = \
__cm_atomic_set(&__val)
#endif /* !defined(__DOXYGEN) */
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Atomic Declare block
*
* This macro disables interrupts for the next command or block of code. The
* interrupt mask is automatically restored after exit of the boundary of the
* code block. Therefore restore of interrupt is done automatically after call
* of return or goto control sentence jumping outside of the block.
*
* @warning The usage of sentences break or continue is prohibited in the block
* due to implementation of this macro!
*
* @note It is safe to use this block inside normal code and in interrupt
* routine.
*
* @example 1: Basic usage of atomic block
*
* @code
* uint64_t value; // This value is used somewhere in interrupt
*
* ...
*
* CM_ATOMIC_BLOCK() { // interrupts are masked in this block
* value = value * 1024 + 651; // access value as atomic
* } // interrupts is restored automatically
* @endcode
*
* @example 2: Use of return inside block:
*
* @code
* uint64_t value; // This value is used somewhere in interrupt
*
* ...
*
* uint64_t allocval(void)
* {
* CM_ATOMIC_BLOCK() { // interrupts are masked in this block
* value = value * 1024 + 651; // do long atomic operation
* return value; // interrupts is restored automatically
* }
* }
* @endcode
*/
#if defined(__DOXYGEN__)
#define CM_ATOMIC_BLOCK()
#else /* defined(__DOXYGEN__) */
#define CM_ATOMIC_BLOCK() \
for (bool ___CM_SAVER(true), __my = true; __my; __my = false)
#endif /* defined(__DOXYGEN__) */
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Atomic Declare context
*
* This macro disables interrupts in the current block of code from the place
* where it is defined to the end of the block. The interrupt mask is
* automatically restored after exit of the boundary of the code block.
* Therefore restore of interrupt is done automatically after call of return,
* continue, break, or goto control sentence jumping outside of the block.
*
* @note This function is intended for use in for- cycles to enable the use of
* break and contine sentences inside the block, and for securing the atomic
* reader-like functions.
*
* @note It is safe to use this block inside normal code and in interrupt
* routine.
*
* @example 1: Basic usage of atomic context
*
* @code
* uint64_t value; // This value is used somewhere in interrupt
*
* ...
*
* for (int i=0;i < 100; i++) {
* CM_ATOMIC_CONTEXT(); // interrupts are masked in this block
* value += 100; // access value as atomic
* if ((value % 16) == 0) {
* break; // restore interrupts and break cycle
* }
* } // interrupts is restored automatically
* @endcode
*
* @example 2: Usage of atomic context inside atomic reader fcn.
*
* @code
* uint64_t value; // This value is used somewhere in interrupt
*
* ...
*
* uint64_t getnextval(void)
* {
* CM_ATOMIC_CONTEXT(); // interrupts are masked in this block
* value = value + 3; // do long atomic operation
* return value; // interrupts is restored automatically
* }
* @endcode
*/
#if defined(__DOXYGEN__)
#define CM_ATOMIC_CONTEXT()
#else /* defined(__DOXYGEN__) */
#define CM_ATOMIC_CONTEXT() bool __CM_SAVER(true)
#endif /* defined(__DOXYGEN__) */
/**@}*/
#endif
/** @defgroup CM3_cortex_defines Cortex Core Defines
*
* @brief <b>libopencm3 Defined Constants and Types for the Cortex Core </b>
*
* @ingroup CM3_defines
*
* @version 1.0.0
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Ben Gamari <bgamari@gmail.com>
* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_CORTEX_H
#define LIBOPENCM3_CORTEX_H
/**@{*/
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Enable interrupts
*
* Disable the interrupt mask and enable interrupts globally
*/
static inline void cm_enable_interrupts(void)
{
__asm__("CPSIE I\n");
}
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Disable interrupts
*
* Mask all interrupts globally
*/
static inline void cm_disable_interrupts(void)
{
__asm__("CPSID I\n");
}
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Enable faults
*
* Disable the HardFault mask and enable fault interrupt globally
*/
static inline void cm_enable_faults(void)
{
__asm__("CPSIE F\n");
}
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Disable faults
*
* Mask the HardFault interrupt globally
*/
static inline void cm_disable_faults(void)
{
__asm__("CPSID F\n");
}
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Check if interrupts are masked
*
* Checks, if interrupts are masked (disabled).
*
* @returns true, if interrupts are disabled.
*/
__attribute__((always_inline))
static inline bool cm_is_masked_interrupts(void)
{
register uint32_t result;
__asm__ ("MRS %0, PRIMASK" : "=r" (result));
return result;
}
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Check if Fault interrupt is masked
*
* Checks, if HardFault interrupt is masked (disabled).
*
* @returns bool true, if HardFault interrupt is disabled.
*/
__attribute__((always_inline))
static inline bool cm_is_masked_faults(void)
{
register uint32_t result;
__asm__ ("MRS %0, FAULTMASK" : "=r" (result));
return result;
}
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Mask interrupts
*
* This function switches the mask of the interrupts. If mask is true, the
* interrupts will be disabled. The result of this function can be used for
* restoring previous state of the mask.
*
* @param[in] mask bool New state of the interrupt mask
* @returns bool old state of the interrupt mask
*/
__attribute__((always_inline))
static inline bool cm_mask_interrupts(bool mask)
{
register bool old;
__asm__ __volatile__("MRS %0, PRIMASK" : "=r" (old));
__asm__ __volatile__("" : : : "memory");
__asm__ __volatile__("MSR PRIMASK, %0" : : "r" (mask));
return old;
}
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Mask HardFault interrupt
*
* This function switches the mask of the HardFault interrupt. If mask is true,
* the HardFault interrupt will be disabled. The result of this function can be
* used for restoring previous state of the mask.
*
* @param[in] mask bool New state of the HardFault interrupt mask
* @returns bool old state of the HardFault interrupt mask
*/
__attribute__((always_inline))
static inline bool cm_mask_faults(bool mask)
{
register bool old;
__asm__ __volatile__ ("MRS %0, FAULTMASK" : "=r" (old));
__asm__ __volatile__ ("" : : : "memory");
__asm__ __volatile__ ("MSR FAULTMASK, %0" : : "r" (mask));
return old;
}
/**@}*/
/*===========================================================================*/
/** @defgroup CM3_cortex_atomic_defines Cortex Core Atomic support Defines
*
* @brief Atomic operation support
*
* @ingroup CM3_cortex_defines
*/
/**@{*/
#if !defined(__DOXYGEN__)
/* Do not populate this definition outside */
static inline bool __cm_atomic_set(bool *val)
{
return cm_mask_interrupts(*val);
}
#define __CM_SAVER(state) \
do { \
__val = state, \
__save __attribute__((__cleanup__(__cm_atomic_set))) = \
__cm_atomic_set(&__val); \
} while (0)
#endif /* !defined(__DOXYGEN) */
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Atomic Declare block
*
* This macro disables interrupts for the next command or block of code. The
* interrupt mask is automatically restored after exit of the boundary of the
* code block. Therefore restore of interrupt is done automatically after call
* of return or goto control sentence jumping outside of the block.
*
* @warning The usage of sentences break or continue is prohibited in the block
* due to implementation of this macro!
*
* @note It is safe to use this block inside normal code and in interrupt
* routine.
*
* @example 1: Basic usage of atomic block
*
* @code
* uint64_t value; // This value is used somewhere in interrupt
*
* ...
*
* CM_ATOMIC_BLOCK() { // interrupts are masked in this block
* value = value * 1024 + 651; // access value as atomic
* } // interrupts is restored automatically
* @endcode
*
* @example 2: Use of return inside block:
*
* @code
* uint64_t value; // This value is used somewhere in interrupt
*
* ...
*
* uint64_t allocval(void)
* {
* CM_ATOMIC_BLOCK() { // interrupts are masked in this block
* value = value * 1024 + 651; // do long atomic operation
* return value; // interrupts is restored automatically
* }
* }
* @endcode
*/
#if defined(__DOXYGEN__)
#define CM_ATOMIC_BLOCK()
#else /* defined(__DOXYGEN__) */
#define CM_ATOMIC_BLOCK() \
do { \
for (bool ___CM_SAVER(true), __my = true; __my; __my = false); \
} while (0)
#endif /* defined(__DOXYGEN__) */
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Atomic Declare context
*
* This macro disables interrupts in the current block of code from the place
* where it is defined to the end of the block. The interrupt mask is
* automatically restored after exit of the boundary of the code block.
* Therefore restore of interrupt is done automatically after call of return,
* continue, break, or goto control sentence jumping outside of the block.
*
* @note This function is intended for use in for- cycles to enable the use of
* break and contine sentences inside the block, and for securing the atomic
* reader-like functions.
*
* @note It is safe to use this block inside normal code and in interrupt
* routine.
*
* @example 1: Basic usage of atomic context
*
* @code
* uint64_t value; // This value is used somewhere in interrupt
*
* ...
*
* for (int i=0;i < 100; i++) {
* CM_ATOMIC_CONTEXT(); // interrupts are masked in this block
* value += 100; // access value as atomic
* if ((value % 16) == 0) {
* break; // restore interrupts and break cycle
* }
* } // interrupts is restored automatically
* @endcode
*
* @example 2: Usage of atomic context inside atomic reader fcn.
*
* @code
* uint64_t value; // This value is used somewhere in interrupt
*
* ...
*
* uint64_t getnextval(void)
* {
* CM_ATOMIC_CONTEXT(); // interrupts are masked in this block
* value = value + 3; // do long atomic operation
* return value; // interrupts is restored automatically
* }
* @endcode
*/
#if defined(__DOXYGEN__)
#define CM_ATOMIC_CONTEXT()
#else /* defined(__DOXYGEN__) */
#define CM_ATOMIC_CONTEXT() bool __CM_SAVER(true)
#endif /* defined(__DOXYGEN__) */
/**@}*/
#endif

2
include/libopencm3/cm3/sync.h
View File

@ -32,7 +32,7 @@ void __dmb(void);
/* --- Exclusive load and store instructions ------------------------------- */
/* Those are defined only on CM3 or CM4 */
#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
uint32_t __ldrex(volatile uint32_t *addr);
uint32_t __strex(uint32_t val, volatile uint32_t *addr);

92
include/libopencm3/ethernet/mac.h
View File

@ -1,46 +1,46 @@
/** @defgroup ethernet_mac_defines MAC Generic Defines
*
* @brief <b>Defined Constants and Types for the Ethernet MAC</b>
*
* @ingroup ETH
*
* @version 1.0.0
*
* @author @htmlonly &copy; @endhtmlonly 2013 Frantisek Burian <BuFran@seznam.cz>
*
* @date 1 September 2013
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
#if defined(STM32F1)
# include <libopencm3/ethernet/mac_stm32fxx7.h>
#elif defined(STM32F4)
# include <libopencm3/ethernet/mac_stm32fxx7.h>
#else
# error "stm32 family not defined."
#endif
/**@}*/
/** @defgroup ethernet_mac_defines MAC Generic Defines
*
* @brief <b>Defined Constants and Types for the Ethernet MAC</b>
*
* @ingroup ETH
*
* @version 1.0.0
*
* @author @htmlonly &copy; @endhtmlonly 2013 Frantisek Burian <BuFran@seznam.cz>
*
* @date 1 September 2013
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
#if defined(STM32F1)
# include <libopencm3/ethernet/mac_stm32fxx7.h>
#elif defined(STM32F4)
# include <libopencm3/ethernet/mac_stm32fxx7.h>
#else
# error "stm32 family not defined."
#endif
/**@}*/

15
include/libopencm3/ethernet/mac_stm32fxx7.h
View File

@ -1,6 +1,6 @@
/** @defgroup ethernet_mac_stm32fxx7_defines MAC STM32Fxx7 Defines
*
* @brief <b>Defined Constants and Types for the Ethernet MAC for STM32Fxx7
* @brief <b>Defined Constants and Types for the Ethernet MAC for STM32Fxx7
* chips</b>
*
* @ingroup ETH
@ -12,10 +12,10 @@
* @date 1 September 2013
*
* LGPL License Terms @ref lgpl_license
*/
*/
/*
* This file is part of the libopencm3 project.
*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
*
* This library is free software: you can redistribute it and/or modify
@ -36,8 +36,8 @@
#define LIBOPENCM3_ETHERNET_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
#include <libopencm3/cm3/common.h>
/**@{*/
/* Ethernet MAC registers */
@ -746,8 +746,7 @@ END_DECLS
* for (;;)
* eth_tx(frame,sizeof(frame));
*/
/**@}*/
#endif

16
include/libopencm3/ethernet/phy.h
View File

@ -11,10 +11,10 @@
* @date 1 September 2013
*
* LGPL License Terms @ref lgpl_license
*/
*/
/*
* This file is part of the libopencm3 project.
*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
*
* This library is free software: you can redistribute it and/or modify
@ -29,12 +29,12 @@
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
*/
#ifndef LIBOPENCM3_PHY_H
#define LIBOPENCM3_PHY_H
#include <stdbool.h>
#include <stdbool.h>
/**@{*/
/* Registers */
@ -83,8 +83,8 @@ bool phy_link_isup(void);
enum phy_status phy_link_status(void);
void phy_autoneg_force(enum phy_status mode);
void phy_autoneg_enable(void);
void phy_autoneg_enable(void);
/**@}*/

18
include/libopencm3/ethernet/phy_ksz8051mll.h
View File

@ -1,6 +1,6 @@
/** @defgroup ethernet_phy_ksz8051mll_defines PHY KSZ8051mll Defines
*
* @brief <b>Defined Constants and Types for the Ethernet PHY KSZ8051mll
* @brief <b>Defined Constants and Types for the Ethernet PHY KSZ8051mll
* chips</b>
*
* @ingroup ETH
@ -12,10 +12,10 @@
* @date 1 September 2013
*
* LGPL License Terms @ref lgpl_license
*/
*/
/*
* This file is part of the libopencm3 project.
*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
*
* This library is free software: you can redistribute it and/or modify
@ -30,13 +30,13 @@
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
*/
#ifndef LIBOPENCM3_PHY_KSZ8051MLL_H
#define LIBOPENCM3_PHY_KSZ8051MLL_H
#include <libopencm3/ethernet/phy.h>
/**@{*/
/* Registers */
@ -52,8 +52,8 @@
#define PHY_REG_LINKMD 0x1D
#define PHY_REG_CR1 0x1E
#define PHY_REG_CR2 0x1E
#define PHY_REG_CR2 0x1E
/**@}*/

4
include/libopencm3/lpc43xx/sgpio.h
View File

@ -483,7 +483,7 @@ LGPL License Terms @ref lgpl_license
#define SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE_SHIFT (3)
#define SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE_MASK \
(0x3 << SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE_SHIFT)
#define SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE(x)
#define SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE(x)
((x) << SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE_SHIFT)
/* QUALIFIER_MODE: Select qualifier mode */
@ -684,7 +684,7 @@ typedef struct {
} sgpio_t;
/* Global access to SGPIO structure */
#define SGPIO ((sgpio_t*)SGPIO_PORT_BASE)
#define SGPIO ((sgpio_t *)SGPIO_PORT_BASE)
/**@}*/

2
include/libopencm3/stm32/common/rcc_common_all.h
View File

@ -29,7 +29,7 @@
#ifndef LIBOPENCM3_RCC_COMMON_ALL_H
#define LIBOPENCM3_RCC_COMMON_ALL_H
BEGIN_DECLS
void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en);

2
include/libopencm3/stm32/f1/adc.h
View File

@ -622,7 +622,7 @@ injected channels.
#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQR_JSQ2_LSB)
#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQR_JSQ1_LSB)
#define ADC_JSQR_JSQ_VAL(n,val) ((val) << (((n) - 1) * 5))
#define ADC_JSQR_JSQ_VAL(n, val) ((val) << (((n) - 1) * 5))
#define ADC_JSQR_JL_VAL(val) (((val) - 1) << ADC_JSQR_JL_SHIFT)
/* --- ADC_JDRx, ADC_DR values --------------------------------------------- */

6
include/libopencm3/stm32/f1/rcc.h
View File

@ -519,7 +519,7 @@ enum rcc_periph_clken {
RCC_ETHMAC = _REG_BIT(0x14, 14),/*--C*/
RCC_ETHMACTX = _REG_BIT(0x14, 15),/*--C*/
RCC_ETHMACRX = _REG_BIT(0x14, 16),/*--C*/
/* APB2 peripherals */
RCC_AFIO = _REG_BIT(0x18, 0),/*VNC*/
RCC_GPIOA = _REG_BIT(0x18, 2),/*VNC*/
@ -542,7 +542,7 @@ enum rcc_periph_clken {
RCC_TIM9 = _REG_BIT(0x18, 19),/*-N-*/
RCC_TIM10 = _REG_BIT(0x18, 20),/*-N-*/
RCC_TIM11 = _REG_BIT(0x18, 21),/*-N-*/
/* APB1 peripherals */
RCC_TIM2 = _REG_BIT(0x1C, 0),/*VNC*/
RCC_TIM3 = _REG_BIT(0x1C, 1),/*VNC*/
@ -600,7 +600,7 @@ enum rcc_periph_rst {
RST_TIM9 = _REG_BIT(0x0c, 19),/*-N-*/
RST_TIM10 = _REG_BIT(0x0c, 20),/*-N-*/
RST_TIM11 = _REG_BIT(0x0c, 21),/*-N-*/
/* APB1 peripherals */
RST_TIM2 = _REG_BIT(0x10, 0),/*VNC*/
RST_TIM3 = _REG_BIT(0x10, 1),/*VNC*/

2
include/libopencm3/stm32/f3/adc.h
View File

@ -628,7 +628,7 @@
#define ADC_JSQR_JSQ2_LSB 14
#define ADC_JSQR_JSQ1_LSB 8
#define ADC_JSQR_JSQ_VAL(n,val) ((val) << (((n) - 1) * 6 + 8))
#define ADC_JSQR_JSQ_VAL(n, val) ((val) << (((n) - 1) * 6 + 8))
#define ADC_JSQR_JL_VAL(val) (((val) - 1) << ADC_JSQR_JL_SHIFT)
/* Bits 30:26 JSQ4[4:0]: 4th conversion in the injected sequence */

2
include/libopencm3/stm32/f4/adc.h
View File

@ -587,7 +587,7 @@ injected channels.
#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQR_JSQ2_LSB)
#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQR_JSQ1_LSB)
#define ADC_JSQR_JSQ_VAL(n,val) ((val) << (((n) - 1) * 5))
#define ADC_JSQR_JSQ_VAL(n, val) ((val) << (((n) - 1) * 5))
#define ADC_JSQR_JL_VAL(val) (((val) - 1) << ADC_JSQR_JL_SHIFT)
/* --- ADC_JDRx, ADC_DR values --------------------------------------------- */

6
include/libopencm3/stm32/f4/rcc.h
View File

@ -530,7 +530,7 @@ enum rcc_periph_clken {
RCC_TIM12 = _REG_BIT(0x40, 6),
RCC_TIM13 = _REG_BIT(0x40, 7),
RCC_TIM14 = _REG_BIT(0x40, 8),
RCC_WWDG = _REG_BIT(0x40, 11),
RCC_WWDG = _REG_BIT(0x40, 11),
RCC_SPI2 = _REG_BIT(0x40, 14),
RCC_SPI3 = _REG_BIT(0x40, 15),
RCC_USART2 = _REG_BIT(0x40, 17),
@ -613,7 +613,7 @@ enum rcc_periph_clken {
SCC_TIM12 = _REG_BIT(0x60, 6),
SCC_TIM13 = _REG_BIT(0x60, 7),
SCC_TIM14 = _REG_BIT(0x60, 8),
SCC_WWDG = _REG_BIT(0x60, 11),
SCC_WWDG = _REG_BIT(0x60, 11),
SCC_SPI2 = _REG_BIT(0x60, 14),
SCC_SPI3 = _REG_BIT(0x60, 15),
SCC_USART2 = _REG_BIT(0x60, 17),
@ -686,7 +686,7 @@ enum rcc_periph_rst {
RST_TIM12 = _REG_BIT(0x20, 6),
RST_TIM13 = _REG_BIT(0x20, 7),
RST_TIM14 = _REG_BIT(0x20, 8),
RST_WWDG = _REG_BIT(0x20, 11),
RST_WWDG = _REG_BIT(0x20, 11),
RST_SPI2 = _REG_BIT(0x20, 14),
RST_SPI3 = _REG_BIT(0x20, 15),
RST_USART2 = _REG_BIT(0x20, 17),

6
include/libopencm3/stm32/l1/rcc.h
View File

@ -439,7 +439,7 @@ enum rcc_periph_clken {
RCC_DMA2 = _REG_BIT(0x1c, 25),
RCC_AES = _REG_BIT(0x1c, 27),
RCC_FSMC = _REG_BIT(0x1c, 30),
/* APB2 peripherals */
RCC_SYSCFG = _REG_BIT(0x20, 0),
RCC_TIM9 = _REG_BIT(0x20, 2),
@ -488,7 +488,7 @@ enum rcc_periph_clken {
SCC_DMA2 = _REG_BIT(0x28, 25),
SCC_AES = _REG_BIT(0x28, 27),
SCC_FSMC = _REG_BIT(0x28, 30),
/* APB2 peripherals */
SCC_SYSCFG = _REG_BIT(0x2c, 0),
SCC_TIM9 = _REG_BIT(0x2c, 2),
@ -538,7 +538,7 @@ enum rcc_periph_rst {
RST_DMA2 = _REG_BIT(0x10, 25),
RST_AES = _REG_BIT(0x10, 27),
RST_FSMC = _REG_BIT(0x10, 30),
/* APB2 peripherals */
RST_SYSCFG = _REG_BIT(0x14, 0),
RST_TIM9 = _REG_BIT(0x14, 2),

2
lib/cm3/dwt.c
View File

@ -37,7 +37,7 @@ bool dwt_enable_cycle_counter(void)
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
/* Note TRCENA is for 7M and above*/
SCS_DEMCR |= SCS_DEMCR_TRCENA;
SCS_DEMCR |= SCS_DEMCR_TRCENA;
if (DWT_CTRL & DWT_CTRL_NOCYCCNT) {
return false; /* Not supported in implementation */
}

2
lib/cm3/nvic.c
View File

@ -164,7 +164,7 @@ void nvic_set_priority(uint8_t irqn, uint8_t priority)
}
/* Those are defined only on CM3 or CM4 */
#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
/*---------------------------------------------------------------------------*/
/** @brief NVIC Return Active Interrupt
*

4
lib/cm3/scb.c
View File

@ -22,7 +22,7 @@
#include <libopencm3/cm3/scb.h>
/* Those are defined only on CM3 or CM4 */
#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
void scb_reset_core(void)
{
SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_VECTRESET;
@ -39,7 +39,7 @@ void scb_reset_system(void)
}
/* Those are defined only on CM3 or CM4 */
#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
void scb_set_priority_grouping(uint32_t prigroup)
{
SCB_AIRCR = SCB_AIRCR_VECTKEY | prigroup;

4
lib/cm3/vector.c
View File

@ -44,7 +44,7 @@ vector_table_t vector_table = {
.hard_fault = hard_fault_handler,
/* Those are defined only on CM3 or CM4 */
#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
.memory_manage_fault = mem_manage_handler,
.bus_fault = bus_fault_handler,
.usage_fault = usage_fault_handler,
@ -112,7 +112,7 @@ void null_handler(void)
#pragma weak sys_tick_handler = null_handler
/* Those are defined only on CM3 or CM4 */
#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
#pragma weak mem_manage_handler = blocking_handler
#pragma weak bus_fault_handler = blocking_handler
#pragma weak usage_fault_handler = blocking_handler

756
lib/ethernet/mac_stm32fxx7.c
View File

@ -1,378 +1,378 @@
/** @defgroup ethernet_mac_stm32fxx7_file MAC STM32Fxx7
*
* @ingroup ETH
*
* @brief <b>Ethernet MAC STM32Fxx7 Drivers</b>
*
* @version 1.0.0
* @author @htmlonly &copy; @endhtmlonly 2013 Frantisek Burian <BuFran@seznam.cz>
*
* @date 1 September 2013
*
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#include <string.h>
#include <libopencm3/ethernet/mac.h>
#include <libopencm3/ethernet/phy.h>
#include <libopencm3/stm32/gpio.h>
#include <libopencm3/cm3/nvic.h>
/**@{*/
uint32_t TxBD;
uint32_t RxBD;
/*---------------------------------------------------------------------------*/
/** @brief Set MAC to the PHY
*
* @param[in] mac uint8_t* Desired MAC
*/
void eth_set_mac(uint8_t *mac)
{
ETH_MACAHR(0) = ((uint32_t)mac[5] << 8) | (uint32_t)mac[4] |
ETH_MACA0HR_MACA0H;
ETH_MACALR(0) = ((uint32_t)mac[3] << 24) | ((uint32_t)mac[2] << 16) |
((uint32_t)mac[1] << 8) | mac[0];
}
/*---------------------------------------------------------------------------*/
/** @brief Initialize descriptors
*
* @param[in] buf uint8_t* Buffer for the descriptors
* @param[in] nTx uint32_t Count of Transmit Descriptors
* @param[in] nRx uint32_t Count of Receive Descriptors
* @param[in] cTx uint32_t Bytes in each Transmit Descriptor
* @param[in] cRx uint32_t Bytes in each Receive Descriptor
* @param[in] isext bool true, if extended descriptors should be used
*/
void eth_desc_init(uint8_t *buf, uint32_t nTx, uint32_t nRx, uint32_t cTx,
uint32_t cRx, bool isext)
{
memset(buf, 0, nTx * cTx + nRx * cRx);
uint32_t bd = (uint32_t)buf;
uint32_t sz = isext ? ETH_DES_EXT_SIZE : ETH_DES_STD_SIZE;
/* enable / disable extended frames */
if (isext) {
ETH_DMABMR |= ETH_DMABMR_EDFE;
} else {
ETH_DMABMR &= ~ETH_DMABMR_EDFE;
}
TxBD = bd;
while (--nTx > 0) {
ETH_DES0(bd) = ETH_TDES0_TCH;
ETH_DES2(bd) = bd + sz;
ETH_DES3(bd) = bd + sz + cTx;
bd = ETH_DES3(bd);
}
ETH_DES0(bd) = ETH_TDES0_TCH;
ETH_DES2(bd) = bd + sz;
ETH_DES3(bd) = TxBD;
bd += sz + cTx;
RxBD = bd;
while (--nRx > 0) {
ETH_DES0(bd) = ETH_RDES0_OWN;
ETH_DES1(bd) = ETH_RDES1_RCH | cRx;
ETH_DES2(bd) = bd + sz;
ETH_DES3(bd) = bd + sz + cRx;
bd = ETH_DES3(bd);
}
ETH_DES0(bd) = ETH_RDES0_OWN;
ETH_DES1(bd) = ETH_RDES1_RCH | cRx;
ETH_DES2(bd) = bd + sz;
ETH_DES3(bd) = RxBD;
ETH_DMARDLAR = (uint32_t) RxBD;
ETH_DMATDLAR = (uint32_t) TxBD;
}
/*---------------------------------------------------------------------------*/
/** @brief Transmit packet
*
* @param[in] ppkt uint8_t* Pointer to the beginning of the packet
* @param[in] n uint32_t Size of the packet
* @returns bool true, if success
*/
bool eth_tx(uint8_t *ppkt, uint32_t n)
{
if (ETH_DES0(TxBD) & ETH_TDES0_OWN) {
return false;
}
memcpy((void *)ETH_DES2(TxBD), ppkt, n);
ETH_DES1(TxBD) = n & ETH_TDES1_TBS1;
ETH_DES0(TxBD) |= ETH_TDES0_LS | ETH_TDES0_FS | ETH_TDES0_OWN;
TxBD = ETH_DES3(TxBD);
if (ETH_DMASR & ETH_DMASR_TBUS) {
ETH_DMASR = ETH_DMASR_TBUS;
ETH_DMATPDR = 0;
}
return true;
}
/*---------------------------------------------------------------------------*/
/** @brief Receive packet
*
* @param[inout] ppkt uint8_t* Pointer to the data buffer where to store data
* @param[inout] len uint32_t* Pointer to the variable with the packet length
* @param[in] maxlen uint32_t Maximum length of the packet
* @returns bool true, if the buffer contains readed packet data
*/
bool eth_rx(uint8_t *ppkt, uint32_t *len, uint32_t maxlen)
{
bool fs = false;
bool ls = false;
bool overrun = false;
uint32_t l = 0;
while (!(ETH_DES0(RxBD) & ETH_RDES0_OWN) && !ls) {
l = (ETH_DES0(RxBD) & ETH_RDES0_FL) >> ETH_RDES0_FL_SHIFT;
fs |= ETH_DES0(RxBD) & ETH_RDES0_FS;
ls |= ETH_DES0(RxBD) & ETH_RDES0_LS;
/* frame buffer overrun ?*/
overrun |= fs && (maxlen < l);
if (fs && !overrun) {
memcpy(ppkt, (void *)ETH_DES2(RxBD), l);
ppkt += l;
*len += l;
maxlen -= l;
}
ETH_DES0(RxBD) = ETH_RDES0_OWN;
RxBD = ETH_DES3(RxBD);
}
if (ETH_DMASR & ETH_DMASR_RBUS) {
ETH_DMASR = ETH_DMASR_RBUS;
ETH_DMARPDR = 0;
}
return fs && ls && !overrun;
}
/*---------------------------------------------------------------------------*/
/** @brief Start the Ethernet DMA processing
*/
void eth_start(void)
{
ETH_MACCR |= ETH_MACCR_TE;
ETH_DMAOMR |= ETH_DMAOMR_FTF;
ETH_MACCR |= ETH_MACCR_RE;
ETH_DMAOMR |= ETH_DMAOMR_ST;
ETH_DMAOMR |= ETH_DMAOMR_SR;
}
/*---------------------------------------------------------------------------*/
/** @brief Initialize ethernet
*
* This function will initialize ethernet, set up clocks, and initialize DMA.
*
* @param[in] clock enum eth_clk Core clock speed
*/
void eth_init(enum eth_clk clock)
{
ETH_MACMIIAR = clock;
phy_reset();
ETH_MACCR = ETH_MACCR_CSTF | ETH_MACCR_FES | ETH_MACCR_DM |
ETH_MACCR_APCS | ETH_MACCR_RD;
ETH_MACFFR = ETH_MACFFR_RA | ETH_MACFFR_PM;
ETH_MACHTHR = 0; /* pass all frames */
ETH_MACHTLR = 0;
ETH_MACFCR = (0x100 << ETH_MACFCR_PT_SHIFT);
ETH_MACVLANTR = 0;
ETH_DMAOMR = ETH_DMAOMR_DTCEFD | ETH_DMAOMR_RSF | ETH_DMAOMR_DFRF |
ETH_DMAOMR_TSF | ETH_DMAOMR_FEF | ETH_DMAOMR_OSF;
ETH_DMABMR = ETH_DMABMR_AAB | ETH_DMABMR_FB |
(32 << ETH_DMABMR_RDP_SHIFT) | (32 << ETH_DMABMR_PBL_SHIFT) |
ETH_DMABMR_PM_2_1 | ETH_DMABMR_USP;
}
/*---------------------------------------------------------------------------*/
/** @brief Enable the Ethernet IRQ
*
* @param[in] reason uint32_t Which irq will be enabled
*/
void eth_irq_enable(uint32_t reason)
{
ETH_DMAIER |= reason;
}
/*---------------------------------------------------------------------------*/
/** @brief Disable the Ethernet IRQ
*
* @param[in] reason uint32_t Which irq will be disabled
*/
void eth_irq_disable(uint32_t reason)
{
ETH_DMAIER &= ~reason;
}
/*---------------------------------------------------------------------------*/
/** @brief Check if IRQ is pending
*
* @param[in] reason uint32_t Which irq type has to be tested
* @returns bool true, if IRQ is pending
*/
bool eth_irq_is_pending(uint32_t reason)
{
return (ETH_DMASR & reason) != 0;
}
/*---------------------------------------------------------------------------*/
/** @brief Check if IRQ is pending, and acknowledge it
*
* @param[in] reason uint32_t Which irq type has to be tested
* @returns bool true, if IRQ is pending
*/
bool eth_irq_ack_pending(uint32_t reason)
{
reason &= ETH_DMASR;
ETH_DMASR = reason;
return reason != 0;
}
/*---------------------------------------------------------------------------*/
/** @brief Enable checksum offload feature
*
* This function will enable the Checksum offload feature for all of the
* transmit descriptors. Note to use this feature, descriptors must be in
* extended format.
*/
void eth_enable_checksum_offload(void)
{
uint32_t tab = TxBD;
do {
ETH_DES0(tab) |= ETH_TDES0_CIC_IPPLPH;
tab = ETH_DES3(tab);
}
while (tab != TxBD);
ETH_MACCR |= ETH_MACCR_IPCO;
}
/*---------------------------------------------------------------------------*/
/** @brief Process pending SMI transaction and wait to be done.
*/
static void eth_smi_transact(void)
{
/* Begin transaction. */
ETH_MACMIIAR |= ETH_MACMIIAR_MB;
/* Wait for not busy. */
while (ETH_MACMIIAR & ETH_MACMIIAR_MB);
}
/*---------------------------------------------------------------------------*/
/** @brief Write 16-bit register to the PHY
*
* @param[in] phy uint8_t ID of the PHY (defaults to 1)
* @param[in] reg uint8_t Register address
* @param[in] data uint16_t Data to write
*/
void eth_smi_write(uint8_t phy, uint8_t reg, uint16_t data)
{
/* Write operation MW=1*/
ETH_MACMIIAR = (ETH_MACMIIAR & ETH_MACMIIAR_CR) | /* save clocks */
(phy << ETH_MACMIIAR_PA_SHIFT) |
(reg << ETH_MACMIIAR_MR_SHIFT) |
ETH_MACMIIAR_MW;
ETH_MACMIIDR = data & ETH_MACMIIDR_MD;
eth_smi_transact();
}
/*---------------------------------------------------------------------------*/
/** @brief Read the 16-bit register from the PHY
*
* @param[in] phy uint8_t ID of the PHY (defaults to 1)
* @param[in] reg uint8_t Register address
* @returns uint16_t Readed data
*/
uint16_t eth_smi_read(uint8_t phy, uint8_t reg)
{
/* Read operation MW=0*/
ETH_MACMIIAR = (ETH_MACMIIAR & ETH_MACMIIAR_CR) | /* save clocks */
(phy << ETH_MACMIIAR_PA_SHIFT) |
(reg << ETH_MACMIIAR_MR_SHIFT);
eth_smi_transact();
return (uint16_t)(ETH_MACMIIDR & ETH_MACMIIDR_MD);
}
/*---------------------------------------------------------------------------*/
/** @brief Process the bit-operation on PHY register
*
* @param[in] phy uint8_t ID of the PHY (defaults to 1)
* @param[in] reg uint8_t Register address
* @param[in] bits uint16_t Bits that have to be set (or'ed)
* @param[in] mask uint16_t Bits that have to be clear (and'ed)
*/
void eth_smi_bit_op(uint8_t phy, uint8_t reg, uint16_t bits, uint16_t mask)
{
uint16_t val = eth_smi_read(phy, reg);
eth_smi_write(phy, reg, (val & mask) | bits);
}
/*---------------------------------------------------------------------------*/
/** @brief Clear bits in the register
*
* @param[in] phy uint8_t ID of the PHY (defaults to 1)
* @param[in] reg uint8_t Register address
* @param[in] clearbits uint16_t Bits that have to be cleared
*/
void eth_smi_bit_clear(uint8_t phy, uint8_t reg, uint16_t clearbits)
{
uint16_t val = eth_smi_read(phy, reg);
eth_smi_write(phy, reg, val & (uint16_t)~(clearbits));
}
/*---------------------------------------------------------------------------*/
/** @brief Set bits in the register
*
* @param[in] phy uint8_t ID of the PHY (defaults to 1)
* @param[in] reg uint8_t Register address
* @param[in] bits uint16_t Bits that have to be set (or'ed)
*/
void eth_smi_bit_set(uint8_t phy, uint8_t reg, uint16_t setbits)
{
uint16_t val = eth_smi_read(phy, reg);
eth_smi_write(phy, reg, val | setbits);
}
/*---------------------------------------------------------------------------*/
/**@}*/
/** @defgroup ethernet_mac_stm32fxx7_file MAC STM32Fxx7
*
* @ingroup ETH
*
* @brief <b>Ethernet MAC STM32Fxx7 Drivers</b>
*
* @version 1.0.0
* @author @htmlonly &copy; @endhtmlonly 2013 Frantisek Burian <BuFran@seznam.cz>
*
* @date 1 September 2013
*
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#include <string.h>
#include <libopencm3/ethernet/mac.h>
#include <libopencm3/ethernet/phy.h>
#include <libopencm3/stm32/gpio.h>
#include <libopencm3/cm3/nvic.h>
/**@{*/
uint32_t TxBD;
uint32_t RxBD;
/*---------------------------------------------------------------------------*/
/** @brief Set MAC to the PHY
*
* @param[in] mac uint8_t* Desired MAC
*/
void eth_set_mac(uint8_t *mac)
{
ETH_MACAHR(0) = ((uint32_t)mac[5] << 8) | (uint32_t)mac[4] |
ETH_MACA0HR_MACA0H;
ETH_MACALR(0) = ((uint32_t)mac[3] << 24) | ((uint32_t)mac[2] << 16) |
((uint32_t)mac[1] << 8) | mac[0];
}
/*---------------------------------------------------------------------------*/
/** @brief Initialize descriptors
*
* @param[in] buf uint8_t* Buffer for the descriptors
* @param[in] nTx uint32_t Count of Transmit Descriptors
* @param[in] nRx uint32_t Count of Receive Descriptors
* @param[in] cTx uint32_t Bytes in each Transmit Descriptor
* @param[in] cRx uint32_t Bytes in each Receive Descriptor
* @param[in] isext bool true, if extended descriptors should be used
*/
void eth_desc_init(uint8_t *buf, uint32_t nTx, uint32_t nRx, uint32_t cTx,
uint32_t cRx, bool isext)
{
memset(buf, 0, nTx * cTx + nRx * cRx);
uint32_t bd = (uint32_t)buf;
uint32_t sz = isext ? ETH_DES_EXT_SIZE : ETH_DES_STD_SIZE;
/* enable / disable extended frames */
if (isext) {
ETH_DMABMR |= ETH_DMABMR_EDFE;
} else {
ETH_DMABMR &= ~ETH_DMABMR_EDFE;
}
TxBD = bd;
while (--nTx > 0) {
ETH_DES0(bd) = ETH_TDES0_TCH;
ETH_DES2(bd) = bd + sz;
ETH_DES3(bd) = bd + sz + cTx;
bd = ETH_DES3(bd);
}
ETH_DES0(bd) = ETH_TDES0_TCH;
ETH_DES2(bd) = bd + sz;
ETH_DES3(bd) = TxBD;
bd += sz + cTx;
RxBD = bd;
while (--nRx > 0) {
ETH_DES0(bd) = ETH_RDES0_OWN;
ETH_DES1(bd) = ETH_RDES1_RCH | cRx;
ETH_DES2(bd) = bd + sz;
ETH_DES3(bd) = bd + sz + cRx;
bd = ETH_DES3(bd);
}
ETH_DES0(bd) = ETH_RDES0_OWN;
ETH_DES1(bd) = ETH_RDES1_RCH | cRx;
ETH_DES2(bd) = bd + sz;
ETH_DES3(bd) = RxBD;
ETH_DMARDLAR = (uint32_t) RxBD;
ETH_DMATDLAR = (uint32_t) TxBD;
}
/*---------------------------------------------------------------------------*/
/** @brief Transmit packet
*
* @param[in] ppkt uint8_t* Pointer to the beginning of the packet
* @param[in] n uint32_t Size of the packet
* @returns bool true, if success
*/
bool eth_tx(uint8_t *ppkt, uint32_t n)
{
if (ETH_DES0(TxBD) & ETH_TDES0_OWN) {
return false;
}
memcpy((void *)ETH_DES2(TxBD), ppkt, n);
ETH_DES1(TxBD) = n & ETH_TDES1_TBS1;
ETH_DES0(TxBD) |= ETH_TDES0_LS | ETH_TDES0_FS | ETH_TDES0_OWN;
TxBD = ETH_DES3(TxBD);
if (ETH_DMASR & ETH_DMASR_TBUS) {
ETH_DMASR = ETH_DMASR_TBUS;
ETH_DMATPDR = 0;
}
return true;
}
/*---------------------------------------------------------------------------*/
/** @brief Receive packet
*
* @param[inout] ppkt uint8_t* Pointer to the data buffer where to store data
* @param[inout] len uint32_t* Pointer to the variable with the packet length
* @param[in] maxlen uint32_t Maximum length of the packet
* @returns bool true, if the buffer contains readed packet data
*/
bool eth_rx(uint8_t *ppkt, uint32_t *len, uint32_t maxlen)
{
bool fs = false;
bool ls = false;
bool overrun = false;
uint32_t l = 0;
while (!(ETH_DES0(RxBD) & ETH_RDES0_OWN) && !ls) {
l = (ETH_DES0(RxBD) & ETH_RDES0_FL) >> ETH_RDES0_FL_SHIFT;
fs |= ETH_DES0(RxBD) & ETH_RDES0_FS;
ls |= ETH_DES0(RxBD) & ETH_RDES0_LS;
/* frame buffer overrun ?*/
overrun |= fs && (maxlen < l);
if (fs && !overrun) {
memcpy(ppkt, (void *)ETH_DES2(RxBD), l);
ppkt += l;
*len += l;
maxlen -= l;
}
ETH_DES0(RxBD) = ETH_RDES0_OWN;
RxBD = ETH_DES3(RxBD);
}
if (ETH_DMASR & ETH_DMASR_RBUS) {
ETH_DMASR = ETH_DMASR_RBUS;
ETH_DMARPDR = 0;
}
return fs && ls && !overrun;
}
/*---------------------------------------------------------------------------*/
/** @brief Start the Ethernet DMA processing
*/
void eth_start(void)
{
ETH_MACCR |= ETH_MACCR_TE;
ETH_DMAOMR |= ETH_DMAOMR_FTF;
ETH_MACCR |= ETH_MACCR_RE;
ETH_DMAOMR |= ETH_DMAOMR_ST;
ETH_DMAOMR |= ETH_DMAOMR_SR;
}
/*---------------------------------------------------------------------------*/
/** @brief Initialize ethernet
*
* This function will initialize ethernet, set up clocks, and initialize DMA.
*
* @param[in] clock enum eth_clk Core clock speed
*/
void eth_init(enum eth_clk clock)
{
ETH_MACMIIAR = clock;
phy_reset();
ETH_MACCR = ETH_MACCR_CSTF | ETH_MACCR_FES | ETH_MACCR_DM |
ETH_MACCR_APCS | ETH_MACCR_RD;
ETH_MACFFR = ETH_MACFFR_RA | ETH_MACFFR_PM;
ETH_MACHTHR = 0; /* pass all frames */
ETH_MACHTLR = 0;
ETH_MACFCR = (0x100 << ETH_MACFCR_PT_SHIFT);
ETH_MACVLANTR = 0;
ETH_DMAOMR = ETH_DMAOMR_DTCEFD | ETH_DMAOMR_RSF | ETH_DMAOMR_DFRF |
ETH_DMAOMR_TSF | ETH_DMAOMR_FEF | ETH_DMAOMR_OSF;
ETH_DMABMR = ETH_DMABMR_AAB | ETH_DMABMR_FB |
(32 << ETH_DMABMR_RDP_SHIFT) | (32 << ETH_DMABMR_PBL_SHIFT) |
ETH_DMABMR_PM_2_1 | ETH_DMABMR_USP;
}
/*---------------------------------------------------------------------------*/
/** @brief Enable the Ethernet IRQ
*
* @param[in] reason uint32_t Which irq will be enabled
*/
void eth_irq_enable(uint32_t reason)
{
ETH_DMAIER |= reason;
}
/*---------------------------------------------------------------------------*/
/** @brief Disable the Ethernet IRQ
*
* @param[in] reason uint32_t Which irq will be disabled
*/
void eth_irq_disable(uint32_t reason)
{
ETH_DMAIER &= ~reason;
}
/*---------------------------------------------------------------------------*/
/** @brief Check if IRQ is pending
*
* @param[in] reason uint32_t Which irq type has to be tested
* @returns bool true, if IRQ is pending
*/
bool eth_irq_is_pending(uint32_t reason)
{
return (ETH_DMASR & reason) != 0;
}
/*---------------------------------------------------------------------------*/
/** @brief Check if IRQ is pending, and acknowledge it
*
* @param[in] reason uint32_t Which irq type has to be tested
* @returns bool true, if IRQ is pending
*/
bool eth_irq_ack_pending(uint32_t reason)
{
reason &= ETH_DMASR;
ETH_DMASR = reason;
return reason != 0;
}
/*---------------------------------------------------------------------------*/
/** @brief Enable checksum offload feature
*
* This function will enable the Checksum offload feature for all of the
* transmit descriptors. Note to use this feature, descriptors must be in
* extended format.
*/
void eth_enable_checksum_offload(void)
{
uint32_t tab = TxBD;
do {
ETH_DES0(tab) |= ETH_TDES0_CIC_IPPLPH;
tab = ETH_DES3(tab);
}
while (tab != TxBD);
ETH_MACCR |= ETH_MACCR_IPCO;
}
/*---------------------------------------------------------------------------*/
/** @brief Process pending SMI transaction and wait to be done.
*/
static void eth_smi_transact(void)
{
/* Begin transaction. */
ETH_MACMIIAR |= ETH_MACMIIAR_MB;
/* Wait for not busy. */
while (ETH_MACMIIAR & ETH_MACMIIAR_MB);
}
/*---------------------------------------------------------------------------*/
/** @brief Write 16-bit register to the PHY
*
* @param[in] phy uint8_t ID of the PHY (defaults to 1)
* @param[in] reg uint8_t Register address
* @param[in] data uint16_t Data to write
*/
void eth_smi_write(uint8_t phy, uint8_t reg, uint16_t data)
{
/* Write operation MW=1*/
ETH_MACMIIAR = (ETH_MACMIIAR & ETH_MACMIIAR_CR) | /* save clocks */
(phy << ETH_MACMIIAR_PA_SHIFT) |
(reg << ETH_MACMIIAR_MR_SHIFT) |
ETH_MACMIIAR_MW;
ETH_MACMIIDR = data & ETH_MACMIIDR_MD;
eth_smi_transact();
}
/*---------------------------------------------------------------------------*/
/** @brief Read the 16-bit register from the PHY
*
* @param[in] phy uint8_t ID of the PHY (defaults to 1)
* @param[in] reg uint8_t Register address
* @returns uint16_t Readed data
*/
uint16_t eth_smi_read(uint8_t phy, uint8_t reg)
{
/* Read operation MW=0*/
ETH_MACMIIAR = (ETH_MACMIIAR & ETH_MACMIIAR_CR) | /* save clocks */
(phy << ETH_MACMIIAR_PA_SHIFT) |
(reg << ETH_MACMIIAR_MR_SHIFT);
eth_smi_transact();
return (uint16_t)(ETH_MACMIIDR & ETH_MACMIIDR_MD);
}
/*---------------------------------------------------------------------------*/
/** @brief Process the bit-operation on PHY register
*
* @param[in] phy uint8_t ID of the PHY (defaults to 1)
* @param[in] reg uint8_t Register address
* @param[in] bits uint16_t Bits that have to be set (or'ed)
* @param[in] mask uint16_t Bits that have to be clear (and'ed)
*/
void eth_smi_bit_op(uint8_t phy, uint8_t reg, uint16_t bits, uint16_t mask)
{
uint16_t val = eth_smi_read(phy, reg);
eth_smi_write(phy, reg, (val & mask) | bits);
}
/*---------------------------------------------------------------------------*/
/** @brief Clear bits in the register
*
* @param[in] phy uint8_t ID of the PHY (defaults to 1)
* @param[in] reg uint8_t Register address
* @param[in] clearbits uint16_t Bits that have to be cleared
*/
void eth_smi_bit_clear(uint8_t phy, uint8_t reg, uint16_t clearbits)
{
uint16_t val = eth_smi_read(phy, reg);
eth_smi_write(phy, reg, val & (uint16_t)~(clearbits));
}
/*---------------------------------------------------------------------------*/
/** @brief Set bits in the register
*
* @param[in] phy uint8_t ID of the PHY (defaults to 1)
* @param[in] reg uint8_t Register address
* @param[in] bits uint16_t Bits that have to be set (or'ed)
*/
void eth_smi_bit_set(uint8_t phy, uint8_t reg, uint16_t setbits)
{
uint16_t val = eth_smi_read(phy, reg);
eth_smi_write(phy, reg, val | setbits);
}
/*---------------------------------------------------------------------------*/
/**@}*/

128
lib/ethernet/phy.c
View File

@ -1,64 +1,64 @@
/** @defgroup ethernet_phy_file PHY Generic Drivers
*
* @ingroup ETH
*
* @brief <b>Ethernet PHY Generic Drivers</b>
*
* @version 1.0.0
* @author @htmlonly &copy; @endhtmlonly 2013 Frantisek Burian <BuFran@seznam.cz>
*
* @date 1 September 2013
*
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#include <libopencm3/ethernet/mac.h>
#include <libopencm3/ethernet/phy.h>
/**@{*/
/*---------------------------------------------------------------------------*/
/** @brief Is the link up ?
*
* @returns bool true, if link is up
*/
bool phy_link_isup(void)
{
return eth_smi_read(1, PHY_REG_BSR) & PHY_REG_BSR_UP;
}
/*---------------------------------------------------------------------------*/
/** @brief Reset the PHY
*
* Reset the PHY chip and wait for done
*/
void phy_reset(void)
{
eth_smi_write(1, PHY_REG_BCR, PHY_REG_BCR_RESET);
while (eth_smi_read(1, PHY_REG_BCR) & PHY_REG_BCR_RESET);
}
/*---------------------------------------------------------------------------*/
/**@}*/
/** @defgroup ethernet_phy_file PHY Generic Drivers
*
* @ingroup ETH
*
* @brief <b>Ethernet PHY Generic Drivers</b>
*
* @version 1.0.0
* @author @htmlonly &copy; @endhtmlonly 2013 Frantisek Burian <BuFran@seznam.cz>
*
* @date 1 September 2013
*
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#include <libopencm3/ethernet/mac.h>
#include <libopencm3/ethernet/phy.h>
/**@{*/
/*---------------------------------------------------------------------------*/
/** @brief Is the link up ?
*
* @returns bool true, if link is up
*/
bool phy_link_isup(void)
{
return eth_smi_read(1, PHY_REG_BSR) & PHY_REG_BSR_UP;
}
/*---------------------------------------------------------------------------*/
/** @brief Reset the PHY
*
* Reset the PHY chip and wait for done
*/
void phy_reset(void)
{
eth_smi_write(1, PHY_REG_BCR, PHY_REG_BCR_RESET);
while (eth_smi_read(1, PHY_REG_BCR) & PHY_REG_BCR_RESET);
}
/*---------------------------------------------------------------------------*/
/**@}*/

178
lib/ethernet/phy_ksz8051mll.c
View File

@ -1,89 +1,89 @@
/** @defgroup ethernet_phy_ksz8051mll_file PHY KSZ8051MLL
*
* @ingroup ETH
*
* @brief <b>Ethernet PHY STM32Fxx7 Drivers</b>
*
* @version 1.0.0
* @author @htmlonly &copy; @endhtmlonly 2013 Frantisek Burian <BuFran@seznam.cz>
*
* @date 1 September 2013
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#include <libopencm3/ethernet/mac.h>
#include <libopencm3/ethernet/phy.h>
#include <libopencm3/ethernet/phy_ksz8051mll.h>
/**@{*/
/*---------------------------------------------------------------------------*/
/** @brief Get the current link status
*
* Retrieve the link speed and duplex status of the link.
*
* @returns ::phy_status Link status
*/
enum phy_status phy_link_status(void)
{
return eth_smi_read(1, PHY_REG_CR1) & 0x07;
}
/*---------------------------------------------------------------------------*/
/** @brief Force autonegotiation
*
* Force the autonegotiation and set link speed and duplex mode of the link
*
* @param[in] mode enum phy_status Desired link status
*/
void phy_autoneg_force(enum phy_status mode)
{
uint16_t bst = 0;
if ((mode == LINK_FD_10M) || (mode == LINK_FD_100M) ||
(mode == LINK_FD_1000M) || (mode == LINK_FD_10000M)) {
bst |= PHY_REG_BCR_FD;
}
if ((mode == LINK_FD_100M) || (mode == LINK_FD_100M)) {
bst |= PHY_REG_BCR_100M;
}
eth_smi_bit_op(1, PHY_REG_BCR, bst,
~(PHY_REG_BCR_AN | PHY_REG_BCR_100M | PHY_REG_BCR_FD));
}
/*---------------------------------------------------------------------------*/
/** @brief Enable the autonegotiation
*
* Enable the autonegotiation of the link speed and duplex mode
*/
void phy_autoneg_enable(void)
{
eth_smi_bit_set(1, PHY_REG_BCR, PHY_REG_BCR_AN | PHY_REG_BCR_ANRST);
}
/*---------------------------------------------------------------------------*/
/**@}*/
/** @defgroup ethernet_phy_ksz8051mll_file PHY KSZ8051MLL
*
* @ingroup ETH
*
* @brief <b>Ethernet PHY STM32Fxx7 Drivers</b>
*
* @version 1.0.0
* @author @htmlonly &copy; @endhtmlonly 2013 Frantisek Burian <BuFran@seznam.cz>
*
* @date 1 September 2013
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#include <libopencm3/ethernet/mac.h>
#include <libopencm3/ethernet/phy.h>
#include <libopencm3/ethernet/phy_ksz8051mll.h>
/**@{*/
/*---------------------------------------------------------------------------*/
/** @brief Get the current link status
*
* Retrieve the link speed and duplex status of the link.
*
* @returns ::phy_status Link status
*/
enum phy_status phy_link_status(void)
{
return eth_smi_read(1, PHY_REG_CR1) & 0x07;
}
/*---------------------------------------------------------------------------*/
/** @brief Force autonegotiation
*
* Force the autonegotiation and set link speed and duplex mode of the link
*
* @param[in] mode enum phy_status Desired link status
*/
void phy_autoneg_force(enum phy_status mode)
{
uint16_t bst = 0;
if ((mode == LINK_FD_10M) || (mode == LINK_FD_100M) ||
(mode == LINK_FD_1000M) || (mode == LINK_FD_10000M)) {
bst |= PHY_REG_BCR_FD;
}
if ((mode == LINK_FD_100M) || (mode == LINK_FD_100M)) {
bst |= PHY_REG_BCR_100M;
}
eth_smi_bit_op(1, PHY_REG_BCR, bst,
~(PHY_REG_BCR_AN | PHY_REG_BCR_100M | PHY_REG_BCR_FD));
}
/*---------------------------------------------------------------------------*/
/** @brief Enable the autonegotiation
*
* Enable the autonegotiation of the link speed and duplex mode
*/
void phy_autoneg_enable(void)
{
eth_smi_bit_set(1, PHY_REG_BCR, PHY_REG_BCR_AN | PHY_REG_BCR_ANRST);
}
/*---------------------------------------------------------------------------*/
/**@}*/

2
lib/stm32/common/exti_common_all.c
View File

@ -110,7 +110,7 @@ void exti_select_source(uint32_t exti, uint32_t gpioport)
case GPIOD:
bits = 3;
break;
#if defined(GPIOE) && defined(GPIO_PORT_E_BASE)
#if defined(GPIOE) && defined(GPIO_PORT_E_BASE)
case GPIOE:
bits = 4;
break;

23
lib/stm32/common/rcc_common_all.c
View File

@ -17,15 +17,15 @@
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#include <libopencm3/stm32/rcc.h>
/*---------------------------------------------------------------------------*/
/** @brief RCC Enable Peripheral Clocks.
*
* Enable the clock on particular peripherals. There are three registers
* involved, each one controlling the enabling of clocks associated with the
* AHB, APB1 and APB2 respectively. Several peripherals could be enabled
* Enable the clock on particular peripherals. There are three registers
* involved, each one controlling the enabling of clocks associated with the
* AHB, APB1 and APB2 respectively. Several peripherals could be enabled
* simultaneously <em>only if they are controlled by the same register</em>.
*
* @param[in] *reg Unsigned int32. Pointer to a Clock Enable Register
@ -45,9 +45,9 @@ void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en)
/*---------------------------------------------------------------------------*/
/** @brief RCC Disable Peripheral Clocks.
*
* Enable the clock on particular peripherals. There are three registers
* involved, each one controlling the enabling of clocks associated with
* the AHB, APB1 and APB2 respectively. Several peripherals could be disabled
* Enable the clock on particular peripherals. There are three registers
* involved, each one controlling the enabling of clocks associated with
* the AHB, APB1 and APB2 respectively. Several peripherals could be disabled
* simultaneously <em>only if they are controlled by the same register</em>.
*
* @param[in] *reg Unsigned int32. Pointer to a Clock Enable Register
@ -70,7 +70,7 @@ void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en)
* controlling reset of peripherals associated with the AHB, APB1 and APB2
* respectively. Several peripherals could be reset simultaneously <em>only if
* they are controlled by the same register</em>.
*
*
* @param[in] *reg Unsigned int32. Pointer to a Reset Register
* (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
* @param[in] reset Unsigned int32. Logical OR of all resets.
@ -93,7 +93,8 @@ void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset)
*
* @param[in] *reg Unsigned int32. Pointer to a Reset Register
* (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
* @param[in] clear_reset Unsigned int32. Logical OR of all resets to be removed:
* @param[in] clear_reset Unsigned int32. Logical OR of all resets to be
* removed:
* @li If register is RCC_AHBRSTR, from @ref rcc_ahbrstr_rst
* @li If register is RCC_APB1RSTR, from @ref rcc_apb1rstr_rst
* @li If register is RCC_APB2RSTR, from @ref rcc_apb2rstr_rst
@ -115,7 +116,7 @@ void rcc_peripheral_clear_reset(volatile uint32_t *reg, uint32_t clear_reset)
*
* For available constants, see #periph_t (RCC_UART1 for example)
*/
void rcc_periph_clock_enable(enum rcc_periph_clken clken)
{
_RCC_REG(clken) |= _RCC_BIT(clken);
@ -182,4 +183,4 @@ void rcc_periph_reset_release(enum rcc_periph_rst rst)
}
#undef _RCC_REG
#undef _RCC_BIT
#undef _RCC_BIT

2
lib/stm32/f0/adc.c
View File

@ -788,7 +788,7 @@ void adc_enable_analog_watchdog_on_all_channels(uint32_t adc)
void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, uint8_t chan)
{
ADC_CFGR1(adc) = (ADC_CFGR1(adc) & ~ADC_CFGR1_AWDCH) | \
ADC_CFGR1(adc) = (ADC_CFGR1(adc) & ~ADC_CFGR1_AWDCH) |
ADC_CFGR1_AWDCH_VAL(chan);
ADC_CFGR1(adc) |= ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL;

2
lib/stm32/f0/rcc.c
View File

@ -250,7 +250,7 @@ void rcc_osc_on(enum rcc_osc osc)
RCC_CSR |= RCC_CSR_LSION;
break;
case PLL:
RCC_CR|=RCC_CR_PLLON;
RCC_CR |= RCC_CR_PLLON;
break;
}
}