Added convenience funcions for timer input capture filter and prescaler.
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@ -851,6 +851,42 @@ enum tim_oc_mode {
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TIM_OCM_PWM2,
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};
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/* Input Capture channel designators */
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enum tim_ic_id {
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TIM_IC1,
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TIM_IC2,
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TIM_IC3,
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TIM_IC4,
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};
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/* Input Capture input filter */
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enum tim_ic_filter {
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TIM_IC_OFF,
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TIM_IC_CK_INT_N_2,
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TIM_IC_CK_INT_N_4,
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TIM_IC_CK_INT_N_8,
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TIM_IC_DTF_DIV_2_N_6,
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TIM_IC_DTF_DIV_2_N_8,
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TIM_IC_DTF_DIV_4_N_6,
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TIM_IC_DTF_DIV_4_N_8,
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TIM_IC_DTF_DIV_8_N_6,
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TIM_IC_DTF_DIV_8_N_8,
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TIM_IC_DTF_DIV_16_N_5,
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TIM_IC_DTF_DIV_16_N_6,
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TIM_IC_DTF_DIV_16_N_8,
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TIM_IC_DTF_DIV_32_N_5,
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TIM_IC_DTF_DIV_32_N_6,
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TIM_IC_DTF_DIV_32_N_8,
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};
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/* Input Capture input prescaler */
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enum tim_ic_psc {
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TIM_IC_PSC_OFF,
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TIM_IC_PSC_2,
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TIM_IC_PSC_4,
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TIM_IC_PSC_8,
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};
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/* --- TIM functions ------------------------------------------------------- */
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void timer_reset(u32 timer_peripheral);
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void timer_enable_irq(u32 timer_peripheral, u32 irq);
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@ -918,4 +954,7 @@ void timer_set_deadtime(u32 timer_peripheral, u32 deadtime);
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void timer_generate_event(u32 timer_peripheral, u32 event);
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u32 timer_get_counter(u32 timer_peripheral);
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void timer_ic_set_filter(u32 timer, enum tim_ic_id ic, enum tim_ic_filter flt);
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void timer_ic_set_prescaler(u32 timer, enum tim_ic_id ic, enum tim_ic_psc psc);
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#endif
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@ -914,3 +914,48 @@ u32 timer_get_counter(u32 timer_peripheral)
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{
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return TIM_CNT(timer_peripheral);
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}
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void timer_ic_set_filter(u32 timer, enum tim_ic_id ic, enum tim_ic_filter flt)
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{
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switch (ic) {
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case TIM_IC1:
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TIM_CCMR1(timer) &= ~TIM_CCMR1_IC1F_MASK;
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TIM_CCMR1(timer) |= flt << 4;
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break;
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case TIM_IC2:
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TIM_CCMR1(timer) &= ~TIM_CCMR1_IC2F_MASK;
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TIM_CCMR1(timer) |= flt << 12;
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break;
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case TIM_IC3:
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TIM_CCMR2(timer) &= ~TIM_CCMR2_IC3F_MASK;
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TIM_CCMR2(timer) |= flt << 4;
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break;
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case TIM_IC4:
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TIM_CCMR2(timer) &= ~TIM_CCMR2_IC4F_MASK;
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TIM_CCMR2(timer) |= flt << 12;
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break;
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}
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}
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void timer_ic_set_prescaler(u32 timer, enum tim_ic_id ic, enum tim_ic_psc psc)
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{
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switch (ic) {
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case TIM_IC1:
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TIM_CCMR1(timer) &= ~TIM_CCMR1_IC1PSC_MASK;
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TIM_CCMR1(timer) |= psc << 2;
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break;
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case TIM_IC2:
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TIM_CCMR1(timer) &= ~TIM_CCMR1_IC2PSC_MASK;
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TIM_CCMR1(timer) |= psc << 10;
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break;
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case TIM_IC3:
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TIM_CCMR2(timer) &= ~TIM_CCMR2_IC3PSC_MASK;
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TIM_CCMR2(timer) |= psc << 4;
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break;
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case TIM_IC4:
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TIM_CCMR2(timer) &= ~TIM_CCMR2_IC4PSC_MASK;
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TIM_CCMR2(timer) |= psc << 10;
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break;
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}
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}
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