diff --git a/include/libopencm3/stm32/timer.h b/include/libopencm3/stm32/timer.h
index 54cc2284..836e0641 100644
--- a/include/libopencm3/stm32/timer.h
+++ b/include/libopencm3/stm32/timer.h
@@ -851,6 +851,42 @@ enum tim_oc_mode {
 	TIM_OCM_PWM2,
 };
 
+/* Input Capture channel designators */
+enum tim_ic_id {
+	TIM_IC1,
+	TIM_IC2,
+	TIM_IC3,
+	TIM_IC4,
+};
+
+/* Input Capture input filter */
+enum tim_ic_filter {
+	TIM_IC_OFF,
+	TIM_IC_CK_INT_N_2,
+	TIM_IC_CK_INT_N_4,
+	TIM_IC_CK_INT_N_8,
+	TIM_IC_DTF_DIV_2_N_6,
+	TIM_IC_DTF_DIV_2_N_8,
+	TIM_IC_DTF_DIV_4_N_6,
+	TIM_IC_DTF_DIV_4_N_8,
+	TIM_IC_DTF_DIV_8_N_6,
+	TIM_IC_DTF_DIV_8_N_8,
+	TIM_IC_DTF_DIV_16_N_5,
+	TIM_IC_DTF_DIV_16_N_6,
+	TIM_IC_DTF_DIV_16_N_8,
+	TIM_IC_DTF_DIV_32_N_5,
+	TIM_IC_DTF_DIV_32_N_6,
+	TIM_IC_DTF_DIV_32_N_8,
+};
+
+/* Input Capture input prescaler */
+enum tim_ic_psc {
+	TIM_IC_PSC_OFF,
+	TIM_IC_PSC_2,
+	TIM_IC_PSC_4,
+	TIM_IC_PSC_8,
+};
+
 /* --- TIM functions ------------------------------------------------------- */
 void timer_reset(u32 timer_peripheral);
 void timer_enable_irq(u32 timer_peripheral, u32 irq);
@@ -918,4 +954,7 @@ void timer_set_deadtime(u32 timer_peripheral, u32 deadtime);
 void timer_generate_event(u32 timer_peripheral, u32 event);
 u32 timer_get_counter(u32 timer_peripheral);
 
+void timer_ic_set_filter(u32 timer, enum tim_ic_id ic, enum tim_ic_filter flt);
+void timer_ic_set_prescaler(u32 timer, enum tim_ic_id ic, enum tim_ic_psc psc);
+
 #endif
diff --git a/lib/stm32/f1/timer.c b/lib/stm32/f1/timer.c
index 85f81ea4..8303f890 100644
--- a/lib/stm32/f1/timer.c
+++ b/lib/stm32/f1/timer.c
@@ -914,3 +914,48 @@ u32 timer_get_counter(u32 timer_peripheral)
 {
 	return TIM_CNT(timer_peripheral);
 }
+
+void timer_ic_set_filter(u32 timer, enum tim_ic_id ic, enum tim_ic_filter flt)
+{
+	switch (ic) {
+	case TIM_IC1:
+		TIM_CCMR1(timer) &= ~TIM_CCMR1_IC1F_MASK;
+		TIM_CCMR1(timer) |= flt << 4;
+		break;
+	case TIM_IC2:
+		TIM_CCMR1(timer) &= ~TIM_CCMR1_IC2F_MASK;
+		TIM_CCMR1(timer) |= flt << 12;
+		break;
+	case TIM_IC3:
+		TIM_CCMR2(timer) &= ~TIM_CCMR2_IC3F_MASK;
+		TIM_CCMR2(timer) |= flt << 4;
+		break;
+	case TIM_IC4:
+		TIM_CCMR2(timer) &= ~TIM_CCMR2_IC4F_MASK;
+		TIM_CCMR2(timer) |= flt << 12;
+		break;
+	}
+}
+
+void timer_ic_set_prescaler(u32 timer, enum tim_ic_id ic, enum tim_ic_psc psc)
+{
+	switch (ic) {
+	case TIM_IC1:
+		TIM_CCMR1(timer) &= ~TIM_CCMR1_IC1PSC_MASK;
+		TIM_CCMR1(timer) |= psc << 2;
+		break;
+	case TIM_IC2:
+		TIM_CCMR1(timer) &= ~TIM_CCMR1_IC2PSC_MASK;
+		TIM_CCMR1(timer) |= psc << 10;
+		break;
+	case TIM_IC3:
+		TIM_CCMR2(timer) &= ~TIM_CCMR2_IC3PSC_MASK;
+		TIM_CCMR2(timer) |= psc << 4;
+		break;
+	case TIM_IC4:
+		TIM_CCMR2(timer) &= ~TIM_CCMR2_IC4PSC_MASK;
+		TIM_CCMR2(timer) |= psc << 10;
+		break;
+	}
+}
+