stm32f2+: flash: Rename FLASH_ACR_XCE -> FLASH_ACR_XCEN
Match the datasheet register names better. squish into xcev
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b40c72828d
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6798cee2a5
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@ -51,8 +51,8 @@
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#define FLASH_ACR_DCRST (1 << 12)
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#define FLASH_ACR_ICRST (1 << 11)
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#define FLASH_ACR_DCE (1 << 10)
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#define FLASH_ACR_ICE (1 << 9)
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#define FLASH_ACR_DCEN (1 << 10)
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#define FLASH_ACR_ICEN (1 << 9)
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#define FLASH_ACR_PRFTEN (1 << 8)
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/* --- FLASH_SR values ----------------------------------------------------- */
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@ -147,4 +147,3 @@ END_DECLS
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#warning "only via flash.h"
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#endif
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/** @endcond */
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@ -48,7 +48,7 @@ static inline void flash_set_program_size(uint32_t psize)
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void flash_dcache_enable(void)
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{
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FLASH_ACR |= FLASH_ACR_DCE;
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FLASH_ACR |= FLASH_ACR_DCEN;
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}
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/*---------------------------------------------------------------------------*/
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@ -58,7 +58,7 @@ void flash_dcache_enable(void)
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void flash_dcache_disable(void)
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{
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FLASH_ACR &= ~FLASH_ACR_DCE;
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FLASH_ACR &= ~FLASH_ACR_DCEN;
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}
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/*---------------------------------------------------------------------------*/
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@ -68,7 +68,7 @@ void flash_dcache_disable(void)
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void flash_icache_enable(void)
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{
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FLASH_ACR |= FLASH_ACR_ICE;
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FLASH_ACR |= FLASH_ACR_ICEN;
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}
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/*---------------------------------------------------------------------------*/
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@ -78,7 +78,7 @@ void flash_icache_enable(void)
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void flash_icache_disable(void)
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{
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FLASH_ACR &= ~FLASH_ACR_ICE;
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FLASH_ACR &= ~FLASH_ACR_ICEN;
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}
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/*---------------------------------------------------------------------------*/
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@ -412,4 +412,3 @@ void flash_program_option_bytes(uint32_t data)
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flash_wait_for_last_operation();
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}
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/**@}*/
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@ -57,7 +57,7 @@ const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = {
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
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FLASH_ACR_LATENCY_3WS,
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.apb1_frequency = 30000000,
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.apb2_frequency = 60000000,
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@ -60,7 +60,7 @@ const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = {
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.power_save = 1,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
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FLASH_ACR_LATENCY_3WS,
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.ahb_frequency = 48000000,
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.apb1_frequency = 12000000,
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@ -75,7 +75,7 @@ const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = {
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_2,
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.ppre2 = RCC_CFGR_PPRE_DIV_NONE,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
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FLASH_ACR_LATENCY_2WS,
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.ahb_frequency = 84000000,
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.apb1_frequency = 42000000,
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@ -91,7 +91,7 @@ const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = {
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.power_save = 1,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
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FLASH_ACR_LATENCY_3WS,
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.ahb_frequency = 120000000,
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.apb1_frequency = 30000000,
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@ -106,7 +106,7 @@ const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = {
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
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FLASH_ACR_LATENCY_5WS,
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.ahb_frequency = 168000000,
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.apb1_frequency = 42000000,
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@ -125,7 +125,7 @@ const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = {
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.power_save = 1,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
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FLASH_ACR_LATENCY_3WS,
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.ahb_frequency = 48000000,
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.apb1_frequency = 12000000,
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@ -140,7 +140,7 @@ const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = {
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_2,
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.ppre2 = RCC_CFGR_PPRE_DIV_NONE,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
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FLASH_ACR_LATENCY_2WS,
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.ahb_frequency = 84000000,
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.apb1_frequency = 42000000,
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@ -156,7 +156,7 @@ const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = {
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.power_save = 1,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
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FLASH_ACR_LATENCY_3WS,
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.ahb_frequency = 120000000,
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.apb1_frequency = 30000000,
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@ -171,7 +171,7 @@ const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = {
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
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FLASH_ACR_LATENCY_5WS,
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.ahb_frequency = 168000000,
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.apb1_frequency = 42000000,
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@ -190,7 +190,7 @@ const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = {
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.power_save = 1,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
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FLASH_ACR_LATENCY_3WS,
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.ahb_frequency = 48000000,
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.apb1_frequency = 12000000,
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@ -205,7 +205,7 @@ const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = {
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_2,
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.ppre2 = RCC_CFGR_PPRE_DIV_NONE,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
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FLASH_ACR_LATENCY_2WS,
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.ahb_frequency = 84000000,
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.apb1_frequency = 42000000,
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@ -221,7 +221,7 @@ const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = {
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.power_save = 1,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
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FLASH_ACR_LATENCY_3WS,
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.ahb_frequency = 120000000,
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.apb1_frequency = 30000000,
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@ -236,7 +236,7 @@ const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = {
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
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FLASH_ACR_LATENCY_5WS,
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.ahb_frequency = 168000000,
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.apb1_frequency = 42000000,
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@ -255,7 +255,7 @@ const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = {
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.power_save = 1,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
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FLASH_ACR_LATENCY_3WS,
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.ahb_frequency = 48000000,
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.apb1_frequency = 12000000,
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@ -270,7 +270,7 @@ const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = {
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_2,
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.ppre2 = RCC_CFGR_PPRE_DIV_NONE,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
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FLASH_ACR_LATENCY_2WS,
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.ahb_frequency = 84000000,
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.apb1_frequency = 42000000,
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@ -286,7 +286,7 @@ const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = {
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.power_save = 1,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
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FLASH_ACR_LATENCY_3WS,
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.ahb_frequency = 120000000,
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.apb1_frequency = 30000000,
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@ -301,7 +301,7 @@ const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = {
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
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FLASH_ACR_LATENCY_5WS,
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.ahb_frequency = 168000000,
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.apb1_frequency = 42000000,
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@ -15,7 +15,7 @@ const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = {
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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.flash_config = FLASH_ACR_ICEN | FLASH_ACR_DCEN |
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FLASH_ACR_LATENCY_7WS,
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.apb1_frequency = 108000000,
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.apb2_frequency = 216000000,
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